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6#include <common.h>
7#include <command.h>
8#include <env.h>
9#include <fdt_support.h>
10#include <image.h>
11#include <init.h>
12#include <netdev.h>
13#include <asm/global_data.h>
14#include <linux/compiler.h>
15#include <asm/mmu.h>
16#include <asm/processor.h>
17#include <asm/cache.h>
18#include <asm/immap_85xx.h>
19#include <asm/fsl_law.h>
20#include <asm/fsl_serdes.h>
21#include <asm/fsl_liodn.h>
22#include <fm_eth.h>
23
24#include "../common/ngpixis.h"
25#include "corenet_ds.h"
26
27DECLARE_GLOBAL_DATA_PTR;
28
29int checkboard (void)
30{
31 u8 sw;
32 struct cpu_type *cpu = gd->arch.cpu;
33#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
34 defined(CONFIG_TARGET_P5040DS)
35 unsigned int i;
36#endif
37 static const char * const freq[] = {"100", "125", "156.25", "212.5" };
38
39 printf("Board: %sDS, ", cpu->name);
40 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
41 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
42
43 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
44 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
45
46 if (sw < 0x8)
47 printf("vBank: %d\n", sw);
48 else if (sw == 0x8)
49 puts("Promjet\n");
50 else if (sw == 0x9)
51 puts("NAND\n");
52 else
53 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
54
55
56
57
58
59
60
61
62 puts("SERDES Reference Clocks: ");
63#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
64 defined(CONFIG_TARGET_P5040DS)
65 sw = in_8(&PIXIS_SW(5));
66 for (i = 0; i < 3; i++) {
67 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
68
69 printf("Bank%u=%sMhz ", i+1, freq[clock]);
70 }
71#ifdef CONFIG_TARGET_P5040DS
72
73 sw = in_8(&PIXIS_SW(9));
74 printf("Bank4=%sMhz ", freq[sw & 3]);
75#endif
76 puts("\n");
77#else
78 sw = in_8(&PIXIS_SW(3));
79
80
81
82 printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
83 printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
84 printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
85#endif
86
87 return 0;
88}
89
90int board_early_init_f(void)
91{
92 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
93
94
95
96
97
98
99 setbits_be32(&gur->ddrclkdr, 0x001B001B);
100
101 return 0;
102}
103
104int board_early_init_r(void)
105{
106 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
107 int flash_esel = find_tlb_idx((void *)flashbase, 1);
108
109
110
111
112
113
114
115 flush_dcache();
116 invalidate_icache();
117
118 if (flash_esel == -1) {
119
120 puts("Error: Could not find TLB for FLASH BASE\n");
121 flash_esel = 2;
122 } else {
123
124 disable_tlb(flash_esel);
125 }
126
127 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
128 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
129 0, flash_esel, BOOKE_PAGESZ_256M, 1);
130
131 return 0;
132}
133
134#define NUM_SRDS_BANKS 3
135
136int misc_init_r(void)
137{
138 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
139 u32 actual[NUM_SRDS_BANKS];
140 unsigned int i;
141 u8 sw;
142
143#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
144 defined(CONFIG_TARGET_P5040DS)
145 sw = in_8(&PIXIS_SW(5));
146 for (i = 0; i < 3; i++) {
147 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
148 switch (clock) {
149 case 0:
150 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
151 break;
152 case 1:
153 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
154 break;
155 case 2:
156 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
157 break;
158 default:
159 printf("Warning: SDREFCLK%u switch setting of '11' is "
160 "unsupported\n", i + 1);
161 break;
162 }
163 }
164#else
165
166
167
168
169 sw = in_8(&PIXIS_SW(3));
170 actual[0] = (sw & 0x40) ?
171 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
172 actual[1] = (sw & 0x20) ?
173 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
174 actual[2] = (sw & 0x10) ?
175 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
176#endif
177
178 for (i = 0; i < NUM_SRDS_BANKS; i++) {
179 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
180 if (expected != actual[i]) {
181 printf("Warning: SERDES bank %u expects reference clock"
182 " %sMHz, but actual is %sMHz\n", i + 1,
183 serdes_clock_to_string(expected),
184 serdes_clock_to_string(actual[i]));
185 }
186 }
187
188 return 0;
189}
190
191int ft_board_setup(void *blob, struct bd_info *bd)
192{
193 phys_addr_t base;
194 phys_size_t size;
195
196 ft_cpu_setup(blob, bd);
197
198 base = env_get_bootm_low();
199 size = env_get_bootm_size();
200
201 fdt_fixup_memory(blob, (u64)base, (u64)size);
202
203#ifdef CONFIG_PCI
204 pci_of_setup(blob, bd);
205#endif
206
207 fdt_fixup_liodn(blob);
208 fsl_fdt_fixup_dr_usb(blob, bd);
209
210#ifdef CONFIG_SYS_DPAA_FMAN
211#ifndef CONFIG_DM_ETH
212 fdt_fixup_fman_ethernet(blob);
213#endif
214 fdt_fixup_board_enet(blob);
215#endif
216
217 return 0;
218}
219