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7#include <common.h>
8#include <dm.h>
9#include <net.h>
10#include <asm/io.h>
11#include <netdev.h>
12#include <fm_eth.h>
13#include <fsl_mdio.h>
14#include <malloc.h>
15#include <asm/types.h>
16#include <fsl_dtsec.h>
17#include <asm/arch/soc.h>
18#include <asm/arch-fsl-layerscape/config.h>
19#include <asm/arch-fsl-layerscape/immap_lsch2.h>
20#include <asm/arch/fsl_serdes.h>
21#include <linux/delay.h>
22#include <net/pfe_eth/pfe_eth.h>
23#include <dm/platform_data/pfe_dm_eth.h>
24
25#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
26#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
27
28#define MASK_ETH_PHY_RST 0x00000100
29
30static inline void ls1012afrdm_reset_phy(void)
31{
32 unsigned int val;
33 struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
34
35 setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
36
37 val = in_be32(&pgpio->gpdat);
38 setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
39 mdelay(10);
40
41 val = in_be32(&pgpio->gpdat);
42 setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
43 mdelay(50);
44}
45
46int pfe_eth_board_init(struct udevice *dev)
47{
48 static int init_done;
49 struct mii_dev *bus;
50 struct pfe_mdio_info mac_mdio_info;
51 struct pfe_eth_dev *priv = dev_get_priv(dev);
52
53 if (!init_done) {
54 ls1012afrdm_reset_phy();
55
56 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
57 mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
58
59 bus = pfe_mdio_init(&mac_mdio_info);
60 if (!bus) {
61 printf("Failed to register mdio\n");
62 return -1;
63 }
64
65 init_done = 1;
66 }
67
68 if (priv->gemac_port) {
69 mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
70 mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
71 bus = pfe_mdio_init(&mac_mdio_info);
72 if (!bus) {
73 printf("Failed to register mdio\n");
74 return -1;
75 }
76 }
77
78 pfe_set_mdio(priv->gemac_port,
79 miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
80 if (!priv->gemac_port)
81
82 pfe_set_phy_address_mode(priv->gemac_port,
83 CONFIG_PFE_EMAC1_PHY_ADDR,
84 PHY_INTERFACE_MODE_SGMII);
85 else
86
87 pfe_set_phy_address_mode(priv->gemac_port,
88 CONFIG_PFE_EMAC2_PHY_ADDR,
89 PHY_INTERFACE_MODE_SGMII);
90 return 0;
91}
92
93static struct pfe_eth_pdata pfe_pdata0 = {
94 .pfe_eth_pdata_mac = {
95 .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
96 .phy_interface = 0,
97 },
98
99 .pfe_ddr_addr = {
100 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
101 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
102 },
103};
104
105static struct pfe_eth_pdata pfe_pdata1 = {
106 .pfe_eth_pdata_mac = {
107 .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
108 .phy_interface = 1,
109 },
110
111 .pfe_ddr_addr = {
112 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
113 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
114 },
115};
116
117U_BOOT_DRVINFO(ls1012a_pfe0) = {
118 .name = "pfe_eth",
119 .plat = &pfe_pdata0,
120};
121
122U_BOOT_DRVINFO(ls1012a_pfe1) = {
123 .name = "pfe_eth",
124 .plat = &pfe_pdata1,
125};
126
