LXR uboot/board/freescale/ls1012afrdm/ls1012afrdm.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2017-2018 NXP
   4 */
   5
   6#include <common.h>
   7#include <fdt_support.h>
   8#include <i2c.h>
   9#include <asm/cache.h>
  10#include <init.h>
  11#include <asm/global_data.h>
  12#include <asm/io.h>
  13#include <asm/arch/clock.h>
  14#include <asm/arch/fsl_serdes.h>
  15#ifdef CONFIG_FSL_LS_PPA
  16#include <asm/arch/ppa.h>
  17#endif
  18#include <asm/arch/mmu.h>
  19#include <asm/arch/soc.h>
  20#include <fsl_esdhc.h>
  21#include <hwconfig.h>
  22#include <env_internal.h>
  23#include <fsl_mmdc.h>
  24#include <netdev.h>
  25#include <fsl_sec.h>
  26#include <net/pfe_eth/pfe/pfe_hw.h>
  27
  28DECLARE_GLOBAL_DATA_PTR;
  29
  30static inline int get_board_version(void)
  31{
  32        uint32_t val;
  33#ifdef CONFIG_TARGET_LS1012AFRDM
  34        val = 0;
  35#else
  36        struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
  37
  38        val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
  39
  40#endif
  41        return val;
  42}
  43
  44int checkboard(void)
  45{
  46#ifdef CONFIG_TARGET_LS1012AFRDM
  47        puts("Board: LS1012AFRDM ");
  48#else
  49        int rev;
  50
  51        rev = get_board_version();
  52
  53        puts("Board: FRWY-LS1012A ");
  54
  55        puts("Version");
  56
  57        switch (rev) {
  58        case BOARD_REV_A_B:
  59                puts(": RevA/B ");
  60                break;
  61        case BOARD_REV_C:
  62                puts(": RevC ");
  63                break;
  64        default:
  65                puts(": unknown");
  66                break;
  67        }
  68#endif
  69
  70        return 0;
  71}
  72
  73#ifdef CONFIG_TARGET_LS1012AFRWY
  74int esdhc_status_fixup(void *blob, const char *compat)
  75{
  76        char esdhc0_path[] = "/soc/esdhc@1560000";
  77        char esdhc1_path[] = "/soc/esdhc@1580000";
  78
  79        do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  80                         sizeof("okay"), 1);
  81
  82        do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  83                         sizeof("disabled"), 1);
  84        return 0;
  85}
  86#endif
  87
  88#ifdef CONFIG_TFABOOT
  89int dram_init(void)
  90{
  91#ifdef CONFIG_TARGET_LS1012AFRWY
  92        int board_rev;
  93#endif
  94
  95        gd->ram_size = tfa_get_dram_size();
  96
  97        if (!gd->ram_size) {
  98#ifdef CONFIG_TARGET_LS1012AFRWY
  99                board_rev = get_board_version();
 100
 101                if (board_rev & BOARD_REV_C)
 102                        gd->ram_size = SYS_SDRAM_SIZE_1024;
 103                else
 104                        gd->ram_size = SYS_SDRAM_SIZE_512;
 105#else
 106                gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 107#endif
 108        }
 109        return 0;
 110}
 111#else
 112int dram_init(void)
 113{
 114#ifdef CONFIG_TARGET_LS1012AFRWY
 115        int board_rev;
 116#endif
 117        struct fsl_mmdc_info mparam = {
 118                0x04180000,     /* mdctl */
 119                0x00030035,     /* mdpdc */
 120                0x12554000,     /* mdotc */
 121                0xbabf7954,     /* mdcfg0 */
 122                0xdb328f64,     /* mdcfg1 */
 123                0x01ff00db,     /* mdcfg2 */
 124                0x00001680,     /* mdmisc */
 125                0x0f3c8000,     /* mdref */
 126                0x00002000,     /* mdrwd */
 127                0x00bf1023,     /* mdor */
 128                0x0000003f,     /* mdasp */
 129                0x0000022a,     /* mpodtctrl */
 130                0xa1390003,     /* mpzqhwctrl */
 131        };
 132
 133#ifdef CONFIG_TARGET_LS1012AFRWY
 134        board_rev = get_board_version();
 135
 136        if (board_rev == BOARD_REV_C) {
 137                mparam.mdctl = 0x05180000;
 138                gd->ram_size = SYS_SDRAM_SIZE_1024;
 139        } else {
 140                gd->ram_size = SYS_SDRAM_SIZE_512;
 141        }
 142#else
 143        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 144#endif
 145        mmdc_init(&mparam);
 146
 147#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 148        /* This will break-before-make MMU for DDR */
 149        update_early_mmu_table();
 150#endif
 151
 152        return 0;
 153}
 154#endif
 155
 156int board_early_init_f(void)
 157{
 158        fsl_lsch2_early_init_f();
 159
 160        return 0;
 161}
 162
 163int board_init(void)
 164{
 165        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 166                                        CONFIG_SYS_CCI400_OFFSET);
 167
 168        /*
 169         * Set CCI-400 control override register to enable barrier
 170         * transaction
 171         */
 172        if (current_el() == 3)
 173                out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 174
 175#ifdef CONFIG_FSL_CAAM
 176        sec_init();
 177#endif
 178
 179#ifdef CONFIG_FSL_LS_PPA
 180        ppa_init();
 181#endif
 182        return 0;
 183}
 184
 185#ifdef CONFIG_FSL_PFE
 186void board_quiesce_devices(void)
 187{
 188        pfe_command_stop(0, NULL);
 189}
 190#endif
 191
 192int ft_board_setup(void *blob, struct bd_info *bd)
 193{
 194        arch_fixup_fdt(blob);
 195
 196        ft_cpu_setup(blob, bd);
 197
 198        return 0;
 199}
 200