1
2
3
4
5
6#include <common.h>
7#include <i2c.h>
8#include <fdt_support.h>
9#include <asm/cache.h>
10#include <init.h>
11#include <asm/global_data.h>
12#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/fsl_serdes.h>
15#ifdef CONFIG_FSL_LS_PPA
16#include <asm/arch/ppa.h>
17#endif
18#include <asm/arch/fdt.h>
19#include <asm/arch/mmu.h>
20#include <asm/arch/soc.h>
21#include <ahci.h>
22#include <hwconfig.h>
23#include <mmc.h>
24#include <env_internal.h>
25#include <scsi.h>
26#include <fm_eth.h>
27#include <fsl_esdhc.h>
28#include <fsl_mmdc.h>
29#include <spl.h>
30#include <netdev.h>
31#include <fsl_sec.h>
32#include "../common/qixis.h"
33#include "ls1012aqds_qixis.h"
34#include "ls1012aqds_pfe.h"
35#include <net/pfe_eth/pfe/pfe_hw.h>
36
37DECLARE_GLOBAL_DATA_PTR;
38
39int checkboard(void)
40{
41 char buf[64];
42 u8 sw;
43
44 sw = QIXIS_READ(arch);
45 printf("Board Arch: V%d, ", sw >> 4);
46 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
47
48 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
49
50 if (sw & QIXIS_LBMAP_ALTBANK)
51 printf("flash: 2\n");
52 else
53 printf("flash: 1\n");
54
55 printf("FPGA: v%d (%s), build %d",
56 (int)QIXIS_READ(scver), qixis_read_tag(buf),
57 (int)qixis_read_minor());
58
59
60 printf(" on %s", qixis_read_time(buf));
61 return 0;
62}
63
64#ifdef CONFIG_TFABOOT
65int dram_init(void)
66{
67 gd->ram_size = tfa_get_dram_size();
68 if (!gd->ram_size)
69 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
70
71 return 0;
72}
73#else
74int dram_init(void)
75{
76 static const struct fsl_mmdc_info mparam = {
77 0x05180000,
78 0x00030035,
79 0x12554000,
80 0xbabf7954,
81 0xdb328f64,
82 0x01ff00db,
83 0x00001680,
84 0x0f3c8000,
85 0x00002000,
86 0x00bf1023,
87 0x0000003f,
88 0x0000022a,
89 0xa1390003,
90 };
91
92 mmdc_init(&mparam);
93 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
94#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
95
96 update_early_mmu_table();
97#endif
98
99 return 0;
100}
101#endif
102
103int board_early_init_f(void)
104{
105 fsl_lsch2_early_init_f();
106
107 return 0;
108}
109
110#ifdef CONFIG_MISC_INIT_R
111int misc_init_r(void)
112{
113 u8 mux_sdhc_cd = 0x80;
114 int bus_num = 0;
115
116#if CONFIG_IS_ENABLED(DM_I2C)
117 struct udevice *dev;
118 int ret;
119
120 ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
121 1, &dev);
122 if (ret) {
123 printf("%s: Cannot find udev for a bus %d\n", __func__,
124 bus_num);
125 return ret;
126 }
127 dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
128#else
129 i2c_set_bus_num(bus_num);
130
131 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
132#endif
133
134 return 0;
135}
136#endif
137
138int board_init(void)
139{
140 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
141 CONFIG_SYS_CCI400_OFFSET);
142
143
144
145 if (current_el() == 3)
146 out_le32(&cci->ctrl_ord,
147 CCI400_CTRLORD_EN_BARRIER);
148
149#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
150 erratum_a010315();
151#endif
152
153#ifdef CONFIG_FSL_CAAM
154 sec_init();
155#endif
156
157#ifdef CONFIG_FSL_LS_PPA
158 ppa_init();
159#endif
160 return 0;
161}
162
163#ifdef CONFIG_FSL_PFE
164void board_quiesce_devices(void)
165{
166 pfe_command_stop(0, NULL);
167}
168#endif
169
170int esdhc_status_fixup(void *blob, const char *compat)
171{
172 char esdhc0_path[] = "/soc/esdhc@1560000";
173 char esdhc1_path[] = "/soc/esdhc@1580000";
174 u8 card_id;
175
176 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
177 sizeof("okay"), 1);
178
179
180
181
182
183
184
185
186 card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
187
188
189 if (card_id == 0x7)
190 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
191 sizeof("disabled"), 1);
192 else
193 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
194 sizeof("okay"), 1);
195 return 0;
196}
197
198static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
199 char *enet_path, char *mdio_path)
200{
201 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
202 &prop_val.busid, PFE_PROP_LEN, 1);
203 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
204 &prop_val.phyid, PFE_PROP_LEN, 1);
205 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
206 &prop_val.mux_val, PFE_PROP_LEN, 1);
207 do_fixup_by_path(set_blob, enet_path, "phy-mode",
208 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
209 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
210 &prop_val.phy_mask, PFE_PROP_LEN, 1);
211 return 0;
212}
213
214static void fdt_fsl_fixup_of_pfe(void *blob)
215{
216 int i = 0;
217 struct pfe_prop_val prop_val;
218 void *l_blob = blob;
219
220 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
221 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
222 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
223 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
224
225 for (i = 0; i < NUM_ETH_NODE; i++) {
226 switch (srds_s1) {
227 case SERDES_1_G_PROTOCOL:
228 if (i == 0) {
229 prop_val.busid = cpu_to_fdt32(
230 ETH_1_1G_BUS_ID);
231 prop_val.phyid = cpu_to_fdt32(
232 ETH_1_1G_PHY_ID);
233 prop_val.mux_val = cpu_to_fdt32(
234 ETH_1_1G_MDIO_MUX);
235 prop_val.phy_mask = cpu_to_fdt32(
236 ETH_1G_MDIO_PHY_MASK);
237 prop_val.phy_mode = "sgmii";
238 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
239 ETH_1_MDIO);
240 } else {
241 prop_val.busid = cpu_to_fdt32(
242 ETH_2_1G_BUS_ID);
243 prop_val.phyid = cpu_to_fdt32(
244 ETH_2_1G_PHY_ID);
245 prop_val.mux_val = cpu_to_fdt32(
246 ETH_2_1G_MDIO_MUX);
247 prop_val.phy_mask = cpu_to_fdt32(
248 ETH_1G_MDIO_PHY_MASK);
249 prop_val.phy_mode = "rgmii";
250 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
251 ETH_2_MDIO);
252 }
253 break;
254 case SERDES_2_5_G_PROTOCOL:
255 if (i == 0) {
256 prop_val.busid = cpu_to_fdt32(
257 ETH_1_2_5G_BUS_ID);
258 prop_val.phyid = cpu_to_fdt32(
259 ETH_1_2_5G_PHY_ID);
260 prop_val.mux_val = cpu_to_fdt32(
261 ETH_1_2_5G_MDIO_MUX);
262 prop_val.phy_mask = cpu_to_fdt32(
263 ETH_2_5G_MDIO_PHY_MASK);
264 prop_val.phy_mode = "2500base-x";
265 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
266 ETH_1_MDIO);
267 } else {
268 prop_val.busid = cpu_to_fdt32(
269 ETH_2_2_5G_BUS_ID);
270 prop_val.phyid = cpu_to_fdt32(
271 ETH_2_2_5G_PHY_ID);
272 prop_val.mux_val = cpu_to_fdt32(
273 ETH_2_2_5G_MDIO_MUX);
274 prop_val.phy_mask = cpu_to_fdt32(
275 ETH_2_5G_MDIO_PHY_MASK);
276 prop_val.phy_mode = "2500base-x";
277 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
278 ETH_2_MDIO);
279 }
280 break;
281 default:
282 printf("serdes:[%d]\n", srds_s1);
283 }
284 }
285}
286
287#ifdef CONFIG_OF_BOARD_SETUP
288int ft_board_setup(void *blob, struct bd_info *bd)
289{
290 arch_fixup_fdt(blob);
291
292 ft_cpu_setup(blob, bd);
293 fdt_fsl_fixup_of_pfe(blob);
294
295 return 0;
296}
297#endif
298
