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7#include <common.h>
8#include <clock_legacy.h>
9#include <fdt_support.h>
10#include <i2c.h>
11#include <init.h>
12#include <log.h>
13#include <asm/io.h>
14#include <asm/arch/immap_ls102xa.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/fsl_serdes.h>
17#include <asm/arch/ls102xa_soc.h>
18#include <asm/arch/ls102xa_devdis.h>
19#include <hwconfig.h>
20#include <mmc.h>
21#include <fsl_csu.h>
22#include <fsl_ifc.h>
23#include <fsl_sec.h>
24#include <spl.h>
25#include <fsl_devdis.h>
26#include <fsl_validate.h>
27#include <fsl_ddr.h>
28#include "../common/i2c_mux.h"
29#include "../common/sleep.h"
30#include "../common/qixis.h"
31#include "ls1021aqds_qixis.h"
32#ifdef CONFIG_U_QE
33#include <fsl_qe.h>
34#endif
35
36#define PIN_MUX_SEL_CAN 0x03
37#define PIN_MUX_SEL_IIC2 0xa0
38#define PIN_MUX_SEL_RGMII 0x00
39#define PIN_MUX_SEL_SAI 0x0c
40#define PIN_MUX_SEL_SDHC 0x00
41
42#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
43#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
44enum {
45 MUX_TYPE_CAN,
46 MUX_TYPE_IIC2,
47 MUX_TYPE_RGMII,
48 MUX_TYPE_SAI,
49 MUX_TYPE_SDHC,
50 MUX_TYPE_SD_PCI4,
51 MUX_TYPE_SD_PC_SA_SG_SG,
52 MUX_TYPE_SD_PC_SA_PC_SG,
53 MUX_TYPE_SD_PC_SG_SG,
54};
55
56enum {
57 GE0_CLK125,
58 GE2_CLK125,
59 GE1_CLK125,
60};
61
62int checkboard(void)
63{
64#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
65 char buf[64];
66#endif
67#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
68 u8 sw;
69#endif
70
71 puts("Board: LS1021AQDS\n");
72
73#ifdef CONFIG_SD_BOOT
74 puts("SD\n");
75#elif CONFIG_QSPI_BOOT
76 puts("QSPI\n");
77#else
78 sw = QIXIS_READ(brdcfg[0]);
79 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
80
81 if (sw < 0x8)
82 printf("vBank: %d\n", sw);
83 else if (sw == 0x8)
84 puts("PromJet\n");
85 else if (sw == 0x9)
86 puts("NAND\n");
87 else if (sw == 0x15)
88 printf("IFCCard\n");
89 else
90 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
91#endif
92
93#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
94 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
95 QIXIS_READ(id), QIXIS_READ(arch));
96
97 printf("FPGA: v%d (%s), build %d\n",
98 (int)QIXIS_READ(scver), qixis_read_tag(buf),
99 (int)qixis_read_minor());
100#endif
101
102 return 0;
103}
104
105unsigned long get_board_sys_clk(void)
106{
107 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
108
109 switch (sysclk_conf & 0x0f) {
110 case QIXIS_SYSCLK_64:
111 return 64000000;
112 case QIXIS_SYSCLK_83:
113 return 83333333;
114 case QIXIS_SYSCLK_100:
115 return 100000000;
116 case QIXIS_SYSCLK_125:
117 return 125000000;
118 case QIXIS_SYSCLK_133:
119 return 133333333;
120 case QIXIS_SYSCLK_150:
121 return 150000000;
122 case QIXIS_SYSCLK_160:
123 return 160000000;
124 case QIXIS_SYSCLK_166:
125 return 166666666;
126 }
127 return 66666666;
128}
129
130#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
131unsigned long get_board_ddr_clk(void)
132{
133 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
134
135 switch ((ddrclk_conf & 0x30) >> 4) {
136 case QIXIS_DDRCLK_100:
137 return 100000000;
138 case QIXIS_DDRCLK_125:
139 return 125000000;
140 case QIXIS_DDRCLK_133:
141 return 133333333;
142 }
143 return 66666666;
144}
145#endif
146
147int dram_init(void)
148{
149
150
151
152
153
154
155
156 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
157 return fsl_initdram();
158}
159
160int board_early_init_f(void)
161{
162 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
163
164#ifdef CONFIG_TSEC_ENET
165
166 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
167#endif
168
169#ifdef CONFIG_FSL_IFC
170 init_early_memctl_regs();
171#endif
172
173 arch_soc_init();
174
175#if defined(CONFIG_DEEP_SLEEP)
176 if (is_warm_boot())
177 fsl_dp_disable_console();
178#endif
179
180 return 0;
181}
182
183#ifdef CONFIG_SPL_BUILD
184void board_init_f(ulong dummy)
185{
186#ifdef CONFIG_NAND_BOOT
187 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
188 u32 porsr1, pinctl;
189
190
191
192
193
194
195 porsr1 = in_be32(&gur->porsr1);
196 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
197 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
198 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
199 pinctl);
200#endif
201
202
203 memset(__bss_start, 0, __bss_end - __bss_start);
204
205#ifdef CONFIG_FSL_IFC
206 init_early_memctl_regs();
207#endif
208
209 get_clocks();
210
211#if defined(CONFIG_DEEP_SLEEP)
212 if (is_warm_boot())
213 fsl_dp_disable_console();
214#endif
215
216 preloader_console_init();
217
218#ifdef CONFIG_SPL_I2C
219 i2c_init_all();
220#endif
221
222 timer_init();
223 dram_init();
224
225
226#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
227 enable_layerscape_ns_access();
228#endif
229
230 board_init_r(NULL, 0);
231}
232#endif
233
234void config_etseccm_source(int etsec_gtx_125_mux)
235{
236 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
237
238 switch (etsec_gtx_125_mux) {
239 case GE0_CLK125:
240 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
241 debug("etseccm set to GE0_CLK125\n");
242 break;
243
244 case GE2_CLK125:
245 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
246 debug("etseccm set to GE2_CLK125\n");
247 break;
248
249 case GE1_CLK125:
250 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
251 debug("etseccm set to GE1_CLK125\n");
252 break;
253
254 default:
255 printf("Error! trying to set etseccm to invalid value\n");
256 break;
257 }
258}
259
260int config_board_mux(int ctrl_type)
261{
262 u8 reg12, reg14;
263
264 reg12 = QIXIS_READ(brdcfg[12]);
265 reg14 = QIXIS_READ(brdcfg[14]);
266
267 switch (ctrl_type) {
268 case MUX_TYPE_CAN:
269 config_etseccm_source(GE2_CLK125);
270 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
271 break;
272 case MUX_TYPE_IIC2:
273 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
274 break;
275 case MUX_TYPE_RGMII:
276 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
277 break;
278 case MUX_TYPE_SAI:
279 config_etseccm_source(GE2_CLK125);
280 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
281 break;
282 case MUX_TYPE_SDHC:
283 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
284 break;
285 case MUX_TYPE_SD_PCI4:
286 reg12 = 0x38;
287 break;
288 case MUX_TYPE_SD_PC_SA_SG_SG:
289 reg12 = 0x01;
290 break;
291 case MUX_TYPE_SD_PC_SA_PC_SG:
292 reg12 = 0x01;
293 break;
294 case MUX_TYPE_SD_PC_SG_SG:
295 reg12 = 0x21;
296 break;
297 default:
298 printf("Wrong mux interface type\n");
299 return -1;
300 }
301
302 QIXIS_WRITE(brdcfg[12], reg12);
303 QIXIS_WRITE(brdcfg[14], reg14);
304
305 return 0;
306}
307
308int config_serdes_mux(void)
309{
310 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
311 u32 cfg;
312
313 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
314 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
315
316 switch (cfg) {
317 case 0x0:
318 config_board_mux(MUX_TYPE_SD_PCI4);
319 break;
320 case 0x30:
321 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
322 break;
323 case 0x60:
324 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
325 break;
326 case 0x70:
327 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
328 break;
329 default:
330 printf("SRDS1 prtcl:0x%x\n", cfg);
331 break;
332 }
333
334 return 0;
335}
336
337#ifdef CONFIG_BOARD_LATE_INIT
338int board_late_init(void)
339{
340#ifdef CONFIG_CHAIN_OF_TRUST
341 fsl_setenv_chain_of_trust();
342#endif
343
344 return 0;
345}
346#endif
347
348int misc_init_r(void)
349{
350 int conflict_flag;
351
352
353 conflict_flag = 0;
354 if (hwconfig("sdhc"))
355 conflict_flag++;
356 if (hwconfig("iic2"))
357 conflict_flag++;
358 if (conflict_flag > 1) {
359 printf("WARNING: pin conflict !\n");
360 return 0;
361 }
362
363 conflict_flag = 0;
364 if (hwconfig("rgmii"))
365 conflict_flag++;
366 if (hwconfig("can"))
367 conflict_flag++;
368 if (hwconfig("sai"))
369 conflict_flag++;
370 if (conflict_flag > 1) {
371 printf("WARNING: pin conflict !\n");
372 return 0;
373 }
374
375 if (hwconfig("can"))
376 config_board_mux(MUX_TYPE_CAN);
377 else if (hwconfig("rgmii"))
378 config_board_mux(MUX_TYPE_RGMII);
379 else if (hwconfig("sai"))
380 config_board_mux(MUX_TYPE_SAI);
381
382 if (hwconfig("iic2"))
383 config_board_mux(MUX_TYPE_IIC2);
384 else if (hwconfig("sdhc"))
385 config_board_mux(MUX_TYPE_SDHC);
386
387#ifdef CONFIG_FSL_DEVICE_DISABLE
388 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
389#endif
390#ifdef CONFIG_FSL_CAAM
391 return sec_init();
392#endif
393 return 0;
394}
395
396int board_init(void)
397{
398#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
399 erratum_a010315();
400#endif
401#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
402 erratum_a009942_check_cpo();
403#endif
404
405 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
406
407#ifndef CONFIG_SYS_FSL_NO_SERDES
408 fsl_serdes_init();
409 config_serdes_mux();
410#endif
411
412 ls102xa_smmu_stream_id_init();
413
414#ifdef CONFIG_U_QE
415 u_qe_init();
416#endif
417
418 return 0;
419}
420
421#if defined(CONFIG_DEEP_SLEEP)
422void board_sleep_prepare(void)
423{
424#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
425 enable_layerscape_ns_access();
426#endif
427}
428#endif
429
430int ft_board_setup(void *blob, struct bd_info *bd)
431{
432 ft_cpu_setup(blob, bd);
433
434#ifdef CONFIG_PCI
435 ft_pci_setup(blob, bd);
436#endif
437
438 return 0;
439}
440
441u8 flash_read8(void *addr)
442{
443 return __raw_readb(addr + 1);
444}
445
446void flash_write16(u16 val, void *addr)
447{
448 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
449
450 __raw_writew(shftval, addr);
451}
452
453u16 flash_read16(void *addr)
454{
455 u16 val = __raw_readw(addr);
456
457 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
458}
459
