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7#include <common.h>
8#include <clock_legacy.h>
9#include <command.h>
10#include <fdt_support.h>
11#include <i2c.h>
12#include <init.h>
13#include <net.h>
14#include <asm/global_data.h>
15#include <asm/io.h>
16#include <asm/arch/immap_ls102xa.h>
17#include <asm/arch/clock.h>
18#include <asm/arch/fsl_serdes.h>
19#include <asm/arch/ls102xa_devdis.h>
20#include <asm/arch/ls102xa_soc.h>
21#include <hwconfig.h>
22#include <mmc.h>
23#include <fsl_csu.h>
24#include <fsl_ifc.h>
25#include <fsl_immap.h>
26#include <netdev.h>
27#include <fsl_mdio.h>
28#include <tsec.h>
29#include <fsl_sec.h>
30#include <fsl_devdis.h>
31#include <spl.h>
32#include <linux/delay.h>
33#include "../common/sleep.h"
34#ifdef CONFIG_U_QE
35#include <fsl_qe.h>
36#endif
37#include <fsl_validate.h>
38
39
40DECLARE_GLOBAL_DATA_PTR;
41
42#define VERSION_MASK 0x00FF
43#define BANK_MASK 0x0001
44#define CFG_RESET 0x1
45#define INIT_RESET 0x1
46
47#define CPLD_SET_MUX_SERDES 0x20
48#define CPLD_SET_BOOT_BANK 0x40
49
50#define BOOT_FROM_UPPER_BANK 0x0
51#define BOOT_FROM_LOWER_BANK 0x1
52
53#define LANEB_SATA (0x01)
54#define LANEB_SGMII1 (0x02)
55#define LANEC_SGMII1 (0x04)
56#define LANEC_PCIEX1 (0x08)
57#define LANED_PCIEX2 (0x10)
58#define LANED_SGMII2 (0x20)
59
60#define MASK_LANE_B 0x1
61#define MASK_LANE_C 0x2
62#define MASK_LANE_D 0x4
63#define MASK_SGMII 0x8
64
65#define KEEP_STATUS 0x0
66#define NEED_RESET 0x1
67
68#define SOFT_MUX_ON_I2C3_IFC 0x2
69#define SOFT_MUX_ON_CAN3_USB2 0x8
70#define SOFT_MUX_ON_QE_LCD 0x10
71
72#define PIN_I2C3_IFC_MUX_I2C3 0x0
73#define PIN_I2C3_IFC_MUX_IFC 0x1
74#define PIN_CAN3_USB2_MUX_USB2 0x0
75#define PIN_CAN3_USB2_MUX_CAN3 0x1
76#define PIN_QE_LCD_MUX_LCD 0x0
77#define PIN_QE_LCD_MUX_QE 0x1
78
79struct cpld_data {
80 u8 cpld_ver;
81 u8 cpld_ver_sub;
82 u8 pcba_ver;
83 u8 system_rst;
84 u8 soft_mux_on;
85 u8 cfg_rcw_src1;
86 u8 cfg_rcw_src2;
87 u8 vbank;
88 u8 gpio;
89 u8 i2c3_ifc_mux;
90 u8 mux_spi2;
91 u8 can3_usb2_mux;
92 u8 qe_lcd_mux;
93 u8 serdes_mux;
94 u8 global_rst;
95 u8 rev1;
96 u8 rev2;
97};
98
99#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
100static void cpld_show(void)
101{
102 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
103
104 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
105 in_8(&cpld_data->cpld_ver) & VERSION_MASK,
106 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
107 in_8(&cpld_data->pcba_ver) & VERSION_MASK,
108 in_8(&cpld_data->vbank) & BANK_MASK);
109
110#ifdef CONFIG_DEBUG
111 printf("soft_mux_on =%x\n",
112 in_8(&cpld_data->soft_mux_on));
113 printf("cfg_rcw_src1 =%x\n",
114 in_8(&cpld_data->cfg_rcw_src1));
115 printf("cfg_rcw_src2 =%x\n",
116 in_8(&cpld_data->cfg_rcw_src2));
117 printf("vbank =%x\n",
118 in_8(&cpld_data->vbank));
119 printf("gpio =%x\n",
120 in_8(&cpld_data->gpio));
121 printf("i2c3_ifc_mux =%x\n",
122 in_8(&cpld_data->i2c3_ifc_mux));
123 printf("mux_spi2 =%x\n",
124 in_8(&cpld_data->mux_spi2));
125 printf("can3_usb2_mux =%x\n",
126 in_8(&cpld_data->can3_usb2_mux));
127 printf("qe_lcd_mux =%x\n",
128 in_8(&cpld_data->qe_lcd_mux));
129 printf("serdes_mux =%x\n",
130 in_8(&cpld_data->serdes_mux));
131#endif
132}
133#endif
134
135int checkboard(void)
136{
137 puts("Board: LS1021ATWR\n");
138#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
139 cpld_show();
140#endif
141
142 return 0;
143}
144
145void ddrmc_init(void)
146{
147 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
148 u32 temp_sdram_cfg, tmp;
149
150 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
151
152 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
153 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
154
155 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
156 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
157 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
158 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
159 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
160 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
161
162#ifdef CONFIG_DEEP_SLEEP
163 if (is_warm_boot()) {
164 out_be32(&ddr->sdram_cfg_2,
165 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
166 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
167 out_be32(&ddr->init_ext_addr, (1 << 31));
168
169
170 out_be32(&ddr->ddr_cdr2,
171 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
172 } else
173#endif
174 {
175 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
176 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
177 }
178
179 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
180 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
181
182 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
183
184 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
185
186 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
187 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
188
189 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
190
191 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
192 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
193
194 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
195
196
197 tmp = in_be32(&ddr->debug[28]);
198 out_be32(&ddr->debug[28], tmp | 0x0070006f);
199
200 udelay(1);
201
202#ifdef CONFIG_DEEP_SLEEP
203 if (is_warm_boot()) {
204
205 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
206 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
207 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
208
209 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
210 } else
211#endif
212 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
213
214 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
215
216#ifdef CONFIG_DEEP_SLEEP
217 if (is_warm_boot()) {
218
219 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
220 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
221 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
222 }
223#endif
224}
225
226int dram_init(void)
227{
228#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
229 ddrmc_init();
230#endif
231
232 erratum_a008850_post();
233
234 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
235
236#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
237 fsl_dp_resume();
238#endif
239
240 return 0;
241}
242
243int board_eth_init(struct bd_info *bis)
244{
245 return pci_eth_init(bis);
246}
247
248#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
249static void convert_serdes_mux(int type, int need_reset)
250{
251 char current_serdes;
252 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
253
254 current_serdes = cpld_data->serdes_mux;
255
256 switch (type) {
257 case LANEB_SATA:
258 current_serdes &= ~MASK_LANE_B;
259 break;
260 case LANEB_SGMII1:
261 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
262 break;
263 case LANEC_SGMII1:
264 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
265 break;
266 case LANED_SGMII2:
267 current_serdes |= MASK_LANE_D;
268 break;
269 case LANEC_PCIEX1:
270 current_serdes |= MASK_LANE_C;
271 break;
272 case (LANED_PCIEX2 | LANEC_PCIEX1):
273 current_serdes |= MASK_LANE_C;
274 current_serdes &= ~MASK_LANE_D;
275 break;
276 default:
277 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
278 return;
279 }
280
281 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
282 cpld_data->serdes_mux = current_serdes;
283
284 if (need_reset == 1) {
285 printf("Reset board to enable configuration\n");
286 cpld_data->system_rst = CFG_RESET;
287 }
288}
289
290int config_serdes_mux(void)
291{
292 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
293 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
294
295 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
296 switch (protocol) {
297 case 0x10:
298 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
299 convert_serdes_mux(LANED_PCIEX2 |
300 LANEC_PCIEX1, KEEP_STATUS);
301 break;
302 case 0x20:
303 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
304 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
305 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
306 break;
307 case 0x30:
308 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
309 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
310 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
311 break;
312 case 0x70:
313 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
314 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
315 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
316 break;
317 }
318
319 return 0;
320}
321#endif
322
323#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
324int config_board_mux(void)
325{
326 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
327 int conflict_flag;
328
329 conflict_flag = 0;
330 if (hwconfig("i2c3")) {
331 conflict_flag++;
332 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
333 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
334 }
335
336 if (hwconfig("ifc")) {
337 conflict_flag++;
338
339 if (conflict_flag > 1)
340 goto conflict;
341 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
342 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
343 }
344
345 conflict_flag = 0;
346 if (hwconfig("usb2")) {
347 conflict_flag++;
348 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
349 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
350 }
351
352 if (hwconfig("can3")) {
353 conflict_flag++;
354
355 if (conflict_flag > 1)
356 goto conflict;
357 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
358 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
359 }
360
361 conflict_flag = 0;
362 if (hwconfig("lcd")) {
363 conflict_flag++;
364 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
365 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
366 }
367
368 if (hwconfig("qe")) {
369 conflict_flag++;
370
371 if (conflict_flag > 1)
372 goto conflict;
373 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
374 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
375 }
376
377 return 0;
378
379conflict:
380 printf("WARNING: pin conflict! MUX setting may failed!\n");
381 return 0;
382}
383#endif
384
385int board_early_init_f(void)
386{
387 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
388
389#ifdef CONFIG_TSEC_ENET
390
391 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
392 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
393#endif
394
395#ifdef CONFIG_FSL_IFC
396 init_early_memctl_regs();
397#endif
398
399 arch_soc_init();
400
401#if defined(CONFIG_DEEP_SLEEP)
402 if (is_warm_boot()) {
403 timer_init();
404 dram_init();
405 }
406#endif
407
408 return 0;
409}
410
411#ifdef CONFIG_SPL_BUILD
412void board_init_f(ulong dummy)
413{
414 void (*second_uboot)(void);
415
416
417 memset(__bss_start, 0, __bss_end - __bss_start);
418
419 get_clocks();
420
421#if defined(CONFIG_DEEP_SLEEP)
422 if (is_warm_boot())
423 fsl_dp_disable_console();
424#endif
425
426 preloader_console_init();
427
428 timer_init();
429 dram_init();
430
431
432#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
433 enable_layerscape_ns_access();
434#endif
435
436
437
438
439
440
441
442 if (is_warm_boot()) {
443 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
444 second_uboot();
445 }
446
447 board_init_r(NULL, 0);
448}
449#endif
450
451#ifdef CONFIG_DEEP_SLEEP
452
453void ls1twr_program_regulator(void)
454{
455 u8 i2c_device_id;
456
457#define LS1TWR_I2C_BUS_MC34VR500 1
458#define MC34VR500_ADDR 0x8
459#define MC34VR500_DEVICEID 0x4
460#define MC34VR500_DEVICEID_MASK 0x0f
461#if CONFIG_IS_ENABLED(DM_I2C)
462 struct udevice *dev;
463 int ret;
464
465 ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
466 1, &dev);
467 if (ret) {
468 printf("%s: Cannot find udev for a bus %d\n", __func__,
469 LS1TWR_I2C_BUS_MC34VR500);
470 return;
471 }
472 i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
473 MC34VR500_DEVICEID_MASK;
474 if (i2c_device_id != MC34VR500_DEVICEID) {
475 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
476 return;
477 }
478
479 dm_i2c_reg_write(dev, 0x31, 0x4);
480 dm_i2c_reg_write(dev, 0x4d, 0x4);
481 dm_i2c_reg_write(dev, 0x6d, 0x38);
482 dm_i2c_reg_write(dev, 0x6f, 0x37);
483 dm_i2c_reg_write(dev, 0x71, 0x30);
484#else
485 unsigned int i2c_bus;
486 i2c_bus = i2c_get_bus_num();
487 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
488 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
489 MC34VR500_DEVICEID_MASK;
490 if (i2c_device_id != MC34VR500_DEVICEID) {
491 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
492 return;
493 }
494
495 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
496 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
497 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
498 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
499 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
500
501 i2c_set_bus_num(i2c_bus);
502#endif
503}
504#endif
505
506int board_init(void)
507{
508#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
509 erratum_a010315();
510#endif
511
512#ifndef CONFIG_SYS_FSL_NO_SERDES
513 fsl_serdes_init();
514#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
515 config_serdes_mux();
516#endif
517#endif
518
519 ls102xa_smmu_stream_id_init();
520
521#ifdef CONFIG_U_QE
522 u_qe_init();
523#endif
524
525#ifdef CONFIG_DEEP_SLEEP
526 ls1twr_program_regulator();
527#endif
528 return 0;
529}
530
531#if defined(CONFIG_SPL_BUILD)
532void spl_board_init(void)
533{
534 ls102xa_smmu_stream_id_init();
535}
536#endif
537
538#ifdef CONFIG_BOARD_LATE_INIT
539int board_late_init(void)
540{
541#ifdef CONFIG_CHAIN_OF_TRUST
542 fsl_setenv_chain_of_trust();
543#endif
544
545 return 0;
546}
547#endif
548
549#if defined(CONFIG_MISC_INIT_R)
550int misc_init_r(void)
551{
552#ifdef CONFIG_FSL_DEVICE_DISABLE
553 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
554#endif
555#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
556 config_board_mux();
557#endif
558
559#ifdef CONFIG_FSL_CAAM
560 return sec_init();
561#endif
562}
563#endif
564
565#if defined(CONFIG_DEEP_SLEEP)
566void board_sleep_prepare(void)
567{
568#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
569 enable_layerscape_ns_access();
570#endif
571}
572#endif
573
574int ft_board_setup(void *blob, struct bd_info *bd)
575{
576 ft_cpu_setup(blob, bd);
577
578#ifdef CONFIG_PCI
579 ft_pci_setup(blob, bd);
580#endif
581
582 return 0;
583}
584
585u8 flash_read8(void *addr)
586{
587 return __raw_readb(addr + 1);
588}
589
590void flash_write16(u16 val, void *addr)
591{
592 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
593
594 __raw_writew(shftval, addr);
595}
596
597u16 flash_read16(void *addr)
598{
599 u16 val = __raw_readw(addr);
600
601 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
602}
603
604#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
605 && !defined(CONFIG_SPL_BUILD)
606static void convert_flash_bank(char bank)
607{
608 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
609
610 printf("Now switch to boot from flash bank %d.\n", bank);
611 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
612 cpld_data->vbank = bank;
613
614 printf("Reset board to enable configuration.\n");
615 cpld_data->system_rst = CFG_RESET;
616}
617
618static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
619 char *const argv[])
620{
621 if (argc != 2)
622 return CMD_RET_USAGE;
623 if (strcmp(argv[1], "0") == 0)
624 convert_flash_bank(BOOT_FROM_UPPER_BANK);
625 else if (strcmp(argv[1], "1") == 0)
626 convert_flash_bank(BOOT_FROM_LOWER_BANK);
627 else
628 return CMD_RET_USAGE;
629
630 return 0;
631}
632
633U_BOOT_CMD(
634 boot_bank, 2, 0, flash_bank_cmd,
635 "Flash bank Selection Control",
636 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
637);
638
639static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
640 char *const argv[])
641{
642 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
643
644 if (argc > 2)
645 return CMD_RET_USAGE;
646 if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
647 cpld_data->system_rst = CFG_RESET;
648 else if (strcmp(argv[1], "init") == 0)
649 cpld_data->global_rst = INIT_RESET;
650 else
651 return CMD_RET_USAGE;
652
653 return 0;
654}
655
656U_BOOT_CMD(
657 cpld_reset, 2, 0, cpld_reset_cmd,
658 "Reset via CPLD",
659 "conf\n"
660 " -reset with current CPLD configuration\n"
661 "init\n"
662 " -reset and initial CPLD configuration with default value"
663
664);
665
666static void print_serdes_mux(void)
667{
668 char current_serdes;
669 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
670
671 current_serdes = cpld_data->serdes_mux;
672
673 printf("Serdes Lane B: ");
674 if ((current_serdes & MASK_LANE_B) == 0)
675 printf("SATA,\n");
676 else
677 printf("SGMII 1,\n");
678
679 printf("Serdes Lane C: ");
680 if ((current_serdes & MASK_LANE_C) == 0)
681 printf("SGMII 1,\n");
682 else
683 printf("PCIe,\n");
684
685 printf("Serdes Lane D: ");
686 if ((current_serdes & MASK_LANE_D) == 0)
687 printf("PCIe,\n");
688 else
689 printf("SGMII 2,\n");
690
691 printf("SGMII 1 is on lane ");
692 if ((current_serdes & MASK_SGMII) == 0)
693 printf("C.\n");
694 else
695 printf("B.\n");
696}
697
698static int serdes_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
699 char *const argv[])
700{
701 if (argc != 2)
702 return CMD_RET_USAGE;
703 if (strcmp(argv[1], "sata") == 0) {
704 printf("Set serdes lane B to SATA.\n");
705 convert_serdes_mux(LANEB_SATA, NEED_RESET);
706 } else if (strcmp(argv[1], "sgmii1b") == 0) {
707 printf("Set serdes lane B to SGMII 1.\n");
708 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
709 } else if (strcmp(argv[1], "sgmii1c") == 0) {
710 printf("Set serdes lane C to SGMII 1.\n");
711 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
712 } else if (strcmp(argv[1], "sgmii2") == 0) {
713 printf("Set serdes lane D to SGMII 2.\n");
714 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
715 } else if (strcmp(argv[1], "pciex1") == 0) {
716 printf("Set serdes lane C to PCIe X1.\n");
717 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
718 } else if (strcmp(argv[1], "pciex2") == 0) {
719 printf("Set serdes lane C & lane D to PCIe X2.\n");
720 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
721 } else if (strcmp(argv[1], "show") == 0) {
722 print_serdes_mux();
723 } else {
724 return CMD_RET_USAGE;
725 }
726
727 return 0;
728}
729
730U_BOOT_CMD(
731 lane_bank, 2, 0, serdes_mux_cmd,
732 "Multiplexed function setting for SerDes Lanes",
733 "sata\n"
734 " -change lane B to sata\n"
735 "lane_bank sgmii1b\n"
736 " -change lane B to SGMII1\n"
737 "lane_bank sgmii1c\n"
738 " -change lane C to SGMII1\n"
739 "lane_bank sgmii2\n"
740 " -change lane D to SGMII2\n"
741 "lane_bank pciex1\n"
742 " -change lane C to PCIeX1\n"
743 "lane_bank pciex2\n"
744 " -change lane C & lane D to PCIeX2\n"
745 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
746);
747#endif
748
