LXR uboot/board/freescale/ls1028a/ls1028a.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2019 NXP
   4 */
   5
   6#include <common.h>
   7#include <init.h>
   8#include <malloc.h>
   9#include <errno.h>
  10#include <fsl_ddr.h>
  11#include <net.h>
  12#include <asm/global_data.h>
  13#include <asm/io.h>
  14#include <hwconfig.h>
  15#include <fdt_support.h>
  16#include <linux/libfdt.h>
  17#include <env_internal.h>
  18#include <asm/arch-fsl-layerscape/soc.h>
  19#include <asm/arch-fsl-layerscape/fsl_icid.h>
  20#include <i2c.h>
  21#include <asm/arch/soc.h>
  22#ifdef CONFIG_FSL_LS_PPA
  23#include <asm/arch/ppa.h>
  24#endif
  25#include <fsl_immap.h>
  26#include <netdev.h>
  27
  28#include <fdtdec.h>
  29#include <miiphy.h>
  30#include "../common/qixis.h"
  31#include "../drivers/net/fsl_enetc.h"
  32
  33DECLARE_GLOBAL_DATA_PTR;
  34
  35int config_board_mux(void)
  36{
  37#ifndef CONFIG_LPUART
  38#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  39        u8 reg;
  40
  41        reg = QIXIS_READ(brdcfg[13]);
  42        /* Field| Function
  43         * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  44         * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  45         * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  46         * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  47         */
  48        reg &= ~(0xf0);
  49        reg |= 0xb0;
  50        QIXIS_WRITE(brdcfg[13], reg);
  51
  52        reg = QIXIS_READ(brdcfg[15]);
  53        /* Field| Function
  54         * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  55         * CAN1 | 0= CAN #1 transceiver enabled
  56         * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  57         * CAN2 | 0= CAN #2 transceiver enabled
  58         */
  59        reg &= ~(0xc0);
  60        QIXIS_WRITE(brdcfg[15], reg);
  61#endif
  62#endif
  63
  64        return 0;
  65}
  66
  67#ifdef CONFIG_LPUART
  68u32 get_lpuart_clk(void)
  69{
  70        return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
  71}
  72#endif
  73
  74int board_init(void)
  75{
  76#ifdef CONFIG_FSL_CAAM
  77        sec_init();
  78#endif
  79
  80#ifdef CONFIG_FSL_LS_PPA
  81        ppa_init();
  82#endif
  83
  84#ifndef CONFIG_SYS_EARLY_PCI_INIT
  85        pci_init();
  86#endif
  87
  88#if defined(CONFIG_TARGET_LS1028ARDB)
  89        u8 val = I2C_MUX_CH_DEFAULT;
  90
  91#if !CONFIG_IS_ENABLED(DM_I2C)
  92        i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  93#else
  94        struct udevice *dev;
  95
  96        if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  97                dm_i2c_write(dev, 0x0b, &val, 1);
  98#endif
  99#endif
 100
 101#if defined(CONFIG_TARGET_LS1028ARDB)
 102        u8 reg;
 103
 104        reg = QIXIS_READ(brdcfg[4]);
 105        /*
 106         * Field | Function
 107         * 3     | DisplayPort Power Enable (net DP_PWR_EN):
 108         * DPPWR | 0= DP_PWR is enabled.
 109         */
 110        reg &= ~(DP_PWD_EN_DEFAULT_MASK);
 111        QIXIS_WRITE(brdcfg[4], reg);
 112#endif
 113        return 0;
 114}
 115
 116int board_eth_init(struct bd_info *bis)
 117{
 118        return pci_eth_init(bis);
 119}
 120
 121#ifdef CONFIG_MISC_INIT_R
 122int misc_init_r(void)
 123{
 124        config_board_mux();
 125
 126        return 0;
 127}
 128#endif
 129
 130int board_early_init_f(void)
 131{
 132#ifdef CONFIG_LPUART
 133        u8 uart;
 134#endif
 135
 136#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
 137        i2c_early_init_f();
 138#endif
 139
 140        fsl_lsch3_early_init_f();
 141
 142#ifdef CONFIG_LPUART
 143        /*
 144         * Field| Function
 145         * --------------------------------------------------------------
 146         * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
 147         * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
 148         * --------------------------------------------------------------
 149         * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
 150         * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
 151         */
 152        /* use lpuart0 as system console */
 153        uart = QIXIS_READ(brdcfg[13]);
 154        uart &= ~CFG_LPUART_MUX_MASK;
 155        uart |= CFG_LPUART_EN;
 156        QIXIS_WRITE(brdcfg[13], uart);
 157#endif
 158
 159        return 0;
 160}
 161
 162void detail_board_ddr_info(void)
 163{
 164        puts("\nDDR    ");
 165        print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 166        print_ddr_info(0);
 167}
 168
 169int esdhc_status_fixup(void *blob, const char *compat)
 170{
 171        void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
 172        char esdhc1_path[] = "/soc/mmc@2140000";
 173        char esdhc2_path[] = "/soc/mmc@2150000";
 174        char dspi1_path[] = "/soc/spi@2100000";
 175        char dspi2_path[] = "/soc/spi@2110000";
 176        u32 mux_sdhc1, mux_sdhc2;
 177        u32 io = 0;
 178
 179        /*
 180         * The PMUX IO-expander for mux select is used to control
 181         * the muxing of various onboard interfaces.
 182         */
 183
 184        io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
 185        mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
 186
 187        /* Disable esdhc1/dspi1 if not selected. */
 188        if (mux_sdhc1 != 0)
 189                do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 190                                 sizeof("disabled"), 1);
 191        if (mux_sdhc1 != 2)
 192                do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 193                                 sizeof("disabled"), 1);
 194
 195        io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
 196        mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
 197
 198        /* Disable esdhc2/dspi2 if not selected. */
 199        if (mux_sdhc2 != 0)
 200                do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
 201                                 sizeof("disabled"), 1);
 202        if (mux_sdhc2 != 2)
 203                do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 204                                 sizeof("disabled"), 1);
 205
 206        return 0;
 207}
 208
 209#ifdef CONFIG_OF_BOARD_SETUP
 210int ft_board_setup(void *blob, struct bd_info *bd)
 211{
 212        u64 base[CONFIG_NR_DRAM_BANKS];
 213        u64 size[CONFIG_NR_DRAM_BANKS];
 214
 215        ft_cpu_setup(blob, bd);
 216
 217        /* fixup DT for the two GPP DDR banks */
 218        base[0] = gd->bd->bi_dram[0].start;
 219        size[0] = gd->bd->bi_dram[0].size;
 220        base[1] = gd->bd->bi_dram[1].start;
 221        size[1] = gd->bd->bi_dram[1].size;
 222
 223#ifdef CONFIG_RESV_RAM
 224        /* reduce size if reserved memory is within this bank */
 225        if (gd->arch.resv_ram >= base[0] &&
 226            gd->arch.resv_ram < base[0] + size[0])
 227                size[0] = gd->arch.resv_ram - base[0];
 228        else if (gd->arch.resv_ram >= base[1] &&
 229                 gd->arch.resv_ram < base[1] + size[1])
 230                size[1] = gd->arch.resv_ram - base[1];
 231#endif
 232
 233        fdt_fixup_memory_banks(blob, base, size, 2);
 234
 235        fdt_fixup_icid(blob);
 236
 237#ifdef CONFIG_FSL_ENETC
 238        fdt_fixup_enetc_mac(blob);
 239#endif
 240
 241        return 0;
 242}
 243#endif
 244
 245#ifdef CONFIG_FSL_QIXIS
 246int checkboard(void)
 247{
 248#ifdef CONFIG_TFABOOT
 249        enum boot_src src = get_boot_src();
 250#endif
 251        u8 sw;
 252
 253        int clock;
 254        char *board;
 255        char buf[64] = {0};
 256        static const char *freq[6] = {"100.00", "125.00", "156.25",
 257                                        "161.13", "322.26", "100.00 SS"};
 258
 259        cpu_name(buf);
 260        /* find the board details */
 261        sw = QIXIS_READ(id);
 262
 263        switch (sw) {
 264        case 0x46:
 265                board = "QDS";
 266                break;
 267        case 0x47:
 268                board = "RDB";
 269                break;
 270        case 0x49:
 271                board = "HSSI";
 272                break;
 273        default:
 274                board = "unknown";
 275                break;
 276        }
 277
 278        sw = QIXIS_READ(arch);
 279        printf("Board: %s-%s, Version: %c, boot from ",
 280               buf, board, (sw & 0xf) + 'A' - 1);
 281
 282        sw = QIXIS_READ(brdcfg[0]);
 283        sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 284
 285#ifdef CONFIG_TFABOOT
 286        if (src == BOOT_SOURCE_SD_MMC) {
 287                puts("SD\n");
 288        } else if (src == BOOT_SOURCE_SD_MMC2) {
 289                puts("eMMC\n");
 290        } else {
 291#endif
 292#ifdef CONFIG_SD_BOOT
 293                puts("SD\n");
 294#elif defined(CONFIG_EMMC_BOOT)
 295                puts("eMMC\n");
 296#else
 297                switch (sw) {
 298                case 0:
 299                case 4:
 300                        printf("NOR\n");
 301                        break;
 302                case 1:
 303                        printf("NAND\n");
 304                        break;
 305                default:
 306                        printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 307                        break;
 308                }
 309#endif
 310#ifdef CONFIG_TFABOOT
 311        }
 312#endif
 313
 314        printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 315        puts("SERDES1 Reference : ");
 316
 317        sw = QIXIS_READ(brdcfg[2]);
 318#ifdef CONFIG_TARGET_LS1028ARDB
 319        clock = (sw >> 6) & 3;
 320#else
 321        clock = (sw >> 4) & 0xf;
 322#endif
 323
 324        printf("Clock1 = %sMHz ", freq[clock]);
 325#ifdef CONFIG_TARGET_LS1028ARDB
 326        clock = (sw >> 4) & 3;
 327#else
 328        clock = sw & 0xf;
 329#endif
 330        printf("Clock2 = %sMHz\n", freq[clock]);
 331
 332        return 0;
 333}
 334#endif
 335