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6#include <common.h>
7#include <i2c.h>
8#include <fdt_support.h>
9#include <init.h>
10#include <asm/global_data.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/fsl_serdes.h>
14#include <asm/arch/soc.h>
15#include <asm/arch-fsl-layerscape/fsl_icid.h>
16#include <hwconfig.h>
17#include <ahci.h>
18#include <mmc.h>
19#include <scsi.h>
20#include <fm_eth.h>
21#include <fsl_csu.h>
22#include <fsl_esdhc.h>
23#include <fsl_sec.h>
24#include <fsl_dspi.h>
25#include "../common/i2c_mux.h"
26
27#define LS1046A_PORSR1_REG 0x1EE0000
28#define BOOT_SRC_SD 0x20000000
29#define BOOT_SRC_MASK 0xFF800000
30#define BOARD_REV_GPIO_SHIFT 17
31#define BOARD_REV_MASK 0x03
32#define USB2_SEL_MASK 0x00000100
33
34#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
35(((word) & 0x00ff0000) >> 8) | \
36(((word) & 0x0000ff00) << 8) | \
37(((word) & 0x000000ff) << 24))
38#define SPI_MCR_REG 0x2100000
39
40DECLARE_GLOBAL_DATA_PTR;
41
42static inline void demux_select_usb2(void)
43{
44 u32 val;
45 struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
46
47 val = in_be32(&pgpio->gpdir);
48 val |= USB2_SEL_MASK;
49 out_be32(&pgpio->gpdir, val);
50
51 val = in_be32(&pgpio->gpdat);
52 val |= USB2_SEL_MASK;
53 out_be32(&pgpio->gpdat, val);
54}
55
56static inline void set_spi_cs_signal_inactive(void)
57{
58
59 uint mcr_val;
60 uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
61 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
62
63 mcr_val = in_be32(SPI_MCR_REG);
64 mcr_val |= DSPI_MCR_HALT;
65 out_be32(SPI_MCR_REG, mcr_val);
66 out_be32(SPI_MCR_REG, mcr_cfg_val);
67 mcr_val = in_be32(SPI_MCR_REG);
68 mcr_val &= ~DSPI_MCR_HALT;
69 out_be32(SPI_MCR_REG, mcr_val);
70}
71
72int board_early_init_f(void)
73{
74 fsl_lsch2_early_init_f();
75
76 return 0;
77}
78
79static inline uint8_t get_board_version(void)
80{
81 struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
82
83
84 u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
85 & BOARD_REV_MASK;
86
87
88 u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
89
90 return val;
91}
92
93int checkboard(void)
94{
95 static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
96 u32 boot_src;
97 u8 rev;
98
99 rev = get_board_version();
100 switch (rev) {
101 case 0x00:
102 puts("Board: LS1046AFRWY, Rev: A, boot from ");
103 break;
104 case 0x01:
105 puts("Board: LS1046AFRWY, Rev: B, boot from ");
106 break;
107 default:
108 puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
109 break;
110 }
111 boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
112
113 if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
114 puts("SD\n");
115 else
116 puts("QSPI\n");
117 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
118
119 return 0;
120}
121
122int board_init(void)
123{
124#ifdef CONFIG_NXP_ESBC
125
126
127
128
129
130
131 u32 val;
132val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
133 out_le32(SMMU_SCR0, val);
134 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
135 out_le32(SMMU_NSCR0, val);
136#endif
137
138#ifdef CONFIG_FSL_CAAM
139 sec_init();
140#endif
141
142 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
143 return 0;
144}
145
146int board_setup_core_volt(u32 vdd)
147{
148 return 0;
149}
150
151void config_board_mux(void)
152{
153#ifdef CONFIG_HAS_FSL_XHCI_USB
154 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
155 u32 usb_pwrfault;
156
157
158
159
160 out_be32(&scfg->rcwpmuxcr0, 0x3300);
161#ifdef CONFIG_HAS_FSL_IIC3
162
163 out_be32(&scfg->rcwpmuxcr0, 0x0000);
164#endif
165 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
166 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
167 SCFG_USBPWRFAULT_USB3_SHIFT) |
168 (SCFG_USBPWRFAULT_DEDICATED <<
169 SCFG_USBPWRFAULT_USB2_SHIFT) |
170 (SCFG_USBPWRFAULT_SHARED <<
171 SCFG_USBPWRFAULT_USB1_SHIFT);
172 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
173#ifndef CONFIG_HAS_FSL_IIC3
174
175
176
177
178
179
180
181
182
183 demux_select_usb2();
184#endif
185#endif
186 set_spi_cs_signal_inactive();
187}
188
189#ifdef CONFIG_MISC_INIT_R
190int misc_init_r(void)
191{
192 config_board_mux();
193 return 0;
194}
195#endif
196
197int ft_board_setup(void *blob, struct bd_info *bd)
198{
199 u64 base[CONFIG_NR_DRAM_BANKS];
200 u64 size[CONFIG_NR_DRAM_BANKS];
201
202
203 base[0] = gd->bd->bi_dram[0].start;
204 size[0] = gd->bd->bi_dram[0].size;
205 base[1] = gd->bd->bi_dram[1].start;
206 size[1] = gd->bd->bi_dram[1].size;
207
208 fdt_fixup_memory_banks(blob, base, size, 2);
209 ft_cpu_setup(blob, bd);
210
211#ifdef CONFIG_SYS_DPAA_FMAN
212#ifndef CONFIG_DM_ETH
213 fdt_fixup_fman_ethernet(blob);
214#endif
215#endif
216
217 fdt_fixup_icid(blob);
218
219 return 0;
220}
221