1
2
3
4
5
6
7#include <common.h>
8#include <i2c.h>
9#include <fdt_support.h>
10#include <fsl_ddr_sdram.h>
11#include <init.h>
12#include <asm/global_data.h>
13#include <asm/io.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/fsl_serdes.h>
16#include <asm/arch/ppa.h>
17#include <asm/arch/fdt.h>
18#include <asm/arch/mmu.h>
19#include <asm/arch/cpu.h>
20#include <asm/arch/soc.h>
21#include <asm/arch-fsl-layerscape/fsl_icid.h>
22#include <ahci.h>
23#include <hwconfig.h>
24#include <mmc.h>
25#include <scsi.h>
26#include <fm_eth.h>
27#include <fsl_csu.h>
28#include <fsl_esdhc.h>
29#include <fsl_ifc.h>
30#include <fsl_sec.h>
31#include <spl.h>
32#include "../common/i2c_mux.h"
33
34#include "../common/vid.h"
35#include "../common/qixis.h"
36#include "ls1046aqds_qixis.h"
37
38DECLARE_GLOBAL_DATA_PTR;
39
40#ifdef CONFIG_TFABOOT
41struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
42 {
43 "nor0",
44 CONFIG_SYS_NOR0_CSPR,
45 CONFIG_SYS_NOR0_CSPR_EXT,
46 CONFIG_SYS_NOR_AMASK,
47 CONFIG_SYS_NOR_CSOR,
48 {
49 CONFIG_SYS_NOR_FTIM0,
50 CONFIG_SYS_NOR_FTIM1,
51 CONFIG_SYS_NOR_FTIM2,
52 CONFIG_SYS_NOR_FTIM3
53 },
54
55 },
56 {
57 "nor1",
58 CONFIG_SYS_NOR1_CSPR,
59 CONFIG_SYS_NOR1_CSPR_EXT,
60 CONFIG_SYS_NOR_AMASK,
61 CONFIG_SYS_NOR_CSOR,
62 {
63 CONFIG_SYS_NOR_FTIM0,
64 CONFIG_SYS_NOR_FTIM1,
65 CONFIG_SYS_NOR_FTIM2,
66 CONFIG_SYS_NOR_FTIM3
67 },
68 },
69 {
70 "nand",
71 CONFIG_SYS_NAND_CSPR,
72 CONFIG_SYS_NAND_CSPR_EXT,
73 CONFIG_SYS_NAND_AMASK,
74 CONFIG_SYS_NAND_CSOR,
75 {
76 CONFIG_SYS_NAND_FTIM0,
77 CONFIG_SYS_NAND_FTIM1,
78 CONFIG_SYS_NAND_FTIM2,
79 CONFIG_SYS_NAND_FTIM3
80 },
81 },
82 {
83 "fpga",
84 CONFIG_SYS_FPGA_CSPR,
85 CONFIG_SYS_FPGA_CSPR_EXT,
86 CONFIG_SYS_FPGA_AMASK,
87 CONFIG_SYS_FPGA_CSOR,
88 {
89 CONFIG_SYS_FPGA_FTIM0,
90 CONFIG_SYS_FPGA_FTIM1,
91 CONFIG_SYS_FPGA_FTIM2,
92 CONFIG_SYS_FPGA_FTIM3
93 },
94 }
95};
96
97struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
98 {
99 "nand",
100 CONFIG_SYS_NAND_CSPR,
101 CONFIG_SYS_NAND_CSPR_EXT,
102 CONFIG_SYS_NAND_AMASK,
103 CONFIG_SYS_NAND_CSOR,
104 {
105 CONFIG_SYS_NAND_FTIM0,
106 CONFIG_SYS_NAND_FTIM1,
107 CONFIG_SYS_NAND_FTIM2,
108 CONFIG_SYS_NAND_FTIM3
109 },
110 },
111 {
112 "nor0",
113 CONFIG_SYS_NOR0_CSPR,
114 CONFIG_SYS_NOR0_CSPR_EXT,
115 CONFIG_SYS_NOR_AMASK,
116 CONFIG_SYS_NOR_CSOR,
117 {
118 CONFIG_SYS_NOR_FTIM0,
119 CONFIG_SYS_NOR_FTIM1,
120 CONFIG_SYS_NOR_FTIM2,
121 CONFIG_SYS_NOR_FTIM3
122 },
123 },
124 {
125 "nor1",
126 CONFIG_SYS_NOR1_CSPR,
127 CONFIG_SYS_NOR1_CSPR_EXT,
128 CONFIG_SYS_NOR_AMASK,
129 CONFIG_SYS_NOR_CSOR,
130 {
131 CONFIG_SYS_NOR_FTIM0,
132 CONFIG_SYS_NOR_FTIM1,
133 CONFIG_SYS_NOR_FTIM2,
134 CONFIG_SYS_NOR_FTIM3
135 },
136 },
137 {
138 "fpga",
139 CONFIG_SYS_FPGA_CSPR,
140 CONFIG_SYS_FPGA_CSPR_EXT,
141 CONFIG_SYS_FPGA_AMASK,
142 CONFIG_SYS_FPGA_CSOR,
143 {
144 CONFIG_SYS_FPGA_FTIM0,
145 CONFIG_SYS_FPGA_FTIM1,
146 CONFIG_SYS_FPGA_FTIM2,
147 CONFIG_SYS_FPGA_FTIM3
148 },
149 }
150};
151
152void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
153{
154 enum boot_src src = get_boot_src();
155
156 if (src == BOOT_SOURCE_IFC_NAND)
157 regs_info->regs = ifc_cfg_nand_boot;
158 else
159 regs_info->regs = ifc_cfg_nor_boot;
160 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
161}
162
163#endif
164
165enum {
166 MUX_TYPE_GPIO,
167};
168
169int checkboard(void)
170{
171#ifdef CONFIG_TFABOOT
172 enum boot_src src = get_boot_src();
173#endif
174 char buf[64];
175#ifndef CONFIG_SD_BOOT
176 u8 sw;
177#endif
178
179 puts("Board: LS1046AQDS, boot from ");
180
181#ifdef CONFIG_TFABOOT
182 if (src == BOOT_SOURCE_SD_MMC)
183 puts("SD\n");
184 else {
185#endif
186
187#ifdef CONFIG_SD_BOOT
188 puts("SD\n");
189#else
190 sw = QIXIS_READ(brdcfg[0]);
191 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
192
193 if (sw < 0x8)
194 printf("vBank: %d\n", sw);
195 else if (sw == 0x8)
196 puts("PromJet\n");
197 else if (sw == 0x9)
198 puts("NAND\n");
199 else if (sw == 0xF)
200 printf("QSPI\n");
201 else
202 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
203#endif
204
205#ifdef CONFIG_TFABOOT
206 }
207#endif
208 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
209 QIXIS_READ(id), QIXIS_READ(arch));
210
211 printf("FPGA: v%d (%s), build %d\n",
212 (int)QIXIS_READ(scver), qixis_read_tag(buf),
213 (int)qixis_read_minor());
214
215 return 0;
216}
217
218bool if_board_diff_clk(void)
219{
220 u8 diff_conf = QIXIS_READ(brdcfg[11]);
221
222 return diff_conf & 0x40;
223}
224
225unsigned long get_board_sys_clk(void)
226{
227 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
228
229 switch (sysclk_conf & 0x0f) {
230 case QIXIS_SYSCLK_64:
231 return 64000000;
232 case QIXIS_SYSCLK_83:
233 return 83333333;
234 case QIXIS_SYSCLK_100:
235 return 100000000;
236 case QIXIS_SYSCLK_125:
237 return 125000000;
238 case QIXIS_SYSCLK_133:
239 return 133333333;
240 case QIXIS_SYSCLK_150:
241 return 150000000;
242 case QIXIS_SYSCLK_160:
243 return 160000000;
244 case QIXIS_SYSCLK_166:
245 return 166666666;
246 }
247
248 return 66666666;
249}
250
251unsigned long get_board_ddr_clk(void)
252{
253 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
254
255 if (if_board_diff_clk())
256 return get_board_sys_clk();
257 switch ((ddrclk_conf & 0x30) >> 4) {
258 case QIXIS_DDRCLK_100:
259 return 100000000;
260 case QIXIS_DDRCLK_125:
261 return 125000000;
262 case QIXIS_DDRCLK_133:
263 return 133333333;
264 }
265
266 return 66666666;
267}
268
269#ifdef CONFIG_LPUART
270u32 get_lpuart_clk(void)
271{
272 return gd->bus_clk;
273}
274#endif
275
276int dram_init(void)
277{
278
279
280
281
282
283
284
285 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
286 fsl_initdram();
287#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
288 defined(CONFIG_SPL_BUILD)
289
290 update_early_mmu_table();
291#endif
292
293 return 0;
294}
295
296int i2c_multiplexer_select_vid_channel(u8 channel)
297{
298 return select_i2c_ch_pca9547(channel, 0);
299}
300
301int board_early_init_f(void)
302{
303 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
304#ifdef CONFIG_HAS_FSL_XHCI_USB
305 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
306 u32 usb_pwrfault;
307#endif
308#ifdef CONFIG_LPUART
309 u8 uart;
310#endif
311
312
313
314
315 out_le32(cntcr, 0x1);
316
317#if defined(CONFIG_SYS_I2C_EARLY_INIT)
318 i2c_early_init_f();
319#endif
320 fsl_lsch2_early_init_f();
321
322#ifdef CONFIG_HAS_FSL_XHCI_USB
323 out_be32(&scfg->rcwpmuxcr0, 0x3333);
324 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
325 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
326 SCFG_USBPWRFAULT_USB3_SHIFT) |
327 (SCFG_USBPWRFAULT_DEDICATED <<
328 SCFG_USBPWRFAULT_USB2_SHIFT) |
329 (SCFG_USBPWRFAULT_SHARED <<
330 SCFG_USBPWRFAULT_USB1_SHIFT);
331 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
332#endif
333
334#ifdef CONFIG_LPUART
335
336 uart = QIXIS_READ(brdcfg[14]);
337 uart &= ~CFG_UART_MUX_MASK;
338 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
339 QIXIS_WRITE(brdcfg[14], uart);
340#endif
341
342 return 0;
343}
344
345#ifdef CONFIG_FSL_DEEP_SLEEP
346
347bool is_warm_boot(void)
348{
349#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
350 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
351
352 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
353 return 1;
354
355 return 0;
356}
357#endif
358
359int config_board_mux(int ctrl_type)
360{
361 u8 reg14;
362
363 reg14 = QIXIS_READ(brdcfg[14]);
364
365 switch (ctrl_type) {
366 case MUX_TYPE_GPIO:
367 reg14 = (reg14 & (~0x6)) | 0x2;
368 break;
369 default:
370 puts("Unsupported mux interface type\n");
371 return -1;
372 }
373
374 QIXIS_WRITE(brdcfg[14], reg14);
375
376 return 0;
377}
378
379int config_serdes_mux(void)
380{
381 return 0;
382}
383
384#ifdef CONFIG_MISC_INIT_R
385int misc_init_r(void)
386{
387 if (hwconfig("gpio"))
388 config_board_mux(MUX_TYPE_GPIO);
389
390 return 0;
391}
392#endif
393
394int board_init(void)
395{
396 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
397
398#ifdef CONFIG_SYS_FSL_SERDES
399 config_serdes_mux();
400#endif
401
402 if (adjust_vdd(0))
403 printf("Warning: Adjusting core voltage failed.\n");
404
405#ifdef CONFIG_FSL_LS_PPA
406 ppa_init();
407#endif
408
409#ifdef CONFIG_NXP_ESBC
410
411
412
413
414
415
416 u32 val;
417 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
418 out_le32(SMMU_SCR0, val);
419 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
420 out_le32(SMMU_NSCR0, val);
421#endif
422
423#ifdef CONFIG_FSL_CAAM
424 sec_init();
425#endif
426
427 return 0;
428}
429
430#ifdef CONFIG_OF_BOARD_SETUP
431int ft_board_setup(void *blob, struct bd_info *bd)
432{
433 u64 base[CONFIG_NR_DRAM_BANKS];
434 u64 size[CONFIG_NR_DRAM_BANKS];
435 u8 reg;
436
437
438 base[0] = gd->bd->bi_dram[0].start;
439 size[0] = gd->bd->bi_dram[0].size;
440 base[1] = gd->bd->bi_dram[1].start;
441 size[1] = gd->bd->bi_dram[1].size;
442
443 fdt_fixup_memory_banks(blob, base, size, 2);
444 ft_cpu_setup(blob, bd);
445
446#ifdef CONFIG_SYS_DPAA_FMAN
447#ifndef CONFIG_DM_ETH
448 fdt_fixup_fman_ethernet(blob);
449#endif
450 fdt_fixup_board_enet(blob);
451#endif
452
453 fdt_fixup_icid(blob);
454
455 reg = QIXIS_READ(brdcfg[0]);
456 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
457
458
459 if (reg == 0xF)
460 do_fixup_by_compat(blob, "fsl,ifc",
461 "status", "disabled", 8 + 1, 1);
462
463 return 0;
464}
465#endif
466
467u8 flash_read8(void *addr)
468{
469 return __raw_readb(addr + 1);
470}
471
472void flash_write16(u16 val, void *addr)
473{
474 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
475
476 __raw_writew(shftval, addr);
477}
478
479u16 flash_read16(void *addr)
480{
481 u16 val = __raw_readw(addr);
482
483 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
484}
485
486#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
487void *env_sf_get_env_addr(void)
488{
489 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
490}
491#endif
492
