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5#include <common.h>
6#include <env.h>
7#include <init.h>
8#include <malloc.h>
9#include <errno.h>
10#include <netdev.h>
11#include <fsl_ifc.h>
12#include <fsl_ddr.h>
13#include <asm/global_data.h>
14#include <asm/io.h>
15#include <fdt_support.h>
16#include <linux/libfdt.h>
17#include <fsl-mc/fsl_mc.h>
18#include <env_internal.h>
19#include <i2c.h>
20#include <rtc.h>
21#include <asm/arch/soc.h>
22#include <hwconfig.h>
23#include <fsl_sec.h>
24#include <asm/arch/ppa.h>
25#include <asm/arch-fsl-layerscape/fsl_icid.h>
26#include "../common/i2c_mux.h"
27
28#include "../common/qixis.h"
29#include "ls2080aqds_qixis.h"
30#include "../common/vid.h"
31
32#define PIN_MUX_SEL_SDHC 0x00
33#define PIN_MUX_SEL_DSPI 0x0a
34#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
35
36#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
37
38DECLARE_GLOBAL_DATA_PTR;
39
40enum {
41 MUX_TYPE_SDHC,
42 MUX_TYPE_DSPI,
43};
44
45unsigned long long get_qixis_addr(void)
46{
47 unsigned long long addr;
48
49 if (gd->flags & GD_FLG_RELOC)
50 addr = QIXIS_BASE_PHYS;
51 else
52 addr = QIXIS_BASE_PHYS_EARLY;
53
54
55
56
57
58 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
59
60 return addr;
61}
62
63int checkboard(void)
64{
65 char buf[64];
66 u8 sw;
67 static const char *const freq[] = {"100", "125", "156.25",
68 "100 separate SSCG"};
69 int clock;
70
71 cpu_name(buf);
72 printf("Board: %s-QDS, ", buf);
73
74 sw = QIXIS_READ(arch);
75 printf("Board Arch: V%d, ", sw >> 4);
76 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
77
78 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
79
80 sw = QIXIS_READ(brdcfg[0]);
81 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
82
83 if (sw < 0x8)
84 printf("vBank: %d\n", sw);
85 else if (sw == 0x8)
86 puts("PromJet\n");
87 else if (sw == 0x9)
88 puts("NAND\n");
89 else if (sw == 0xf)
90 puts("QSPI\n");
91 else if (sw == 0x15)
92 printf("IFCCard\n");
93 else
94 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
95
96 printf("FPGA: v%d (%s), build %d",
97 (int)QIXIS_READ(scver), qixis_read_tag(buf),
98 (int)qixis_read_minor());
99
100 printf(" on %s", qixis_read_time(buf));
101
102
103
104
105
106
107
108
109
110 puts("SERDES1 Reference : ");
111 sw = QIXIS_READ(brdcfg[2]);
112 clock = (sw >> 6) & 3;
113 printf("Clock1 = %sMHz ", freq[clock]);
114 clock = (sw >> 4) & 3;
115 printf("Clock2 = %sMHz", freq[clock]);
116
117 puts("\nSERDES2 Reference : ");
118 clock = (sw >> 2) & 3;
119 printf("Clock1 = %sMHz ", freq[clock]);
120 clock = (sw >> 0) & 3;
121 printf("Clock2 = %sMHz\n", freq[clock]);
122
123 return 0;
124}
125
126unsigned long get_board_sys_clk(void)
127{
128 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
129
130 switch (sysclk_conf & 0x0F) {
131 case QIXIS_SYSCLK_83:
132 return 83333333;
133 case QIXIS_SYSCLK_100:
134 return 100000000;
135 case QIXIS_SYSCLK_125:
136 return 125000000;
137 case QIXIS_SYSCLK_133:
138 return 133333333;
139 case QIXIS_SYSCLK_150:
140 return 150000000;
141 case QIXIS_SYSCLK_160:
142 return 160000000;
143 case QIXIS_SYSCLK_166:
144 return 166666666;
145 }
146 return 66666666;
147}
148
149unsigned long get_board_ddr_clk(void)
150{
151 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
152
153 switch ((ddrclk_conf & 0x30) >> 4) {
154 case QIXIS_DDRCLK_100:
155 return 100000000;
156 case QIXIS_DDRCLK_125:
157 return 125000000;
158 case QIXIS_DDRCLK_133:
159 return 133333333;
160 }
161 return 66666666;
162}
163
164int config_board_mux(int ctrl_type)
165{
166 u8 reg5;
167
168 reg5 = QIXIS_READ(brdcfg[5]);
169
170 switch (ctrl_type) {
171 case MUX_TYPE_SDHC:
172 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
173 break;
174 case MUX_TYPE_DSPI:
175 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
176 break;
177 default:
178 printf("Wrong mux interface type\n");
179 return -1;
180 }
181
182 QIXIS_WRITE(brdcfg[5], reg5);
183
184 return 0;
185}
186
187int board_init(void)
188{
189 char *env_hwconfig;
190 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
191 u32 val;
192
193 init_final_memctl_regs();
194
195 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
196
197 env_hwconfig = env_get("hwconfig");
198
199 if (hwconfig_f("dspi", env_hwconfig) &&
200 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
201 config_board_mux(MUX_TYPE_DSPI);
202 else
203 config_board_mux(MUX_TYPE_SDHC);
204
205#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
206 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
207
208 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
209 QIXIS_WRITE(brdcfg[9],
210 (QIXIS_READ(brdcfg[9]) & 0xf8) |
211 FSL_QIXIS_BRDCFG9_QSPI);
212#endif
213
214 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
215
216#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
217#if CONFIG_IS_ENABLED(DM_I2C)
218 rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
219#else
220 rtc_enable_32khz_output();
221#endif
222#endif
223
224#ifdef CONFIG_FSL_CAAM
225 sec_init();
226#endif
227
228#ifdef CONFIG_FSL_LS_PPA
229 ppa_init();
230#endif
231
232#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
233 pci_init();
234#endif
235
236 return 0;
237}
238
239int board_early_init_f(void)
240{
241#if defined(CONFIG_SYS_I2C_EARLY_INIT)
242 i2c_early_init_f();
243#endif
244 fsl_lsch3_early_init_f();
245#ifdef CONFIG_FSL_QSPI
246
247 out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
248#endif
249 return 0;
250}
251
252int misc_init_r(void)
253{
254 if (adjust_vdd(0))
255 printf("Warning: Adjusting core voltage failed.\n");
256
257 return 0;
258}
259
260void detail_board_ddr_info(void)
261{
262 puts("\nDDR ");
263 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
264 print_ddr_info(0);
265#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
266 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
267 puts("\nDP-DDR ");
268 print_size(gd->bd->bi_dram[2].size, "");
269 print_ddr_info(CONFIG_DP_DDR_CTRL);
270 }
271#endif
272}
273
274#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
275void fdt_fixup_board_enet(void *fdt)
276{
277 int offset;
278
279 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
280
281 if (offset < 0)
282 offset = fdt_path_offset(fdt, "/fsl-mc");
283
284 if (offset < 0) {
285 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
286 __func__, offset);
287 return;
288 }
289
290 if (get_mc_boot_status() == 0 &&
291 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
292 fdt_status_okay(fdt, offset);
293 else
294 fdt_status_fail(fdt, offset);
295}
296
297void board_quiesce_devices(void)
298{
299 fsl_mc_ldpaa_exit(gd->bd);
300}
301#endif
302
303#ifdef CONFIG_OF_BOARD_SETUP
304int ft_board_setup(void *blob, struct bd_info *bd)
305{
306 u64 base[CONFIG_NR_DRAM_BANKS];
307 u64 size[CONFIG_NR_DRAM_BANKS];
308
309 ft_cpu_setup(blob, bd);
310
311
312 base[0] = gd->bd->bi_dram[0].start;
313 size[0] = gd->bd->bi_dram[0].size;
314 base[1] = gd->bd->bi_dram[1].start;
315 size[1] = gd->bd->bi_dram[1].size;
316
317#ifdef CONFIG_RESV_RAM
318
319 if (gd->arch.resv_ram >= base[0] &&
320 gd->arch.resv_ram < base[0] + size[0])
321 size[0] = gd->arch.resv_ram - base[0];
322 else if (gd->arch.resv_ram >= base[1] &&
323 gd->arch.resv_ram < base[1] + size[1])
324 size[1] = gd->arch.resv_ram - base[1];
325#endif
326
327 fdt_fixup_memory_banks(blob, base, size, 2);
328
329 fdt_fsl_mc_fixup_iommu_map_entry(blob);
330
331 fsl_fdt_fixup_dr_usb(blob, bd);
332
333#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
334 fdt_fixup_board_enet(blob);
335#endif
336
337 fdt_fixup_icid(blob);
338
339 return 0;
340}
341#endif
342
343void qixis_dump_switch(void)
344{
345 int i, nr_of_cfgsw;
346
347 QIXIS_WRITE(cms[0], 0x00);
348 nr_of_cfgsw = QIXIS_READ(cms[1]);
349
350 puts("DIP switch settings dump:\n");
351 for (i = 1; i <= nr_of_cfgsw; i++) {
352 QIXIS_WRITE(cms[0], i);
353 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
354 }
355}
356
