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6#include <common.h>
7#include <env.h>
8#include <init.h>
9#include <malloc.h>
10#include <errno.h>
11#include <netdev.h>
12#include <fsl_ifc.h>
13#include <fsl_ddr.h>
14#include <asm/global_data.h>
15#include <asm/io.h>
16#include <hwconfig.h>
17#include <fdt_support.h>
18#include <linux/libfdt.h>
19#include <fsl-mc/fsl_mc.h>
20#include <env_internal.h>
21#include <efi_loader.h>
22#include <i2c.h>
23#include <asm/arch/mmu.h>
24#include <asm/arch/soc.h>
25#include <asm/arch/ppa.h>
26#include <fsl_sec.h>
27#include <asm/arch-fsl-layerscape/fsl_icid.h>
28#include "../common/i2c_mux.h"
29
30#ifdef CONFIG_FSL_QIXIS
31#include "../common/qixis.h"
32#include "ls2080ardb_qixis.h"
33#endif
34#include "../common/vid.h"
35
36#define CORTINA_FW_ADDR_IFCNOR 0x580980000
37#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0x584980000
38#define CORTINA_FW_ADDR_QSPI 0x980000
39#define PIN_MUX_SEL_SDHC 0x00
40#define PIN_MUX_SEL_DSPI 0x0a
41
42#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
43DECLARE_GLOBAL_DATA_PTR;
44
45enum {
46 MUX_TYPE_SDHC,
47 MUX_TYPE_DSPI,
48};
49
50#ifdef CONFIG_VID
51u16 soc_get_fuse_vid(int vid_index)
52{
53 static const u16 vdd[32] = {
54 10500,
55 0,
56 9750,
57 0,
58 9500,
59 0,
60 0,
61 0,
62 9000,
63 0,
64 0,
65 0,
66 0,
67 0,
68 0,
69 0,
70 10000,
71 0,
72 10250,
73 0,
74 10500,
75 0,
76 0,
77 0,
78 0,
79 0,
80 0,
81 0,
82 0,
83 0,
84 0,
85 0,
86 };
87
88 return vdd[vid_index];
89};
90#endif
91
92unsigned long long get_qixis_addr(void)
93{
94 unsigned long long addr;
95
96 if (gd->flags & GD_FLG_RELOC)
97 addr = QIXIS_BASE_PHYS;
98 else
99 addr = QIXIS_BASE_PHYS_EARLY;
100
101
102
103
104
105 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
106
107 return addr;
108}
109
110int checkboard(void)
111{
112#ifdef CONFIG_FSL_QIXIS
113 u8 sw;
114#endif
115 char buf[15];
116
117 cpu_name(buf);
118 printf("Board: %s-RDB, ", buf);
119
120#ifdef CONFIG_TARGET_LS2081ARDB
121#ifdef CONFIG_FSL_QIXIS
122 sw = QIXIS_READ(arch);
123 printf("Board version: %c, ", (sw & 0xf) + 'A');
124
125 sw = QIXIS_READ(brdcfg[0]);
126 sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
127 switch (sw) {
128 case 0:
129 puts("boot from QSPI DEV#0\n");
130 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
131 break;
132 case 1:
133 puts("boot from QSPI DEV#1\n");
134 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
135 break;
136 case 2:
137 puts("boot from QSPI EMU\n");
138 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
139 break;
140 case 3:
141 puts("boot from QSPI EMU\n");
142 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
143 break;
144 case 4:
145 puts("boot from QSPI DEV#0\n");
146 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
147 break;
148 default:
149 printf("invalid setting of SW%u\n", sw);
150 break;
151 }
152 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
153#endif
154 puts("SERDES1 Reference : ");
155 printf("Clock1 = 100MHz ");
156 printf("Clock2 = 161.13MHz");
157#else
158#ifdef CONFIG_FSL_QIXIS
159 sw = QIXIS_READ(arch);
160 printf("Board Arch: V%d, ", sw >> 4);
161 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
162
163 sw = QIXIS_READ(brdcfg[0]);
164 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
165
166 if (sw < 0x8)
167 printf("vBank: %d\n", sw);
168 else if (sw == 0x9)
169 puts("NAND\n");
170 else
171 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
172
173 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
174#endif
175 puts("SERDES1 Reference : ");
176 printf("Clock1 = 156.25MHz ");
177 printf("Clock2 = 156.25MHz");
178#endif
179
180 puts("\nSERDES2 Reference : ");
181 printf("Clock1 = 100MHz ");
182 printf("Clock2 = 100MHz\n");
183
184 return 0;
185}
186
187unsigned long get_board_sys_clk(void)
188{
189#ifdef CONFIG_FSL_QIXIS
190 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
191
192 switch (sysclk_conf & 0x0F) {
193 case QIXIS_SYSCLK_83:
194 return 83333333;
195 case QIXIS_SYSCLK_100:
196 return 100000000;
197 case QIXIS_SYSCLK_125:
198 return 125000000;
199 case QIXIS_SYSCLK_133:
200 return 133333333;
201 case QIXIS_SYSCLK_150:
202 return 150000000;
203 case QIXIS_SYSCLK_160:
204 return 160000000;
205 case QIXIS_SYSCLK_166:
206 return 166666666;
207 }
208#endif
209 return 100000000;
210}
211
212int i2c_multiplexer_select_vid_channel(u8 channel)
213{
214 return select_i2c_ch_pca9547(channel, 0);
215}
216
217int config_board_mux(int ctrl_type)
218{
219#ifdef CONFIG_FSL_QIXIS
220 u8 reg5;
221
222 reg5 = QIXIS_READ(brdcfg[5]);
223
224 switch (ctrl_type) {
225 case MUX_TYPE_SDHC:
226 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
227 break;
228 case MUX_TYPE_DSPI:
229 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
230 break;
231 default:
232 printf("Wrong mux interface type\n");
233 return -1;
234 }
235
236 QIXIS_WRITE(brdcfg[5], reg5);
237#endif
238 return 0;
239}
240
241ulong *cs4340_get_fw_addr(void)
242{
243#ifdef CONFIG_TFABOOT
244 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
245 u32 svr = gur_in32(&gur->svr);
246#endif
247 ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
248
249#ifdef CONFIG_TFABOOT
250
251 if (SVR_SOC_VER(svr) == SVR_LS2088A) {
252 enum boot_src src = get_boot_src();
253 u8 sw;
254
255 switch (src) {
256 case BOOT_SOURCE_IFC_NOR:
257 sw = QIXIS_READ(brdcfg[0]);
258 sw = (sw & 0x0f);
259 if (sw == 0)
260 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
261 else if (sw == 4)
262 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
263 break;
264 case BOOT_SOURCE_QSPI_NOR:
265
266 cortina_fw_addr = CORTINA_FW_ADDR_QSPI;
267 break;
268 default:
269 printf("WARNING: Boot source not found\n");
270 }
271 }
272#endif
273 return (ulong *)cortina_fw_addr;
274}
275
276int board_init(void)
277{
278#ifdef CONFIG_FSL_MC_ENET
279 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
280#endif
281
282 init_final_memctl_regs();
283
284 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
285
286#ifdef CONFIG_FSL_QIXIS
287 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
288#endif
289
290#ifdef CONFIG_FSL_CAAM
291 sec_init();
292#endif
293#ifdef CONFIG_FSL_LS_PPA
294 ppa_init();
295#endif
296
297#ifdef CONFIG_FSL_MC_ENET
298
299 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
300#endif
301#ifdef CONFIG_FSL_CAAM
302 sec_init();
303#endif
304
305#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
306 pci_init();
307#endif
308
309 return 0;
310}
311
312int board_early_init_f(void)
313{
314#if defined(CONFIG_SYS_I2C_EARLY_INIT)
315 i2c_early_init_f();
316#endif
317 fsl_lsch3_early_init_f();
318 return 0;
319}
320
321int misc_init_r(void)
322{
323 char *env_hwconfig;
324 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
325 u32 val;
326 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
327 u32 svr = gur_in32(&gur->svr);
328
329 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
330
331 env_hwconfig = env_get("hwconfig");
332
333 if (hwconfig_f("dspi", env_hwconfig) &&
334 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
335 config_board_mux(MUX_TYPE_DSPI);
336 else
337 config_board_mux(MUX_TYPE_SDHC);
338
339
340
341
342
343
344#ifdef CONFIG_TARGET_LS2081ARDB
345 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
346 in_le32(GPIO4_GPDIR_ADDR)));
347 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
348 in_le32(GPIO4_GPDAT_ADDR)));
349#endif
350 if (hwconfig("sdhc"))
351 config_board_mux(MUX_TYPE_SDHC);
352
353 if (adjust_vdd(0))
354 printf("Warning: Adjusting core voltage failed.\n");
355
356
357
358
359 if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
360 (SVR_SOC_VER(svr) == SVR_LS2048A))
361 env_set("board", "ls2088ardb");
362 else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
363 (SVR_SOC_VER(svr) == SVR_LS2041A))
364 env_set("board", "ls2081ardb");
365
366 return 0;
367}
368
369void detail_board_ddr_info(void)
370{
371 puts("\nDDR ");
372 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
373 print_ddr_info(0);
374#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
375 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
376 puts("\nDP-DDR ");
377 print_size(gd->bd->bi_dram[2].size, "");
378 print_ddr_info(CONFIG_DP_DDR_CTRL);
379 }
380#endif
381}
382
383#ifdef CONFIG_FSL_MC_ENET
384void fdt_fixup_board_enet(void *fdt)
385{
386 int offset;
387
388 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
389
390 if (offset < 0)
391 offset = fdt_path_offset(fdt, "/fsl-mc");
392
393 if (offset < 0) {
394 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
395 __func__, offset);
396 return;
397 }
398
399 if (get_mc_boot_status() == 0 &&
400 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
401 fdt_status_okay(fdt, offset);
402 else
403 fdt_status_fail(fdt, offset);
404}
405
406void board_quiesce_devices(void)
407{
408 fsl_mc_ldpaa_exit(gd->bd);
409}
410#endif
411
412#ifdef CONFIG_OF_BOARD_SETUP
413void fsl_fdt_fixup_flash(void *fdt)
414{
415 int offset;
416#ifdef CONFIG_TFABOOT
417 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
418 u32 val;
419#endif
420
421
422
423
424
425
426#ifdef CONFIG_TFABOOT
427 enum boot_src src = get_boot_src();
428 bool disable_ifc = false;
429
430 switch (src) {
431 case BOOT_SOURCE_IFC_NOR:
432 disable_ifc = false;
433 break;
434 case BOOT_SOURCE_QSPI_NOR:
435 disable_ifc = true;
436 break;
437 default:
438 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
439 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
440 disable_ifc = true;
441 break;
442 }
443
444 if (disable_ifc) {
445 offset = fdt_path_offset(fdt, "/soc/ifc");
446
447 if (offset < 0)
448 offset = fdt_path_offset(fdt, "/ifc");
449 } else {
450 offset = fdt_path_offset(fdt, "/soc/quadspi");
451
452 if (offset < 0)
453 offset = fdt_path_offset(fdt, "/quadspi");
454 }
455
456#else
457#ifdef CONFIG_FSL_QSPI
458 offset = fdt_path_offset(fdt, "/soc/ifc");
459
460 if (offset < 0)
461 offset = fdt_path_offset(fdt, "/ifc");
462#else
463 offset = fdt_path_offset(fdt, "/soc/quadspi");
464
465 if (offset < 0)
466 offset = fdt_path_offset(fdt, "/quadspi");
467#endif
468#endif
469
470 if (offset < 0)
471 return;
472
473 fdt_status_disabled(fdt, offset);
474}
475
476int ft_board_setup(void *blob, struct bd_info *bd)
477{
478 int i;
479 u16 mc_memory_bank = 0;
480
481 u64 *base;
482 u64 *size;
483 u64 mc_memory_base = 0;
484 u64 mc_memory_size = 0;
485 u16 total_memory_banks;
486
487 ft_cpu_setup(blob, bd);
488
489 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
490
491 if (mc_memory_base != 0)
492 mc_memory_bank++;
493
494 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
495
496 base = calloc(total_memory_banks, sizeof(u64));
497 size = calloc(total_memory_banks, sizeof(u64));
498
499
500 base[0] = gd->bd->bi_dram[0].start;
501 size[0] = gd->bd->bi_dram[0].size;
502 base[1] = gd->bd->bi_dram[1].start;
503 size[1] = gd->bd->bi_dram[1].size;
504
505#ifdef CONFIG_RESV_RAM
506
507 if (gd->arch.resv_ram >= base[0] &&
508 gd->arch.resv_ram < base[0] + size[0])
509 size[0] = gd->arch.resv_ram - base[0];
510 else if (gd->arch.resv_ram >= base[1] &&
511 gd->arch.resv_ram < base[1] + size[1])
512 size[1] = gd->arch.resv_ram - base[1];
513#endif
514
515 if (mc_memory_base != 0) {
516 for (i = 0; i <= total_memory_banks; i++) {
517 if (base[i] == 0 && size[i] == 0) {
518 base[i] = mc_memory_base;
519 size[i] = mc_memory_size;
520 break;
521 }
522 }
523 }
524
525 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
526
527 fdt_fsl_mc_fixup_iommu_map_entry(blob);
528
529 fsl_fdt_fixup_dr_usb(blob, bd);
530
531 fsl_fdt_fixup_flash(blob);
532
533#ifdef CONFIG_FSL_MC_ENET
534 fdt_fixup_board_enet(blob);
535#endif
536
537 fdt_fixup_icid(blob);
538
539 return 0;
540}
541#endif
542
543void qixis_dump_switch(void)
544{
545#ifdef CONFIG_FSL_QIXIS
546 int i, nr_of_cfgsw;
547
548 QIXIS_WRITE(cms[0], 0x00);
549 nr_of_cfgsw = QIXIS_READ(cms[1]);
550
551 puts("DIP switch settings dump:\n");
552 for (i = 1; i <= nr_of_cfgsw; i++) {
553 QIXIS_WRITE(cms[0], i);
554 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
555 }
556#endif
557}
558
559
560
561
562
563void update_spd_address(unsigned int ctrl_num,
564 unsigned int slot,
565 unsigned int *addr)
566{
567#ifndef CONFIG_TARGET_LS2081ARDB
568#ifdef CONFIG_FSL_QIXIS
569 u8 sw;
570
571 sw = QIXIS_READ(arch);
572 if ((sw & 0xf) < 0x3) {
573 if (ctrl_num == 1 && slot == 0)
574 *addr = SPD_EEPROM_ADDRESS4;
575 else if (ctrl_num == 1 && slot == 1)
576 *addr = SPD_EEPROM_ADDRESS3;
577 }
578#endif
579#endif
580}
581
