LXR uboot/board/freescale/t104xrdb/t104xrdb.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2013 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <command.h>
   8#include <env.h>
   9#include <fdt_support.h>
  10#include <hwconfig.h>
  11#include <image.h>
  12#include <init.h>
  13#include <log.h>
  14#include <netdev.h>
  15#include <asm/global_data.h>
  16#include <linux/compiler.h>
  17#include <asm/mmu.h>
  18#include <asm/processor.h>
  19#include <asm/cache.h>
  20#include <asm/immap_85xx.h>
  21#include <asm/fsl_fdt.h>
  22#include <asm/fsl_law.h>
  23#include <asm/fsl_serdes.h>
  24#include <asm/fsl_liodn.h>
  25#include <fm_eth.h>
  26#include "../common/sleep.h"
  27#include "t104xrdb.h"
  28#include "cpld.h"
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32int checkboard(void)
  33{
  34        struct cpu_type *cpu = gd->arch.cpu;
  35        u8 sw;
  36
  37#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
  38        printf("Board: %sD4RDB\n", cpu->name);
  39#else
  40        printf("Board: %sRDB\n", cpu->name);
  41#endif
  42        printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  43               CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  44
  45        sw = CPLD_READ(flash_ctl_status);
  46        sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  47
  48        printf("vBank: %d\n", sw);
  49
  50        return 0;
  51}
  52
  53int board_early_init_f(void)
  54{
  55#if defined(CONFIG_DEEP_SLEEP)
  56        if (is_warm_boot())
  57                fsl_dp_disable_console();
  58#endif
  59
  60        return 0;
  61}
  62
  63int board_early_init_r(void)
  64{
  65#ifdef CONFIG_SYS_FLASH_BASE
  66        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  67        int flash_esel = find_tlb_idx((void *)flashbase, 1);
  68
  69        /*
  70         * Remap Boot flash region to caching-inhibited
  71         * so that flash can be erased properly.
  72         */
  73
  74        /* Flush d-cache and invalidate i-cache of any FLASH data */
  75        flush_dcache();
  76        invalidate_icache();
  77
  78        if (flash_esel == -1) {
  79                /* very unlikely unless something is messed up */
  80                puts("Error: Could not find TLB for FLASH BASE\n");
  81                flash_esel = 2; /* give our best effort to continue */
  82        } else {
  83                /* invalidate existing TLB entry for flash */
  84                disable_tlb(flash_esel);
  85        }
  86
  87        set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  88                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  89                0, flash_esel, BOOKE_PAGESZ_256M, 1);
  90#endif
  91        return 0;
  92}
  93
  94int misc_init_r(void)
  95{
  96        ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  97        u32 srds_s1;
  98
  99        srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
 100
 101        printf("SERDES Reference : 0x%X\n", srds_s1);
 102
 103        /* select SGMII*/
 104        if (srds_s1 == 0x86)
 105                CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 106                                         MISC_CTL_SG_SEL);
 107
 108        /* select SGMII and Aurora*/
 109        if (srds_s1 == 0x8E)
 110                CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 111                                         MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
 112
 113#if defined(CONFIG_TARGET_T1040D4RDB)
 114        if (hwconfig("qe-tdm")) {
 115                CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
 116                           MISC_MUX_QE_TDM);
 117                printf("QECSR : 0x%02x, mux to qe-tdm\n",
 118                       CPLD_READ(sfp_ctl_status));
 119        }
 120        /* Mask all CPLD interrupt sources, except QSGMII interrupts */
 121        if (CPLD_READ(sw_ver) < 0x03) {
 122                debug("CPLD SW version 0x%02x doesn't support int_mask\n",
 123                      CPLD_READ(sw_ver));
 124        } else {
 125                CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
 126                           ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
 127        }
 128#endif
 129
 130        return 0;
 131}
 132
 133int ft_board_setup(void *blob, struct bd_info *bd)
 134{
 135        phys_addr_t base;
 136        phys_size_t size;
 137
 138        ft_cpu_setup(blob, bd);
 139
 140        base = env_get_bootm_low();
 141        size = env_get_bootm_size();
 142
 143        fdt_fixup_memory(blob, (u64)base, (u64)size);
 144
 145#ifdef CONFIG_PCI
 146        pci_of_setup(blob, bd);
 147#endif
 148
 149        fdt_fixup_liodn(blob);
 150
 151#ifdef CONFIG_HAS_FSL_DR_USB
 152        fsl_fdt_fixup_dr_usb(blob, bd);
 153#endif
 154
 155#ifdef CONFIG_SYS_DPAA_FMAN
 156#ifndef CONFIG_DM_ETH
 157        fdt_fixup_fman_ethernet(blob);
 158#endif
 159#endif
 160
 161        if (hwconfig("qe-tdm"))
 162                fdt_del_diu(blob);
 163        return 0;
 164}
 165