LXR uboot/board/freescale/t208xrdb/spl.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/* Copyright 2013 Freescale Semiconductor, Inc.
   3 */
   4
   5#include <common.h>
   6#include <clock_legacy.h>
   7#include <console.h>
   8#include <env_internal.h>
   9#include <init.h>
  10#include <malloc.h>
  11#include <ns16550.h>
  12#include <nand.h>
  13#include <i2c.h>
  14#include <mmc.h>
  15#include <fsl_esdhc.h>
  16#include <spi_flash.h>
  17#include <asm/global_data.h>
  18#include "../common/spl.h"
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22phys_size_t get_effective_memsize(void)
  23{
  24        return CONFIG_SYS_L3_SIZE;
  25}
  26
  27unsigned long get_board_sys_clk(void)
  28{
  29        return CONFIG_SYS_CLK_FREQ;
  30}
  31
  32void board_init_f(ulong bootflag)
  33{
  34        u32 plat_ratio, sys_clk, ccb_clk;
  35        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  36
  37        /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  38        memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  39
  40        /* Update GD pointer */
  41        gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  42
  43        console_init_f();
  44
  45        /* initialize selected port with appropriate baud rate */
  46        sys_clk = get_board_sys_clk();
  47        plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  48        ccb_clk = sys_clk * plat_ratio / 2;
  49
  50        ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
  51                     ccb_clk / 16 / CONFIG_BAUDRATE);
  52
  53#if defined(CONFIG_SPL_MMC_BOOT)
  54        puts("\nSD boot...\n");
  55#elif defined(CONFIG_SPL_SPI_BOOT)
  56        puts("\nSPI boot...\n");
  57#elif defined(CONFIG_SPL_NAND_BOOT)
  58        puts("\nNAND boot...\n");
  59#endif
  60
  61        relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  62}
  63
  64void board_init_r(gd_t *gd, ulong dest_addr)
  65{
  66        struct bd_info *bd;
  67
  68        bd = (struct bd_info *)(gd + sizeof(gd_t));
  69        memset(bd, 0, sizeof(struct bd_info));
  70        gd->bd = bd;
  71
  72        arch_cpu_init();
  73        get_clocks();
  74        mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  75                        CONFIG_SPL_RELOC_MALLOC_SIZE);
  76        gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  77
  78#ifdef CONFIG_SPL_NAND_BOOT
  79        nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  80                            (uchar *)SPL_ENV_ADDR);
  81#endif
  82#ifdef CONFIG_SPL_MMC_BOOT
  83        mmc_initialize(bd);
  84        mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  85                           (uchar *)SPL_ENV_ADDR);
  86#endif
  87#ifdef CONFIG_SPL_SPI_BOOT
  88        fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  89                               (uchar *)SPL_ENV_ADDR);
  90#endif
  91
  92        gd->env_addr  = (ulong)(SPL_ENV_ADDR);
  93        gd->env_valid = ENV_VALID;
  94
  95        i2c_init_all();
  96
  97        dram_init();
  98
  99#ifdef CONFIG_SPL_MMC_BOOT
 100        mmc_boot();
 101#elif defined(CONFIG_SPL_SPI_BOOT)
 102        fsl_spi_boot();
 103#elif defined(CONFIG_SPL_NAND_BOOT)
 104        nand_boot();
 105#endif
 106}
 107