LXR uboot/board/freescale/t208xrdb/t208xrdb.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2009-2013 Freescale Semiconductor, Inc.
   4 * Copyright 2021 NXP
   5 */
   6
   7#include <common.h>
   8#include <command.h>
   9#include <env.h>
  10#include <fdt_support.h>
  11#include <i2c.h>
  12#include <image.h>
  13#include <init.h>
  14#include <netdev.h>
  15#include <asm/global_data.h>
  16#include <linux/compiler.h>
  17#include <asm/mmu.h>
  18#include <asm/processor.h>
  19#include <asm/immap_85xx.h>
  20#include <asm/fsl_law.h>
  21#include <asm/fsl_serdes.h>
  22#include <asm/fsl_liodn.h>
  23#include <fm_eth.h>
  24#include "t208xrdb.h"
  25#include "cpld.h"
  26#include "../common/vid.h"
  27
  28DECLARE_GLOBAL_DATA_PTR;
  29
  30u8 get_hw_revision(void)
  31{
  32        u8 ver = CPLD_READ(hw_ver);
  33
  34        switch (ver) {
  35        default:
  36        case 0x1:
  37                return 'C';
  38        case 0x0:
  39                return 'D';
  40        case 0x2:
  41                return 'E';
  42        }
  43}
  44
  45int checkboard(void)
  46{
  47        struct cpu_type *cpu = gd->arch.cpu;
  48        static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  49
  50        printf("Board: %sRDB, ", cpu->name);
  51        printf("Board rev: %c CPLD ver: 0x%02x, boot from ",
  52               get_hw_revision(), CPLD_READ(sw_ver));
  53
  54#ifdef CONFIG_SDCARD
  55        puts("SD/MMC\n");
  56#elif CONFIG_SPIFLASH
  57        puts("SPI\n");
  58#else
  59        u8 reg;
  60
  61        reg = CPLD_READ(flash_csr);
  62
  63        if (reg & CPLD_BOOT_SEL) {
  64                puts("NAND\n");
  65        } else {
  66                reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  67                printf("NOR vBank%d\n", reg);
  68        }
  69#endif
  70
  71        puts("SERDES Reference Clocks:\n");
  72        printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  73        printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
  74
  75        return 0;
  76}
  77
  78int board_early_init_r(void)
  79{
  80        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  81        int flash_esel = find_tlb_idx((void *)flashbase, 1);
  82        /*
  83         * Remap Boot flash + PROMJET region to caching-inhibited
  84         * so that flash can be erased properly.
  85         */
  86
  87        /* Flush d-cache and invalidate i-cache of any FLASH data */
  88        flush_dcache();
  89        invalidate_icache();
  90        if (flash_esel == -1) {
  91                /* very unlikely unless something is messed up */
  92                puts("Error: Could not find TLB for FLASH BASE\n");
  93                flash_esel = 2; /* give our best effort to continue */
  94        } else {
  95                /* invalidate existing TLB entry for flash + promjet */
  96                disable_tlb(flash_esel);
  97        }
  98
  99        set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 100                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 101                0, flash_esel, BOOKE_PAGESZ_256M, 1);
 102
 103        /*
 104         * Adjust core voltage according to voltage ID
 105         * This function changes I2C mux to channel 2.
 106         */
 107        if (adjust_vdd(0))
 108                printf("Warning: Adjusting core voltage failed.\n");
 109        return 0;
 110}
 111
 112unsigned long get_board_sys_clk(void)
 113{
 114        return CONFIG_SYS_CLK_FREQ;
 115}
 116
 117int misc_init_r(void)
 118{
 119        u8 reg;
 120
 121        /* Reset CS4315 PHY */
 122        reg = CPLD_READ(reset_ctl);
 123        reg |= CPLD_RSTCON_EDC_RST;
 124        CPLD_WRITE(reset_ctl, reg);
 125
 126        /* Enable POR for boards revisions D and up */
 127        if (get_hw_revision() >= 'D') {
 128                reg = CPLD_READ(misc_csr);
 129                reg |= CPLD_MISC_POR_EN;
 130                CPLD_WRITE(misc_csr, reg);
 131        }
 132
 133        return 0;
 134}
 135
 136int ft_board_setup(void *blob, struct bd_info *bd)
 137{
 138        phys_addr_t base;
 139        phys_size_t size;
 140
 141        ft_cpu_setup(blob, bd);
 142
 143        base = env_get_bootm_low();
 144        size = env_get_bootm_size();
 145
 146        fdt_fixup_memory(blob, (u64)base, (u64)size);
 147
 148#ifdef CONFIG_PCI
 149        pci_of_setup(blob, bd);
 150#endif
 151
 152        fdt_fixup_liodn(blob);
 153        fsl_fdt_fixup_dr_usb(blob, bd);
 154
 155#ifdef CONFIG_SYS_DPAA_FMAN
 156        fdt_fixup_board_fman_ethernet(blob);
 157        fdt_fixup_board_enet(blob);
 158        fdt_fixup_board_phy(blob);
 159#endif
 160
 161        return 0;
 162}
 163
 164ulong *cs4340_get_fw_addr(void)
 165{
 166        ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
 167
 168#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
 169        u8 reg;
 170
 171        reg = CPLD_READ(flash_csr);
 172        if (!(reg & CPLD_BOOT_SEL)) {
 173                reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
 174                if (reg == 0)
 175                        cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
 176                else if (reg == 4)
 177                        cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
 178        }
 179#endif
 180
 181        return (ulong *)cortina_fw_addr;
 182}
 183