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6#include <common.h>
7#include <command.h>
8#include <env.h>
9#include <fdt_support.h>
10#include <i2c.h>
11#include <image.h>
12#include <init.h>
13#include <netdev.h>
14#include <asm/global_data.h>
15#include <linux/compiler.h>
16#include <asm/mmu.h>
17#include <asm/processor.h>
18#include <asm/cache.h>
19#include <asm/immap_85xx.h>
20#include <asm/fsl_law.h>
21#include <asm/fsl_serdes.h>
22#include <asm/fsl_liodn.h>
23#include <fm_eth.h>
24
25#include "t4rdb.h"
26#include "cpld.h"
27#include "../common/vid.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
31int checkboard(void)
32{
33 struct cpu_type *cpu = gd->arch.cpu;
34 u8 sw;
35
36 printf("Board: %sRDB, ", cpu->name);
37 printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
38 CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
39
40 sw = CPLD_READ(vbank);
41 sw = sw & CPLD_BANK_SEL_MASK;
42
43 if (sw <= 7)
44 printf("vBank: %d\n", sw);
45 else
46 printf("Unsupported Bank=%x\n", sw);
47
48 puts("SERDES Reference Clocks:\n");
49 printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
50 " SERDES3=100MHz SERDES4=100MHz\n");
51
52 return 0;
53}
54
55int board_early_init_r(void)
56{
57 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
58 int flash_esel = find_tlb_idx((void *)flashbase, 1);
59
60
61
62
63
64
65
66 flush_dcache();
67 invalidate_icache();
68
69 if (flash_esel == -1) {
70
71 puts("Error: Could not find TLB for FLASH BASE\n");
72 flash_esel = 2;
73 } else {
74
75 disable_tlb(flash_esel);
76 }
77
78 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
79 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
80 0, flash_esel, BOOKE_PAGESZ_256M, 1);
81
82
83
84
85
86 if (adjust_vdd(0))
87 printf("Warning: Adjusting core voltage failed.\n");
88
89 return 0;
90}
91
92int misc_init_r(void)
93{
94 return 0;
95}
96
97int ft_board_setup(void *blob, struct bd_info *bd)
98{
99 phys_addr_t base;
100 phys_size_t size;
101
102 ft_cpu_setup(blob, bd);
103
104 base = env_get_bootm_low();
105 size = env_get_bootm_size();
106
107 fdt_fixup_memory(blob, (u64)base, (u64)size);
108
109#ifdef CONFIG_PCI
110 pci_of_setup(blob, bd);
111#endif
112
113 fdt_fixup_liodn(blob);
114 fsl_fdt_fixup_dr_usb(blob, bd);
115
116#ifdef CONFIG_SYS_DPAA_FMAN
117#ifndef CONFIG_DM_ETH
118 fdt_fixup_fman_ethernet(blob);
119#endif
120 fdt_fixup_board_enet(blob);
121#endif
122
123 return 0;
124}
125
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135
136
137
138void board_detail(void)
139{
140 int rcwsrc;
141
142
143 rcwsrc = 0x0;
144 puts("RCW source = ");
145 switch (rcwsrc & 0x1) {
146 case 0x1:
147 puts("SDHC/eMMC\n");
148 break;
149 default:
150 puts("I2C normal addressing\n");
151 break;
152 }
153}
154
155ulong *cs4340_get_fw_addr(void)
156{
157 ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
158
159#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
160 u8 sw;
161
162 sw = CPLD_READ(vbank);
163 sw = sw & CPLD_BANK_SEL_MASK;
164
165 if (sw == 0)
166 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
167 else if (sw == 4)
168 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
169#endif
170
171 return (ulong *)cortina_fw_addr;
172}
173