1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2008 4 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5 */ 6 7#ifndef __KEYMILE_COMMON_H 8#define __KEYMILE_COMMON_H 9 10#define WRG_RESET 0x80 11#define H_OPORTS_14 0x40 12#define WRG_LED 0x02 13#define WRL_BOOT 0x01 14 15#define OPRTL_XBUFENA 0x20 16 17#define H_OPORTS_SCC4_ENA 0x10 18#define H_OPORTS_SCC4_FD_ENA 0x04 19#define H_OPORTS_FCC1_PW_DWN 0x01 20 21#define PIGGY_PRESENT 0x80 22 23struct km_bec_fpga { 24 unsigned char id; 25 unsigned char rev; 26 unsigned char oprth; 27 unsigned char oprtl; 28 unsigned char res1[3]; 29 unsigned char bprth; 30 unsigned char bprtl; 31 unsigned char gprt3; 32 unsigned char gprt2; 33 unsigned char gprt1; 34 unsigned char gprt0; 35 unsigned char res2[2]; 36 unsigned char prst; 37 unsigned char res3[0xfff0]; 38 unsigned char pgy_id; 39 unsigned char pgy_rev; 40 unsigned char pgy_outputs; 41 unsigned char pgy_eth; 42}; 43 44#define BFTICU_DIPSWITCH_MASK 0x0f 45 46/* 47 * BFTICU FPGA iomap 48 * BFTICU is used on mgcoge and mgocge3ne 49 */ 50struct bfticu_iomap { 51 u8 xi_ena; /* General defect enable */ 52 u8 pack1[3]; 53 u8 en_csn; 54 u8 pack2; 55 u8 safe_mem; 56 u8 pack3; 57 u8 id; 58 u8 pack4; 59 u8 rev; 60 u8 build; 61 u8 p_frc; 62 u8 p_msk; 63 u8 pack5[2]; 64 u8 xg_int; 65 u8 pack6[15]; 66 u8 s_conf; 67 u8 pack7; 68 u8 dmx_conf12; 69 u8 pack8; 70 u8 s_clkslv; 71 u8 pack9[11]; 72 u8 d_conf; 73 u8 d_mask_ca; 74 u8 d_pll_del; 75 u8 pack10[16]; 76 u8 t_conf_ca; 77 u8 t_mask_ca; 78 u8 pack11[13]; 79 u8 m_def0; 80 u8 m_def1; 81 u8 m_def2; 82 u8 m_def3; 83 u8 m_def4; 84 u8 m_def5; 85 u8 m_def_trap0; 86 u8 m_def_trap1; 87 u8 m_def_trap2; 88 u8 m_def_trap3; 89 u8 m_def_trap4; 90 u8 m_def_trap5; 91 u8 m_mask_def0; 92 u8 m_mask_def1; 93 u8 m_mask_def2; 94 u8 m_mask_def3; 95 u8 m_mask_def4; 96 u8 m_mask_def5; 97 u8 m_def_mask0; 98 u8 m_def_mask1; 99 u8 m_def_mask2; 100 u8 m_def_mask3; 101 u8 m_def_mask4; 102 u8 m_def_mask5; 103 u8 m_def_pri; 104 u8 pack12[11]; 105 u8 hw_status; 106 u8 pack13; 107 u8 hw_control1; 108 u8 hw_control2; 109 u8 hw_control3; 110 u8 pack14[7]; 111 u8 led_on; /* Leds */ 112 u8 pack15; 113 u8 sfp_control; /* SFP modules */ 114 u8 pack16; 115 u8 alarm_control; /* Alarm output */ 116 u8 pack17; 117 u8 icps; /* ICN clock pulse shaping */ 118 u8 mswitch; /* Read mode switch */ 119 u8 pack18[6]; 120 u8 pb_dbug; 121}; 122 123int ethernet_present(void); 124int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset); 125int ivm_analyze_eeprom(unsigned char *buf, int len); 126 127int trigger_fpga_config(void); 128int wait_for_fpga_config(void); 129int fpga_reset(void); 130int toggle_eeprom_spi_bus(void); 131 132int get_testpin(void); 133 134int set_km_env(void); 135 136#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ 137#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) 138 139void set_sda(int state); 140void set_scl(int state); 141int get_sda(void); 142int get_scl(void); 143 144int i2c_soft_read_pin(void); 145int i2c_make_abort(void); 146#endif /* __KEYMILE_COMMON_H */ 147