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16#include <common.h>
17#include <env.h>
18#include <fdt_support.h>
19#include <init.h>
20#include <ioports.h>
21#include <log.h>
22#include <mpc83xx.h>
23#include <i2c.h>
24#include <miiphy.h>
25#include <asm/global_data.h>
26#include <asm/io.h>
27#include <asm/mmu.h>
28#include <asm/processor.h>
29#include <pci.h>
30#include <linux/delay.h>
31#include <linux/libfdt.h>
32#include <post.h>
33
34#include "../common/common.h"
35
36DECLARE_GLOBAL_DATA_PTR;
37
38static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
39
40static int piggy_present(void)
41{
42 struct km_bec_fpga __iomem *base =
43 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
44
45 return in_8(&base->bprth) & PIGGY_PRESENT;
46}
47
48int ethernet_present(void)
49{
50 return piggy_present();
51}
52
53int board_early_init_r(void)
54{
55 struct km_bec_fpga *base =
56 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
57
58#if defined(CONFIG_ARCH_MPC8360)
59 unsigned short svid;
60
61
62
63
64 svid = SVR_REV(mfspr(SVR));
65 switch (svid) {
66 case 0x0020:
67
68
69
70
71
72 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
73 break;
74 case 0x0021:
75
76
77
78
79 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
80 0x00000050, 0x000000a0);
81 break;
82 }
83#endif
84
85
86 setbits_8(&base->pgy_eth, 0x01);
87
88 setbits_8(&base->oprth, WRL_BOOT);
89
90 setbits_8(&base->oprtl, OPRTL_XBUFENA);
91
92 return 0;
93}
94
95int misc_init_r(void)
96{
97 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
98 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
99 return 0;
100}
101
102int last_stage_init(void)
103{
104#if defined(CONFIG_TARGET_KMCOGE5NE)
105 struct bfticu_iomap *base =
106 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
107 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
108
109 if (dip_switch != 0) {
110
111 puts("DIP: Enabled\n");
112 env_set("actual_bank", "0");
113 }
114#endif
115 set_km_env();
116 return 0;
117}
118
119static int fixed_sdram(void)
120{
121 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
122 u32 msize = 0;
123 u32 ddr_size;
124 u32 ddr_size_log2;
125
126 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
127 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
128 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
129 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
130 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
131 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
132 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
133 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
134 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
135 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
136 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
137 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
138 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
139 udelay(200);
140 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
141
142 msize = CONFIG_SYS_DDR_SIZE << 20;
143 disable_addr_trans();
144 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
145 enable_addr_trans();
146 msize /= (1024 * 1024);
147 if (CONFIG_SYS_DDR_SIZE != msize) {
148 for (ddr_size = msize << 20, ddr_size_log2 = 0;
149 (ddr_size > 1);
150 ddr_size = ddr_size >> 1, ddr_size_log2++)
151 if (ddr_size & 1)
152 return -1;
153 out_be32(&im->sysconf.ddrlaw[0].ar,
154 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
155 out_be32(&im->ddr.csbnds[0].csbnds,
156 (((msize / 16) - 1) & 0xff));
157 }
158
159 return msize;
160}
161
162int dram_init(void)
163{
164 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
165 u32 msize = 0;
166
167 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
168 return -ENXIO;
169
170 out_be32(&im->sysconf.ddrlaw[0].bar,
171 CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
172 msize = fixed_sdram();
173
174#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
175
176
177
178 ddr_enable_ecc(msize * 1024 * 1024);
179#endif
180
181
182 gd->ram_size = msize * 1024 * 1024;
183
184 return 0;
185}
186
187int checkboard(void)
188{
189 puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
190
191 if (piggy_present())
192 puts(" with PIGGY.");
193 puts("\n");
194 return 0;
195}
196
197int ft_board_setup(void *blob, struct bd_info *bd)
198{
199 ft_cpu_setup(blob, bd);
200
201 return 0;
202}
203
204#if defined(CONFIG_HUSH_INIT_VAR)
205int hush_init_var(void)
206{
207 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
208 return 0;
209}
210#endif
211
212#if defined(CONFIG_POST)
213int post_hotkeys_pressed(void)
214{
215 int testpin = 0;
216 struct km_bec_fpga *base =
217 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
218 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
219 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
220 debug("post_hotkeys_pressed: %d\n", !testpin);
221 return testpin;
222}
223
224ulong post_word_load(void)
225{
226 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
227 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
228 return in_le32(addr);
229
230}
231void post_word_store(ulong value)
232{
233 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
234 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
235 out_le32(addr, value);
236}
237
238int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
239{
240 *vstart = CONFIG_SYS_MEMTEST_START;
241 *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
242 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
243
244 return 0;
245}
246#endif
247
