LXR uboot/board/keymile/km_arm/km

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2009
   4 * Marvell Semiconductor <www.marvell.com>
   5 * Prafulla Wadaskar <prafulla@marvell.com>
   6 *
   7 * (C) Copyright 2009
   8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   9 *
  10 * (C) Copyright 2010
  11 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  12 */
  13
  14#include <common.h>
  15#include <env.h>
  16#include <i2c.h>
  17#include <init.h>
  18#include <nand.h>
  19#include <net.h>
  20#include <netdev.h>
  21#include <miiphy.h>
  22#include <spi.h>
  23#include <asm/global_data.h>
  24#include <asm/io.h>
  25#include <asm/arch/cpu.h>
  26#include <asm/arch/soc.h>
  27#include <asm/arch/mpp.h>
  28
  29#include "../common/common.h"
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33/*
  34 * BOCO FPGA definitions
  35 */
  36#define BOCO            0x10
  37#define REG_CTRL_H              0x02
  38#define MASK_WRL_UNITRUN        0x01
  39#define MASK_RBX_PGY_PRESENT    0x40
  40#define REG_IRQ_CIRQ2           0x2d
  41#define MASK_RBI_DEFECT_16      0x01
  42
  43/*
  44 * PHY registers definitions
  45 */
  46#define PHY_MARVELL_OUI                                 0x5043
  47#define PHY_MARVELL_88E1118_MODEL                       0x0022
  48#define PHY_MARVELL_88E1118R_MODEL                      0x0024
  49
  50#define PHY_MARVELL_PAGE_REG                            0x0016
  51#define PHY_MARVELL_DEFAULT_PAGE                        0x0000
  52
  53#define PHY_MARVELL_88E1118R_LED_CTRL_PAGE              0x0003
  54#define PHY_MARVELL_88E1118R_LED_CTRL_REG               0x0010
  55
  56#define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED          0x1000
  57#define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB       (0x7 << 0)
  58#define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT          (0x3 << 4)
  59#define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK         (0x0 << 8)
  60
  61/* I/O pin to erase flash RGPP09 = MPP43 */
  62#define KM_FLASH_ERASE_ENABLE   43
  63
  64/* Multi-Purpose Pins Functionality configuration */
  65static const u32 kwmpp_config[] = {
  66        MPP0_NF_IO2,
  67        MPP1_NF_IO3,
  68        MPP2_NF_IO4,
  69        MPP3_NF_IO5,
  70        MPP4_NF_IO6,
  71        MPP5_NF_IO7,
  72        MPP6_SYSRST_OUTn,
  73        MPP7_PEX_RST_OUTn,
  74#if defined(CONFIG_SYS_I2C_SOFT)
  75        MPP8_GPIO,              /* SDA */
  76        MPP9_GPIO,              /* SCL */
  77#endif
  78        MPP10_UART0_TXD,
  79        MPP11_UART0_RXD,
  80        MPP12_GPO,              /* Reserved */
  81        MPP13_UART1_TXD,
  82        MPP14_UART1_RXD,
  83        MPP15_GPIO,             /* Not used */
  84        MPP16_GPIO,             /* Not used */
  85        MPP17_GPIO,             /* Reserved */
  86        MPP18_NF_IO0,
  87        MPP19_NF_IO1,
  88        MPP20_GPIO,
  89        MPP21_GPIO,
  90        MPP22_GPIO,
  91        MPP23_GPIO,
  92        MPP24_GPIO,
  93        MPP25_GPIO,
  94        MPP26_GPIO,
  95        MPP27_GPIO,
  96        MPP28_GPIO,
  97        MPP29_GPIO,
  98        MPP30_GPIO,
  99        MPP31_GPIO,
 100        MPP32_GPIO,
 101        MPP33_GPIO,
 102        MPP34_GPIO,             /* CDL1 (input) */
 103        MPP35_GPIO,             /* CDL2 (input) */
 104        MPP36_GPIO,             /* MAIN_IRQ (input) */
 105        MPP37_GPIO,             /* BOARD_LED */
 106        MPP38_GPIO,             /* Piggy3 LED[1] */
 107        MPP39_GPIO,             /* Piggy3 LED[2] */
 108        MPP40_GPIO,             /* Piggy3 LED[3] */
 109        MPP41_GPIO,             /* Piggy3 LED[4] */
 110        MPP42_GPIO,             /* Piggy3 LED[5] */
 111        MPP43_GPIO,             /* Piggy3 LED[6] */
 112        MPP44_GPIO,             /* Piggy3 LED[7], BIST_EN_L */
 113        MPP45_GPIO,             /* Piggy3 LED[8] */
 114        MPP46_GPIO,             /* Reserved */
 115        MPP47_GPIO,             /* Reserved */
 116        MPP48_GPIO,             /* Reserved */
 117        MPP49_GPIO,             /* SW_INTOUTn */
 118        0
 119};
 120
 121static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 122
 123#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
 124/*
 125 * All boards with PIGGY4 connected via a simple switch have ethernet always
 126 * present.
 127 */
 128int ethernet_present(void)
 129{
 130        return 1;
 131}
 132#else
 133int ethernet_present(void)
 134{
 135        uchar   buf;
 136        int     ret = 0;
 137
 138        if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 139                printf("%s: Error reading Boco\n", __func__);
 140                return -1;
 141        }
 142        if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
 143                ret = 1;
 144
 145        return ret;
 146}
 147#endif
 148
 149static int initialize_unit_leds(void)
 150{
 151        /*
 152         * Init the unit LEDs per default they all are
 153         * ok apart from bootstat
 154         */
 155        uchar buf;
 156
 157        if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 158                printf("%s: Error reading Boco\n", __func__);
 159                return -1;
 160        }
 161        buf |= MASK_WRL_UNITRUN;
 162        if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 163                printf("%s: Error writing Boco\n", __func__);
 164                return -1;
 165        }
 166        return 0;
 167}
 168
 169static void set_bootcount_addr(void)
 170{
 171        uchar buf[32];
 172        unsigned int bootcountaddr;
 173
 174        bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
 175        sprintf((char *)buf, "0x%x", bootcountaddr);
 176        env_set("bootcountaddr", (char *)buf);
 177}
 178
 179int misc_init_r(void)
 180{
 181        ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
 182                        CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
 183
 184        initialize_unit_leds();
 185        set_km_env();
 186        set_bootcount_addr();
 187        return 0;
 188}
 189
 190int board_early_init_f(void)
 191{
 192#if defined(CONFIG_SYS_I2C_SOFT)
 193        u32 tmp;
 194
 195        /* set the 2 bitbang i2c pins as output gpios */
 196        tmp = readl(MVEBU_GPIO0_BASE + 4);
 197        writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS), MVEBU_GPIO0_BASE + 4);
 198#endif
 199        /* adjust SDRAM size for bank 0 */
 200        mvebu_sdram_size_adjust(0);
 201        kirkwood_mpp_conf(kwmpp_config, NULL);
 202        return 0;
 203}
 204
 205int board_init(void)
 206{
 207        /* address of boot parameters */
 208        gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 209
 210        /*
 211         * The KM_FLASH_GPIO_PIN switches between using a
 212         * NAND or a SPI FLASH. Set this pin on start
 213         * to NAND mode.
 214         */
 215        kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
 216        kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 217
 218#if defined(CONFIG_SYS_I2C_SOFT)
 219        /*
 220         * Reinit the GPIO for I2C Bitbang driver so that the now
 221         * available gpio framework is consistent. The calls to
 222         * direction output in are not necessary, they are already done in
 223         * board_early_init_f
 224         */
 225        kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
 226        kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
 227#endif
 228
 229#if defined(CONFIG_SYS_EEPROM_WREN)
 230        kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
 231        kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
 232#endif
 233
 234#if defined(CONFIG_KM_FPGA_CONFIG)
 235        trigger_fpga_config();
 236#endif
 237
 238        return 0;
 239}
 240
 241int board_late_init(void)
 242{
 243#if defined(CONFIG_KM_COGE5UN)
 244        u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
 245
 246        /* if pin 1 do full erase */
 247        if (dip_switch != 0) {
 248                /* start bootloader */
 249                puts("DIP:   Enabled\n");
 250                env_set("actual_bank", "0");
 251        }
 252#endif
 253
 254#if defined(CONFIG_KM_FPGA_CONFIG)
 255        wait_for_fpga_config();
 256        fpga_reset();
 257        toggle_eeprom_spi_bus();
 258#endif
 259        return 0;
 260}
 261
 262static const u32 spi_mpp_config[] = {
 263        MPP1_SPI_MOSI,
 264        MPP2_SPI_SCK,
 265        MPP3_SPI_MISO,
 266        0
 267};
 268
 269static u32 spi_mpp_backup[4];
 270
 271int mvebu_board_spi_claim_bus(struct udevice *dev)
 272{
 273        spi_mpp_backup[3] = 0;
 274
 275        /* set new spi mpp config and save current one */
 276        kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
 277
 278        kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
 279
 280        return 0;
 281}
 282
 283int mvebu_board_spi_release_bus(struct udevice *dev)
 284{
 285        /* restore saved mpp config */
 286        kirkwood_mpp_conf(spi_mpp_backup, NULL);
 287
 288        kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
 289
 290        return 0;
 291}
 292
 293#if (defined(CONFIG_KM_PIGGY4_88E6061))
 294
 295#define PHY_LED_SEL_REG         0x18
 296#define PHY_LED0_LINK           (0x5)
 297#define PHY_LED1_ACT            (0x8 << 4)
 298#define PHY_LED2_INT            (0xe << 8)
 299#define PHY_SPEC_CTRL_REG       0x1c
 300#define PHY_RGMII_CLK_STABLE    (0x1 << 10)
 301#define PHY_CLSA                (0x1 << 1)
 302
 303/* Configure and enable MV88E3018 PHY */
 304void reset_phy(void)
 305{
 306        char *name = "egiga0";
 307        unsigned short reg;
 308
 309        if (miiphy_set_current_dev(name))
 310                return;
 311
 312        /* RGMII clk transition on data stable */
 313        if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
 314                printf("Error reading PHY spec ctrl reg\n");
 315        if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
 316                         reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
 317                printf("Error writing PHY spec ctrl reg\n");
 318
 319        /* leds setup */
 320        if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
 321                         PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
 322                printf("Error writing PHY LED reg\n");
 323
 324        /* reset the phy */
 325        miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 326}
 327#elif defined(CONFIG_KM_PIGGY4_88E6352)
 328
 329#include <mv88e6352.h>
 330
 331#if defined(CONFIG_KM_NUSA)
 332struct mv88e_sw_reg extsw_conf[] = {
 333        /*
 334         * port 0, PIGGY4, autoneg
 335         * first the fix for the 1000Mbits Autoneg, this is from
 336         * a Marvell errata, the regs are undocumented
 337         */
 338        { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
 339        { PHY(0), PHY_STATUS, AN1000FIX },
 340        { PHY(0), PHY_PAGE, 0 },
 341        /* now the real port and phy configuration */
 342        { PORT(0), PORT_PHY, NO_SPEED_FOR },
 343        { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 344        { PHY(0), PHY_1000_CTRL, NO_ADV },
 345        { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
 346        { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
 347                FULL_DUPLEX },
 348        /* port 1, unused */
 349        { PORT(1), PORT_CTRL, PORT_DIS },
 350        { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
 351        { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 352        /* port 2, unused */
 353        { PORT(2), PORT_CTRL, PORT_DIS },
 354        { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
 355        { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 356        /* port 3, unused */
 357        { PORT(3), PORT_CTRL, PORT_DIS },
 358        { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
 359        { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 360        /* port 4, ICNEV, SerDes, SGMII */
 361        { PORT(4), PORT_STATUS, NO_PHY_DETECT },
 362        { PORT(4), PORT_PHY, SPEED_1000_FOR },
 363        { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 364        { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
 365        { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 366        /* port 5, CPU_RGMII */
 367        { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
 368                FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
 369                FULL_DPX_FOR | SPEED_1000_FOR },
 370        { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 371        /* port 6, unused, this port has no phy */
 372        { PORT(6), PORT_CTRL, PORT_DIS },
 373};
 374#else
 375struct mv88e_sw_reg extsw_conf[] = {};
 376#endif
 377
 378void reset_phy(void)
 379{
 380#if defined(CONFIG_KM_MVEXTSW_ADDR)
 381        char *name = "egiga0";
 382
 383        if (miiphy_set_current_dev(name))
 384                return;
 385
 386        mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
 387                ARRAY_SIZE(extsw_conf));
 388        mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
 389#endif
 390}
 391
 392#else
 393/* Configure and enable MV88E1118 PHY on the piggy*/
 394void reset_phy(void)
 395{
 396        unsigned int oui;
 397        unsigned char model, rev;
 398
 399        char *name = "egiga0";
 400
 401        if (miiphy_set_current_dev(name))
 402                return;
 403
 404        /* reset the phy */
 405        miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 406
 407        /* get PHY model */
 408        if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
 409                return;
 410
 411        /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
 412        if (oui == PHY_MARVELL_OUI &&
 413            model == PHY_MARVELL_88E1118R_MODEL) {
 414                /* set page register to 3 */
 415                if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
 416                                 PHY_MARVELL_PAGE_REG,
 417                                 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
 418                        printf("Error writing PHY page reg\n");
 419
 420                /*
 421                 * leds setup as printed on PCB:
 422                 * LED2 (Link): 0x0 (On Link, Off No Link)
 423                 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
 424                 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
 425                 */
 426                if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
 427                                 PHY_MARVELL_88E1118R_LED_CTRL_REG,
 428                                 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
 429                                 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
 430                                 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
 431                                 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
 432                        printf("Error writing PHY LED reg\n");
 433
 434                /* set page register back to 0 */
 435                if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
 436                                 PHY_MARVELL_PAGE_REG,
 437                                 PHY_MARVELL_DEFAULT_PAGE))
 438                        printf("Error writing PHY page reg\n");
 439        }
 440}
 441#endif
 442
 443#if defined(CONFIG_HUSH_INIT_VAR)
 444int hush_init_var(void)
 445{
 446        ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 447        return 0;
 448}
 449#endif
 450
 451#if defined(CONFIG_SYS_I2C_SOFT)
 452void set_sda(int state)
 453{
 454        I2C_ACTIVE;
 455        I2C_SDA(state);
 456}
 457
 458void set_scl(int state)
 459{
 460        I2C_SCL(state);
 461}
 462
 463int get_sda(void)
 464{
 465        I2C_TRISTATE;
 466        return I2C_READ;
 467}
 468
 469int get_scl(void)
 470{
 471        return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
 472}
 473#endif
 474
 475#if defined(CONFIG_POST)
 476
 477#define KM_POST_EN_L    44
 478#define POST_WORD_OFF   8
 479
 480int post_hotkeys_pressed(void)
 481{
 482        if (IS_ENABLED(CONFIG_KM_COGE5UN))
 483                return kw_gpio_get_value(KM_POST_EN_L);
 484        else
 485                return !kw_gpio_get_value(KM_POST_EN_L);
 486}
 487
 488ulong post_word_load(void)
 489{
 490        void *addr = (void *)(gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
 491
 492        return in_le32(addr);
 493
 494}
 495void post_word_store(ulong value)
 496{
 497        void *addr = (void *)(gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
 498
 499        out_le32(addr, value);
 500}
 501
 502int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 503{
 504        *vstart = CONFIG_SYS_SDRAM_BASE;
 505
 506        /* we go up to relocation plus a 1 MB margin */
 507        *size = CONFIG_SYS_TEXT_BASE - (1 << 20);
 508
 509        return 0;
 510}
 511#endif
 512
 513#if defined(CONFIG_SYS_EEPROM_WREN)
 514int eeprom_write_enable(unsigned int dev_addr, int state)
 515{
 516        kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
 517
 518        return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
 519}
 520#endif
 521