LXR uboot/board/phytec/pcm058/pcm058.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
   4 */
   5
   6/*
   7 * Please note: there are two version of the board
   8 * one with NAND and the other with eMMC.
   9 * Both NAND and eMMC cannot be set because they share the
  10 * same pins (SD4)
  11 */
  12#include <common.h>
  13#include <init.h>
  14#include <net.h>
  15#include <asm/arch/crm_regs.h>
  16#include <asm/arch/mx6-ddr.h>
  17#include <asm/global_data.h>
  18#include <asm/mach-imx/boot_mode.h>
  19#include <asm/arch/sys_proto.h>
  20#include <dm.h>
  21
  22DECLARE_GLOBAL_DATA_PTR;
  23
  24#define IMX6Q_DRIVE_STRENGTH    0x30
  25
  26int dram_init(void)
  27{
  28        gd->ram_size = imx_ddr_size();
  29        return 0;
  30}
  31
  32int board_mmc_get_env_dev(int devno)
  33{
  34        return devno - 1;
  35}
  36
  37#ifdef CONFIG_CMD_NAND
  38static void setup_gpmi_nand(void)
  39{
  40        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  41
  42        /* gate ENFC_CLK_ROOT clock first,before clk source switch */
  43        clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  44
  45        /* config gpmi and bch clock to 100 MHz */
  46        clrsetbits_le32(&mxc_ccm->cs2cdr,
  47                        MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  48                        MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  49                        MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  50                        MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  51                        MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  52                        MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  53
  54        /* enable ENFC_CLK_ROOT clock */
  55        setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  56
  57        /* enable gpmi and bch clock gating */
  58        setbits_le32(&mxc_ccm->CCGR4,
  59                     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  60                     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  61                     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  62                     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  63                     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  64
  65        /* enable apbh clock gating */
  66        setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  67}
  68#endif
  69
  70int board_init(void)
  71{
  72        /* address of boot parameters */
  73        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  74
  75#ifdef CONFIG_CMD_NAND
  76        setup_gpmi_nand();
  77#endif
  78        return 0;
  79}
  80
  81#ifdef CONFIG_CMD_BMODE
  82/*
  83 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
  84 * see Table 8-11 and Table 5-9
  85 *  BOOT_CFG1[7] = 1 (boot from NAND)
  86 *  BOOT_CFG1[5] = 0 - raw NAND
  87 *  BOOT_CFG1[4] = 0 - default pad settings
  88 *  BOOT_CFG1[3:2] = 00 - devices = 1
  89 *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
  90 *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
  91 *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
  92 *  BOOT_CFG2[0] = 0 - Reset time 12ms
  93 */
  94static const struct boot_mode board_boot_modes[] = {
  95        /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
  96        {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
  97        {"mmc0",  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  98        {NULL, 0},
  99};
 100#endif
 101
 102int board_late_init(void)
 103{
 104#ifdef CONFIG_CMD_BMODE
 105        add_board_boot_modes(board_boot_modes);
 106#endif
 107
 108        return 0;
 109}
 110
 111#ifdef CONFIG_SPL_BUILD
 112#include <spl.h>
 113#include <linux/libfdt.h>
 114
 115static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 116        .dram_sdclk_0 = 0x00000030,
 117        .dram_sdclk_1 = 0x00000030,
 118        .dram_cas = 0x00000030,
 119        .dram_ras = 0x00000030,
 120        .dram_reset = 0x00000030,
 121        .dram_sdcke0 = 0x00000030,
 122        .dram_sdcke1 = 0x00000030,
 123        .dram_sdba2 = 0x00000000,
 124        .dram_sdodt0 = 0x00000030,
 125        .dram_sdodt1 = 0x00000030,
 126        .dram_sdqs0 = 0x00000030,
 127        .dram_sdqs1 = 0x00000030,
 128        .dram_sdqs2 = 0x00000030,
 129        .dram_sdqs3 = 0x00000030,
 130        .dram_sdqs4 = 0x00000030,
 131        .dram_sdqs5 = 0x00000030,
 132        .dram_sdqs6 = 0x00000030,
 133        .dram_sdqs7 = 0x00000030,
 134        .dram_dqm0 = 0x00000030,
 135        .dram_dqm1 = 0x00000030,
 136        .dram_dqm2 = 0x00000030,
 137        .dram_dqm3 = 0x00000030,
 138        .dram_dqm4 = 0x00000030,
 139        .dram_dqm5 = 0x00000030,
 140        .dram_dqm6 = 0x00000030,
 141        .dram_dqm7 = 0x00000030,
 142};
 143
 144static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 145        .grp_ddr_type =  0x000C0000,
 146        .grp_ddrmode_ctl =  0x00020000,
 147        .grp_ddrpke =  0x00000000,
 148        .grp_addds = IMX6Q_DRIVE_STRENGTH,
 149        .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
 150        .grp_ddrmode =  0x00020000,
 151        .grp_b0ds = IMX6Q_DRIVE_STRENGTH,
 152        .grp_b1ds = IMX6Q_DRIVE_STRENGTH,
 153        .grp_b2ds = IMX6Q_DRIVE_STRENGTH,
 154        .grp_b3ds = IMX6Q_DRIVE_STRENGTH,
 155        .grp_b4ds = IMX6Q_DRIVE_STRENGTH,
 156        .grp_b5ds = IMX6Q_DRIVE_STRENGTH,
 157        .grp_b6ds = IMX6Q_DRIVE_STRENGTH,
 158        .grp_b7ds = IMX6Q_DRIVE_STRENGTH,
 159};
 160
 161static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 162        .p0_mpwldectrl0 =  0x00140014,
 163        .p0_mpwldectrl1 =  0x000A0015,
 164        .p1_mpwldectrl0 =  0x000A001E,
 165        .p1_mpwldectrl1 =  0x000A0015,
 166        .p0_mpdgctrl0 =  0x43080314,
 167        .p0_mpdgctrl1 =  0x02680300,
 168        .p1_mpdgctrl0 =  0x430C0318,
 169        .p1_mpdgctrl1 =  0x03000254,
 170        .p0_mprddlctl =  0x3A323234,
 171        .p1_mprddlctl =  0x3E3C3242,
 172        .p0_mpwrdlctl =  0x2A2E3632,
 173        .p1_mpwrdlctl =  0x3C323E34,
 174};
 175
 176static struct mx6_ddr3_cfg mem_ddr = {
 177        .mem_speed = 1600,
 178        .density = 2,
 179        .width = 16,
 180        .banks = 8,
 181        .rowaddr = 14,
 182        .coladdr = 10,
 183        .pagesz = 2,
 184        .trcd = 1375,
 185        .trcmin = 4875,
 186        .trasmin = 3500,
 187        .SRT       = 1,
 188};
 189
 190static void ccgr_init(void)
 191{
 192        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 193
 194        writel(0x00C03F3F, &ccm->CCGR0);
 195        writel(0x0030FC03, &ccm->CCGR1);
 196        writel(0x0FFFC000, &ccm->CCGR2);
 197        writel(0x3FF00000, &ccm->CCGR3);
 198        writel(0x00FFF300, &ccm->CCGR4);
 199        writel(0x0F0000C3, &ccm->CCGR5);
 200        writel(0x000003FF, &ccm->CCGR6);
 201}
 202
 203static void spl_dram_init(void)
 204{
 205        struct mx6_ddr_sysinfo sysinfo = {
 206                /* width of data bus:0=16,1=32,2=64 */
 207                .dsize = 2,
 208                /* config for full 4GB range so that get_mem_size() works */
 209                .cs_density = 32, /* 32Gb per CS */
 210                /* single chip select */
 211                .ncs = 1,
 212                .cs1_mirror = 0,
 213                .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 214                .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 215                .walat = 1,     /* Write additional latency */
 216                .ralat = 5,     /* Read additional latency */
 217                .mif3_mode = 3, /* Command prediction working mode */
 218                .bi_on = 1,     /* Bank interleaving enabled */
 219                .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 220                .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 221                .ddr_type = DDR_TYPE_DDR3,
 222                .refsel = 1,    /* Refresh cycles at 32KHz */
 223                .refr = 7,      /* 8 refresh commands per refresh cycle */
 224        };
 225
 226        mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 227        mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 228}
 229
 230void board_boot_order(u32 *spl_boot_list)
 231{
 232        spl_boot_list[0] = spl_boot_device();
 233        printf("Boot device %x\n", spl_boot_list[0]);
 234        switch (spl_boot_list[0]) {
 235        case BOOT_DEVICE_SPI:
 236                spl_boot_list[1] = BOOT_DEVICE_UART;
 237                break;
 238        case BOOT_DEVICE_MMC1:
 239                spl_boot_list[1] = BOOT_DEVICE_SPI;
 240                spl_boot_list[2] = BOOT_DEVICE_UART;
 241                break;
 242        default:
 243                printf("Boot device %x\n", spl_boot_list[0]);
 244        }
 245}
 246
 247void board_init_f(ulong dummy)
 248{
 249        /* setup clock gating */
 250        ccgr_init();
 251
 252        /* setup AIPS and disable watchdog */
 253        arch_cpu_init();
 254
 255        /* setup AXI */
 256        gpr_init();
 257
 258        /* setup GP timer */
 259        timer_init();
 260
 261        /* DDR initialization */
 262        spl_dram_init();
 263
 264        /* Clear the BSS. */
 265        memset(__bss_start, 0, __bss_end - __bss_start);
 266
 267        /* Enable device tree and early DM support*/
 268        spl_early_init();
 269
 270        /* UART clocks enabled and gd valid - init serial console */
 271        preloader_console_init();
 272}
 273
 274/*
 275 *  Manually probe the SPI bus devices, as this does not happen when the
 276 *  SPI Flash is probed, which then fails to find the bus.
 277 */
 278void spl_board_init(void)
 279{
 280        struct udevice *udev;
 281        int ret = uclass_get_device_by_name(UCLASS_SPI, "spi@2008000", &udev);
 282
 283        if (ret) {
 284                printf("SPI bus probe failed, err = %d\n", ret);
 285        };
 286}
 287#endif
 288