LXR uboot/board/socionext/developerbox/developerbox.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * u-boot/board/socionext/developerbox/developerbox.c
   4 *
   5 * Copyright (C) 2016-2017 Socionext Inc.
   6 * Copyright (C) 2021 Linaro Ltd.
   7 */
   8#include <asm/types.h>
   9#include <asm/armv8/mmu.h>
  10#include <asm/global_data.h>
  11#include <asm/io.h>
  12#include <common.h>
  13#include <env_internal.h>
  14#include <fdt_support.h>
  15#include <log.h>
  16
  17static struct mm_region sc2a11_mem_map[] = {
  18        {
  19                .virt = 0x0UL,
  20                .phys = 0x0UL,
  21                .size = 0x80000000UL,
  22                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  23                         PTE_BLOCK_OUTER_SHARE
  24        }, {
  25                /* 1st DDR block */
  26                .virt = 0x80000000UL,
  27                .phys = 0x80000000UL,
  28                .size = PHYS_SDRAM_SIZE,
  29                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  30                         PTE_BLOCK_OUTER_SHARE
  31        }, {
  32                /* 2nd DDR place holder */
  33                0,
  34        }, {
  35                /* 3rd DDR place holder */
  36                0,
  37        }, {
  38                /* List terminator */
  39                0,
  40        }
  41};
  42
  43struct mm_region *mem_map = sc2a11_mem_map;
  44
  45#define DDR_REGION_INDEX(i)     (1 + (i))
  46#define MAX_DDR_REGIONS         3
  47
  48struct draminfo_entry {
  49        u64     base;
  50        u64     size;
  51};
  52
  53struct draminfo {
  54        u32     nr_regions;
  55        u32     reserved;
  56        struct draminfo_entry   entry[3];
  57};
  58
  59struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
  60
  61DECLARE_GLOBAL_DATA_PTR;
  62
  63#define LOAD_OFFSET 0x100
  64
  65/* SCBM System MMU is used for eMMC and NETSEC */
  66#define SCBM_SMMU_ADDR                          (0x52e00000UL)
  67#define SMMU_SCR0_OFFS                          (0x0)
  68#define SMMU_SCR0_SHCFG_INNER                   (0x2 << 22)
  69#define SMMU_SCR0_MTCFG                         (0x1 << 20)
  70#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB        (0xf << 16)
  71
  72static void synquacer_setup_scbm_smmu(void)
  73{
  74        writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
  75               SCBM_SMMU_ADDR + SMMU_SCR0_OFFS);
  76}
  77
  78/*
  79 * Miscellaneous platform dependent initialisations
  80 */
  81int board_init(void)
  82{
  83        gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
  84
  85        gd->env_addr = (ulong)&default_environment[0];
  86
  87        synquacer_setup_scbm_smmu();
  88
  89        return 0;
  90}
  91
  92int ft_board_setup(void *blob, struct bd_info *bd)
  93{
  94        /* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
  95        fdt_del_node_and_alias(blob, "spi_nor");
  96        fdt_del_node_and_alias(blob, "i2c0");
  97
  98        return 0;
  99}
 100
 101/*
 102 * DRAM configuration
 103 */
 104
 105int dram_init(void)
 106{
 107        struct draminfo_entry *ent = synquacer_draminfo->entry;
 108        struct mm_region *mr;
 109        int i, ri;
 110
 111        if (synquacer_draminfo->nr_regions < 1) {
 112                log_err("Failed to get correct DRAM information\n");
 113                return -1;
 114        }
 115
 116        /*
 117         * U-Boot RAM size must be under the first DRAM region so that it doesn't
 118         * access secure memory which is at the end of the first DRAM region.
 119         */
 120        gd->ram_size = ent[0].size;
 121
 122        /* Update memory region maps */
 123        for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
 124                if (i >= MAX_DDR_REGIONS)
 125                        break;
 126
 127                ri = DDR_REGION_INDEX(i);
 128                mem_map[ri].phys = ent[i].base;
 129                mem_map[ri].size = ent[i].size;
 130                if (i == 0)
 131                        continue;
 132
 133                mr = &mem_map[DDR_REGION_INDEX(0)];
 134                mem_map[ri].virt = mr->virt + mr->size;
 135                mem_map[ri].attrs = mr->attrs;
 136        }
 137
 138        return 0;
 139}
 140
 141int dram_init_banksize(void)
 142{
 143        struct draminfo_entry *ent = synquacer_draminfo->entry;
 144        int i;
 145
 146        for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
 147                if (i < synquacer_draminfo->nr_regions) {
 148                        debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
 149                        gd->bd->bi_dram[i].start = ent[i].base;
 150                        gd->bd->bi_dram[i].size = ent[i].size;
 151                }
 152        }
 153
 154        return 0;
 155}
 156
 157int print_cpuinfo(void)
 158{
 159        printf("CPU:   SC2A11:Cortex-A53 MPCore 24cores\n");
 160        return 0;
 161}
 162