LXR uboot/board/st/common/stpmic1.c

   1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2/*
   3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
   4 */
   5
   6#define LOG_CATEGORY LOGC_BOARD
   7
   8#include <common.h>
   9#include <dm.h>
  10#include <log.h>
  11#include <asm/io.h>
  12#include <asm/arch/ddr.h>
  13#include <linux/bitops.h>
  14#include <linux/delay.h>
  15#include <power/pmic.h>
  16#include <power/stpmic1.h>
  17
  18int board_ddr_power_init(enum ddr_type ddr_type)
  19{
  20        struct udevice *dev;
  21        bool buck3_at_1800000v = false;
  22        int ret;
  23        u32 buck2;
  24
  25        ret = uclass_get_device_by_driver(UCLASS_PMIC,
  26                                          DM_DRIVER_GET(pmic_stpmic1), &dev);
  27        if (ret)
  28                /* No PMIC on board */
  29                return 0;
  30
  31        switch (ddr_type) {
  32        case STM32MP_DDR3:
  33                /* VTT = Set LDO3 to sync mode */
  34                ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
  35                if (ret < 0)
  36                        return ret;
  37
  38                ret &= ~STPMIC1_LDO3_MODE;
  39                ret &= ~STPMIC1_LDO12356_VOUT_MASK;
  40                ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
  41
  42                ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
  43                                     ret);
  44                if (ret < 0)
  45                        return ret;
  46
  47                /* VDD_DDR = Set BUCK2 to 1.35V */
  48                ret = pmic_clrsetbits(dev,
  49                                      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
  50                                      STPMIC1_BUCK_VOUT_MASK,
  51                                      STPMIC1_BUCK2_1350000V);
  52                if (ret < 0)
  53                        return ret;
  54
  55                /* Enable VDD_DDR = BUCK2 */
  56                ret = pmic_clrsetbits(dev,
  57                                      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
  58                                      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
  59                if (ret < 0)
  60                        return ret;
  61
  62                mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
  63
  64                /* Enable VREF */
  65                ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
  66                                      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
  67                if (ret < 0)
  68                        return ret;
  69
  70                mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
  71
  72                /* Enable VTT = LDO3 */
  73                ret = pmic_clrsetbits(dev,
  74                                      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
  75                                      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
  76                if (ret < 0)
  77                        return ret;
  78
  79                mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
  80
  81                break;
  82
  83        case STM32MP_LPDDR2_16:
  84        case STM32MP_LPDDR2_32:
  85        case STM32MP_LPDDR3_16:
  86        case STM32MP_LPDDR3_32:
  87                /*
  88                 * configure VDD_DDR1 = LDO3
  89                 * Set LDO3 to 1.8V
  90                 * + bypass mode if BUCK3 = 1.8V
  91                 * + normal mode if BUCK3 != 1.8V
  92                 */
  93                ret = pmic_reg_read(dev,
  94                                    STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
  95                if (ret < 0)
  96                        return ret;
  97
  98                if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
  99                        buck3_at_1800000v = true;
 100
 101                ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
 102                if (ret < 0)
 103                        return ret;
 104
 105                ret &= ~STPMIC1_LDO3_MODE;
 106                ret &= ~STPMIC1_LDO12356_VOUT_MASK;
 107                ret |= STPMIC1_LDO3_1800000;
 108                if (buck3_at_1800000v)
 109                        ret |= STPMIC1_LDO3_MODE;
 110
 111                ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 112                                     ret);
 113                if (ret < 0)
 114                        return ret;
 115
 116                /* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
 117                switch (ddr_type) {
 118                case STM32MP_LPDDR2_32:
 119                case STM32MP_LPDDR3_32:
 120                        buck2 = STPMIC1_BUCK2_1250000V;
 121                        break;
 122                default:
 123                case STM32MP_LPDDR2_16:
 124                case STM32MP_LPDDR3_16:
 125                        buck2 = STPMIC1_BUCK2_1200000V;
 126                        break;
 127                }
 128
 129                ret = pmic_clrsetbits(dev,
 130                                      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
 131                                      STPMIC1_BUCK_VOUT_MASK,
 132                                      buck2);
 133                if (ret < 0)
 134                        return ret;
 135
 136                /* Enable VDD_DDR1 = LDO3 */
 137                ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 138                                      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
 139                if (ret < 0)
 140                        return ret;
 141
 142                mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 143
 144                /* Enable VDD_DDR2 =BUCK2 */
 145                ret = pmic_clrsetbits(dev,
 146                                      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
 147                                      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
 148                if (ret < 0)
 149                        return ret;
 150
 151                mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 152
 153                /* Enable VREF */
 154                ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
 155                                      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
 156                if (ret < 0)
 157                        return ret;
 158
 159                mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 160
 161                break;
 162
 163        default:
 164                break;
 165        };
 166
 167        return 0;
 168}
 169
 170static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv)
 171{
 172        u32 value;
 173
 174        /* VDDCORE= STMPCI1 BUCK1 ramp=+25mV, 5 => 725mV, 36 => 1500mV */
 175        value = ((voltage_mv - 725) / 25) + 5;
 176        if (value < 5)
 177                value = 5;
 178        if (value > 36)
 179                value = 36;
 180
 181        return pmic_clrsetbits(dev,
 182                               STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK1),
 183                               STPMIC1_BUCK_VOUT_MASK,
 184                               STPMIC1_BUCK_VOUT(value));
 185}
 186
 187/* early init of PMIC */
 188void stpmic1_init(u32 voltage_mv)
 189{
 190        struct udevice *dev;
 191
 192        if (uclass_get_device_by_driver(UCLASS_PMIC,
 193                                        DM_DRIVER_GET(pmic_stpmic1), &dev))
 194                return;
 195
 196        /* update VDDCORE = BUCK1 */
 197        if (voltage_mv)
 198                stmpic_buck1_set(dev, voltage_mv);
 199
 200        /* Keep vdd on during the reset cycle */
 201        pmic_clrsetbits(dev,
 202                        STPMIC1_BUCKS_MRST_CR,
 203                        STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
 204                        STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
 205
 206        /* Check if debug is enabled to program PMIC according to the bit */
 207        if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) {
 208                log_info("Keep debug unit ON\n");
 209
 210                pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
 211                                STPMIC1_MRST_BUCK_DEBUG,
 212                                STPMIC1_MRST_BUCK_DEBUG);
 213
 214                if (STPMIC1_MRST_LDO_DEBUG)
 215                        pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR,
 216                                        STPMIC1_MRST_LDO_DEBUG,
 217                                        STPMIC1_MRST_LDO_DEBUG);
 218        }
 219}
 220