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10#include <common.h>
11#include <env.h>
12#include <fastboot.h>
13#include <fdt_support.h>
14#include <image.h>
15#include <init.h>
16#include <malloc.h>
17#include <net.h>
18#include <palmas.h>
19#include <sata.h>
20#include <serial.h>
21#include <usb.h>
22#include <errno.h>
23#include <asm/global_data.h>
24#include <asm/omap_common.h>
25#include <asm/omap_sec_common.h>
26#include <asm/emif.h>
27#include <asm/gpio.h>
28#include <asm/arch/gpio.h>
29#include <asm/arch/clock.h>
30#include <asm/arch/dra7xx_iodelay.h>
31#include <asm/arch/sys_proto.h>
32#include <asm/arch/mmc_host_def.h>
33#include <asm/arch/sata.h>
34#include <asm/arch/gpio.h>
35#include <asm/arch/omap.h>
36#include <usb.h>
37#include <linux/usb/gadget.h>
38#include <dwc3-uboot.h>
39#include <dwc3-omap-uboot.h>
40#include <ti-usb-phy-uboot.h>
41#include <mmc.h>
42#include <dm/uclass.h>
43#include <hang.h>
44
45#include "../common/board_detect.h"
46#include "../common/cape_detect.h"
47#include "mux_data.h"
48
49#ifdef CONFIG_SUPPORT_EMMC_BOOT
50static int board_bootmode_has_emmc(void);
51#endif
52
53#define board_is_x15() board_ti_is("BBRDX15_")
54#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
55 !strncmp("B.10", board_ti_get_rev(), 3))
56#define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
57 !strncmp("C.00", board_ti_get_rev(), 3))
58#define board_is_am572x_evm() board_ti_is("AM572PM_")
59#define board_is_am572x_evm_reva3() \
60 (board_ti_is("AM572PM_") && \
61 !strncmp("A.30", board_ti_get_rev(), 3))
62#define board_is_am574x_idk() board_ti_is("AM574IDK")
63#define board_is_am572x_idk() board_ti_is("AM572IDK")
64#define board_is_am571x_idk() board_ti_is("AM571IDK")
65#define board_is_bbai() board_ti_is("BBONE-AI")
66
67#define board_is_ti_idk() board_is_am574x_idk() || \
68 board_is_am572x_idk() || \
69 board_is_am571x_idk()
70
71#ifdef CONFIG_DRIVER_TI_CPSW
72#include <cpsw.h>
73#endif
74
75DECLARE_GLOBAL_DATA_PTR;
76
77#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
78#define GPIO_DDR_VTT_EN GPIO_TO_PIN(7, 11)
79
80
81#define OSD_TS_FT_BUS_ADDRESS 0
82#define OSD_TS_FT_CHIP_ADDRESS 0x38
83#define OSD_TS_FT_REG_ID 0xA3
84
85
86
87
88
89#define OSD_TS_FT_ID_5x46 0x54
90
91#define OSD_TS_FT_ID_5606 0x08
92
93#define SYSINFO_BOARD_NAME_MAX_LEN 45
94
95#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
96#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
97
98const struct omap_sysinfo sysinfo = {
99 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
100};
101
102static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
103 .dmm_lisa_map_3 = 0x80740300,
104 .is_ma_present = 0x1
105};
106
107static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
108 .dmm_lisa_map_3 = 0x80640100,
109 .is_ma_present = 0x1
110};
111
112static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
113 .dmm_lisa_map_2 = 0xc0600200,
114 .dmm_lisa_map_3 = 0x80600100,
115 .is_ma_present = 0x1
116};
117
118static const struct dmm_lisa_map_regs bbai_lisa_regs = {
119 .dmm_lisa_map_3 = 0x80640100,
120 .is_ma_present = 0x1
121};
122
123void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
124{
125 if (board_is_am571x_idk())
126 *dmm_lisa_regs = &am571x_idk_lisa_regs;
127 else if (board_is_am574x_idk())
128 *dmm_lisa_regs = &am574x_idk_lisa_regs;
129 else if (board_is_bbai())
130 *dmm_lisa_regs = &bbai_lisa_regs;
131 else
132 *dmm_lisa_regs = &beagle_x15_lisa_regs;
133}
134
135static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
136 .sdram_config_init = 0x61851b32,
137 .sdram_config = 0x61851b32,
138 .sdram_config2 = 0x08000000,
139 .ref_ctrl = 0x000040F1,
140 .ref_ctrl_final = 0x00001035,
141 .sdram_tim1 = 0xcccf36ab,
142 .sdram_tim2 = 0x308f7fda,
143 .sdram_tim3 = 0x409f88a8,
144 .read_idle_ctrl = 0x00050000,
145 .zq_config = 0x5007190b,
146 .temp_alert_config = 0x00000000,
147 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
148 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
149 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
150 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
151 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
152 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
153 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
154 .emif_rd_wr_lvl_rmp_win = 0x00000000,
155 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
156 .emif_rd_wr_lvl_ctl = 0x00000000,
157 .emif_rd_wr_exec_thresh = 0x00000305
158};
159
160
161static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
162 0x10040100,
163 0x00910091,
164 0x00950095,
165 0x009B009B,
166 0x009E009E,
167 0x00980098,
168 0x00340034,
169 0x00350035,
170 0x00340034,
171 0x00310031,
172 0x00340034,
173 0x007F007F,
174 0x007F007F,
175 0x007F007F,
176 0x007F007F,
177 0x007F007F,
178 0x00480048,
179 0x004A004A,
180 0x00520052,
181 0x00550055,
182 0x00500050,
183 0x00000000,
184 0x00600020,
185 0x40011080,
186 0x08102040,
187 0x0,
188 0x0,
189 0x0,
190 0x0,
191 0x0,
192 0x0,
193 0x0,
194 0x0,
195 0x0,
196 0x0
197};
198
199static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
200 .sdram_config_init = 0x61851b32,
201 .sdram_config = 0x61851b32,
202 .sdram_config2 = 0x08000000,
203 .ref_ctrl = 0x000040F1,
204 .ref_ctrl_final = 0x00001035,
205 .sdram_tim1 = 0xcccf36b3,
206 .sdram_tim2 = 0x308f7fda,
207 .sdram_tim3 = 0x407f88a8,
208 .read_idle_ctrl = 0x00050000,
209 .zq_config = 0x5007190b,
210 .temp_alert_config = 0x00000000,
211 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
212 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
213 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
214 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
215 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
216 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
217 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
218 .emif_rd_wr_lvl_rmp_win = 0x00000000,
219 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
220 .emif_rd_wr_lvl_ctl = 0x00000000,
221 .emif_rd_wr_exec_thresh = 0x00000305
222};
223
224static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
225 0x10040100,
226 0x00910091,
227 0x00950095,
228 0x009B009B,
229 0x009E009E,
230 0x00980098,
231 0x00340034,
232 0x00350035,
233 0x00340034,
234 0x00310031,
235 0x00340034,
236 0x007F007F,
237 0x007F007F,
238 0x007F007F,
239 0x007F007F,
240 0x007F007F,
241 0x00480048,
242 0x004A004A,
243 0x00520052,
244 0x00550055,
245 0x00500050,
246 0x00000000,
247 0x00600020,
248 0x40011080,
249 0x08102040,
250 0x0,
251 0x0,
252 0x0,
253 0x0,
254 0x0,
255 0x0,
256 0x0,
257 0x0,
258 0x0,
259 0x0
260};
261
262static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
263 .sdram_config_init = 0x61863332,
264 .sdram_config = 0x61863332,
265 .sdram_config2 = 0x08000000,
266 .ref_ctrl = 0x0000514d,
267 .ref_ctrl_final = 0x0000144a,
268 .sdram_tim1 = 0xd333887c,
269 .sdram_tim2 = 0x30b37fe3,
270 .sdram_tim3 = 0x409f8ad8,
271 .read_idle_ctrl = 0x00050000,
272 .zq_config = 0x5007190b,
273 .temp_alert_config = 0x00000000,
274 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
275 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
276 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
277 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
278 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
279 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
280 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
281 .emif_rd_wr_lvl_rmp_win = 0x00000000,
282 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
283 .emif_rd_wr_lvl_ctl = 0x00000000,
284 .emif_rd_wr_exec_thresh = 0x00000305
285};
286
287static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
288 .sdram_config_init = 0x61863332,
289 .sdram_config = 0x61863332,
290 .sdram_config2 = 0x08000000,
291 .ref_ctrl = 0x0000514d,
292 .ref_ctrl_final = 0x0000144a,
293 .sdram_tim1 = 0xd333887c,
294 .sdram_tim2 = 0x30b37fe3,
295 .sdram_tim3 = 0x409f8ad8,
296 .read_idle_ctrl = 0x00050000,
297 .zq_config = 0x5007190b,
298 .temp_alert_config = 0x00000000,
299 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
300 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
301 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
302 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
303 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
304 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
305 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
306 .emif_rd_wr_lvl_rmp_win = 0x00000000,
307 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
308 .emif_rd_wr_lvl_ctl = 0x00000000,
309 .emif_rd_wr_exec_thresh = 0x00000305,
310 .emif_ecc_ctrl_reg = 0xD0000001,
311 .emif_ecc_address_range_1 = 0x3FFF0000,
312 .emif_ecc_address_range_2 = 0x00000000
313};
314
315void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
316{
317 switch (emif_nr) {
318 case 1:
319 if (board_is_am571x_idk())
320 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
321 else if (board_is_am574x_idk())
322 *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
323 else
324 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
325 break;
326 case 2:
327 if (board_is_am574x_idk())
328 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
329 else
330 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
331 break;
332 }
333}
334
335void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
336{
337 switch (emif_nr) {
338 case 1:
339 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
340 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
341 break;
342 case 2:
343 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
344 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
345 break;
346 }
347}
348
349struct vcores_data beagle_x15_volts = {
350 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
351 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
352 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
353 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
354 .mpu.pmic = &tps659038,
355 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
356
357 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
358 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
359 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
360 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
361 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
362 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
363 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
364 .eve.addr = TPS659038_REG_ADDR_SMPS45,
365 .eve.pmic = &tps659038,
366 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
367
368 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
369 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
370 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
371 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
372 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
373 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
374 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
375 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
376 .gpu.pmic = &tps659038,
377 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
378
379 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
380 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
381 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
382 .core.addr = TPS659038_REG_ADDR_SMPS6,
383 .core.pmic = &tps659038,
384
385 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
386 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
387 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
388 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
389 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
390 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
391 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
392 .iva.addr = TPS659038_REG_ADDR_SMPS45,
393 .iva.pmic = &tps659038,
394 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
395};
396
397struct vcores_data am572x_idk_volts = {
398 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
399 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
400 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
401 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
402 .mpu.pmic = &tps659038,
403 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
404
405 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
406 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
407 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
408 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
409 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
410 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
411 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
412 .eve.addr = TPS659038_REG_ADDR_SMPS45,
413 .eve.pmic = &tps659038,
414 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
415
416 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
417 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
418 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
419 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
420 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
421 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
422 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
423 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
424 .gpu.pmic = &tps659038,
425 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
426
427 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
428 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
429 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
430 .core.addr = TPS659038_REG_ADDR_SMPS7,
431 .core.pmic = &tps659038,
432
433 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
434 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
435 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
436 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
437 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
438 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
439 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
440 .iva.addr = TPS659038_REG_ADDR_SMPS8,
441 .iva.pmic = &tps659038,
442 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
443};
444
445struct vcores_data am571x_idk_volts = {
446 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
447 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
448 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
449 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
450 .mpu.pmic = &tps659038,
451 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
452
453 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
454 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
455 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
456 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
457 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
458 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
459 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
460 .eve.addr = TPS659038_REG_ADDR_SMPS45,
461 .eve.pmic = &tps659038,
462 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
463
464 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
465 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
466 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
467 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
468 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
469 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
470 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
471 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
472 .gpu.pmic = &tps659038,
473 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
474
475 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
476 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
477 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
478 .core.addr = TPS659038_REG_ADDR_SMPS7,
479 .core.pmic = &tps659038,
480
481 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
482 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
483 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
484 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
485 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
486 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
487 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
488 .iva.addr = TPS659038_REG_ADDR_SMPS45,
489 .iva.pmic = &tps659038,
490 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
491};
492
493int get_voltrail_opp(int rail_offset)
494{
495 int opp;
496
497 switch (rail_offset) {
498 case VOLT_MPU:
499 opp = DRA7_MPU_OPP;
500 break;
501 case VOLT_CORE:
502 opp = DRA7_CORE_OPP;
503 break;
504 case VOLT_GPU:
505 opp = DRA7_GPU_OPP;
506 break;
507 case VOLT_EVE:
508 opp = DRA7_DSPEVE_OPP;
509 break;
510 case VOLT_IVA:
511 opp = DRA7_IVA_OPP;
512 break;
513 default:
514 opp = OPP_NOM;
515 }
516
517 return opp;
518}
519
520
521#ifdef CONFIG_SPL_BUILD
522
523static inline void setup_board_eeprom_env(void) { }
524
525
526void do_board_detect(void)
527{
528 int rc;
529
530 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
531 CONFIG_EEPROM_CHIP_ADDRESS);
532 if (rc)
533 printf("ti_i2c_eeprom_init failed %d\n", rc);
534
535#ifdef CONFIG_SUPPORT_EMMC_BOOT
536 rc = board_bootmode_has_emmc();
537 if (!rc)
538 rc = ti_emmc_boardid_get();
539 if (rc)
540 printf("ti_emmc_boardid_get failed %d\n", rc);
541#endif
542}
543
544#else
545
546
547void do_board_detect(void)
548{
549 char *bname = NULL;
550 int rc;
551
552 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
553 CONFIG_EEPROM_CHIP_ADDRESS);
554 if (rc)
555 printf("ti_i2c_eeprom_init failed %d\n", rc);
556
557#ifdef CONFIG_SUPPORT_EMMC_BOOT
558 rc = board_bootmode_has_emmc();
559 if (!rc)
560 rc = ti_emmc_boardid_get();
561 if (rc)
562 printf("ti_emmc_boardid_get failed %d\n", rc);
563#endif
564
565 if (board_is_x15())
566 bname = "BeagleBoard X15";
567 else if (board_is_am572x_evm())
568 bname = "AM572x EVM";
569 else if (board_is_am574x_idk())
570 bname = "AM574x IDK";
571 else if (board_is_am572x_idk())
572 bname = "AM572x IDK";
573 else if (board_is_am571x_idk())
574 bname = "AM571x IDK";
575 else if (board_is_bbai())
576 bname = "BeagleBone AI";
577
578 if (bname)
579 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
580 "Board: %s REV %s\n", bname, board_ti_get_rev());
581}
582
583static void setup_board_eeprom_env(void)
584{
585 char *name = "beagle_x15";
586 int rc;
587
588 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
589 CONFIG_EEPROM_CHIP_ADDRESS);
590 if (rc)
591 goto invalid_eeprom;
592
593 if (board_is_x15()) {
594 if (board_is_x15_revb1())
595 name = "beagle_x15_revb1";
596 else if (board_is_x15_revc())
597 name = "beagle_x15_revc";
598 else
599 name = "beagle_x15";
600 } else if (board_is_am572x_evm()) {
601 if (board_is_am572x_evm_reva3())
602 name = "am57xx_evm_reva3";
603 else
604 name = "am57xx_evm";
605 } else if (board_is_am574x_idk()) {
606 name = "am574x_idk";
607 } else if (board_is_am572x_idk()) {
608 name = "am572x_idk";
609 } else if (board_is_am571x_idk()) {
610 name = "am571x_idk";
611 } else if (board_is_bbai()) {
612 name = "am5729_beagleboneai";
613 } else {
614 printf("Unidentified board claims %s in eeprom header\n",
615 board_ti_get_name());
616 }
617
618invalid_eeprom:
619 set_board_info_env(name);
620}
621
622#endif
623
624void vcores_init(void)
625{
626 if (board_is_am572x_idk() || board_is_am574x_idk())
627 *omap_vcores = &am572x_idk_volts;
628 else if (board_is_am571x_idk())
629 *omap_vcores = &am571x_idk_volts;
630 else
631 *omap_vcores = &beagle_x15_volts;
632}
633
634void hw_data_init(void)
635{
636 *prcm = &dra7xx_prcm;
637 if (is_dra72x())
638 *dplls_data = &dra72x_dplls;
639 else if (is_dra76x())
640 *dplls_data = &dra76x_dplls;
641 else
642 *dplls_data = &dra7xx_dplls;
643 *ctrl = &dra7xx_ctrl;
644}
645
646bool am571x_idk_needs_lcd(void)
647{
648 bool needs_lcd;
649
650 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
651 if (gpio_get_value(GPIO_ETH_LCD))
652 needs_lcd = false;
653 else
654 needs_lcd = true;
655
656 gpio_free(GPIO_ETH_LCD);
657
658 return needs_lcd;
659}
660
661int board_init(void)
662{
663 gpmc_init();
664 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
665
666 return 0;
667}
668
669void am57x_idk_lcd_detect(void)
670{
671 int r = -ENODEV;
672 char *idk_lcd = "no";
673 struct udevice *dev;
674
675
676 if (!board_is_ti_idk())
677 return;
678
679
680 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
681 goto out;
682
683 r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
684 OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
685 if (r) {
686 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
687 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
688 r);
689
690 if (board_is_am571x_idk())
691 printf("%s: Touch screen detect failed: %d!\n",
692 __func__, r);
693 goto out;
694 }
695
696
697 r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
698 if (r < 0) {
699 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
700 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
701 OSD_TS_FT_REG_ID, r);
702 goto out;
703 }
704
705 switch (r) {
706 case OSD_TS_FT_ID_5606:
707 idk_lcd = "osd101t2045";
708 break;
709 case OSD_TS_FT_ID_5x46:
710 idk_lcd = "osd101t2587";
711 break;
712 default:
713 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
714 __func__, r);
715
716 }
717out:
718 env_set("idk_lcd", idk_lcd);
719
720
721
722
723
724 if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
725 !strncmp(idk_lcd, "no", 2)) {
726 printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
727 __func__);
728 hang();
729 }
730
731 return;
732}
733
734#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
735static int device_okay(const char *path)
736{
737 int node;
738
739 node = fdt_path_offset(gd->fdt_blob, path);
740 if (node < 0)
741 return 0;
742
743 return fdtdec_get_is_enabled(gd->fdt_blob, node);
744}
745#endif
746
747int board_late_init(void)
748{
749 setup_board_eeprom_env();
750 u8 val;
751 struct udevice *dev;
752
753
754
755
756
757 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
758
759
760
761
762
763 if (get_device_type() == HS_DEVICE)
764 env_set("boot_fit", "1");
765
766
767
768
769
770
771
772 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
773 &val);
774 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
775 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
776 val);
777
778 omap_die_id_serial();
779 omap_set_fastboot_vars();
780
781 am57x_idk_lcd_detect();
782
783
784 uclass_get_device(UCLASS_CLK, 0, &dev);
785
786 if (board_is_bbai())
787 env_set("console", "ttyS0,115200n8");
788
789#if !defined(CONFIG_SPL_BUILD)
790 board_ti_set_ethaddr(2);
791#endif
792
793#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
794 if (device_okay("/ocp/omap_dwc3_1@48880000"))
795 enable_usb_clocks(0);
796 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
797 enable_usb_clocks(1);
798#endif
799 return 0;
800}
801
802void set_muxconf_regs(void)
803{
804 do_set_mux32((*ctrl)->control_padconf_core_base,
805 early_padconf, ARRAY_SIZE(early_padconf));
806
807#ifdef CONFIG_SUPPORT_EMMC_BOOT
808 do_set_mux32((*ctrl)->control_padconf_core_base,
809 emmc_padconf, ARRAY_SIZE(emmc_padconf));
810#endif
811}
812
813#ifdef CONFIG_IODELAY_RECALIBRATION
814void recalibrate_iodelay(void)
815{
816 const struct pad_conf_entry *pconf;
817 const struct iodelay_cfg_entry *iod, *delta_iod;
818 int pconf_sz, iod_sz, delta_iod_sz = 0;
819 int ret;
820
821 if (board_is_am572x_idk()) {
822 pconf = core_padconf_array_essential_am572x_idk;
823 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
824 iod = iodelay_cfg_array_am572x_idk;
825 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
826 } else if (board_is_am574x_idk()) {
827 pconf = core_padconf_array_essential_am574x_idk;
828 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
829 iod = iodelay_cfg_array_am574x_idk;
830 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
831 } else if (board_is_am571x_idk()) {
832 pconf = core_padconf_array_essential_am571x_idk;
833 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
834 iod = iodelay_cfg_array_am571x_idk;
835 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
836 } else if (board_is_bbai()) {
837 pconf = core_padconf_array_essential_bbai;
838 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
839 iod = iodelay_cfg_array_bbai;
840 iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
841 } else {
842
843 pconf = core_padconf_array_essential_x15;
844 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
845
846 if (omap_revision() == DRA752_ES1_1) {
847 iod = iodelay_cfg_array_x15_sr1_1;
848 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
849 } else {
850
851 iod = iodelay_cfg_array_x15_sr2_0;
852 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
853 }
854 }
855
856
857 ret = __recalibrate_iodelay_start();
858 if (ret)
859 goto err;
860
861
862 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
863
864
865 if (board_is_x15() || board_is_am572x_evm()) {
866 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
867 board_is_x15_revc()) {
868 pconf = core_padconf_array_delta_x15_sr2_0;
869 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
870 } else {
871 pconf = core_padconf_array_delta_x15_sr1_1;
872 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
873 }
874 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
875 }
876
877 if (board_is_am571x_idk()) {
878 if (am571x_idk_needs_lcd()) {
879 pconf = core_padconf_array_vout_am571x_idk;
880 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
881 delta_iod = iodelay_cfg_array_am571x_idk_4port;
882 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
883
884 } else {
885 pconf = core_padconf_array_icss1eth_am571x_idk;
886 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
887 }
888 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
889 }
890
891
892 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
893 if (delta_iod_sz)
894 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
895 delta_iod_sz);
896
897err:
898
899 __recalibrate_iodelay_end(ret);
900}
901#endif
902
903#if defined(CONFIG_MMC)
904int board_mmc_init(struct bd_info *bis)
905{
906 omap_mmc_init(0, 0, 0, -1, -1);
907 omap_mmc_init(1, 0, 0, -1, -1);
908 return 0;
909}
910
911static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
912 .hw_rev = "rev11",
913 .unsupported_caps = MMC_CAP(MMC_HS_200) |
914 MMC_CAP(UHS_SDR104),
915 .max_freq = 96000000,
916};
917
918static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
919 .hw_rev = "rev11",
920 .unsupported_caps = MMC_CAP(MMC_HS_200) |
921 MMC_CAP(UHS_SDR104) |
922 MMC_CAP(UHS_SDR50),
923 .max_freq = 48000000,
924};
925
926const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
927{
928 switch (omap_revision()) {
929 case DRA752_ES1_0:
930 case DRA752_ES1_1:
931 if (addr == OMAP_HSMMC1_BASE)
932 return &am57x_es1_1_mmc1_fixups;
933 else
934 return &am57x_es1_1_mmc23_fixups;
935 default:
936 return NULL;
937 }
938}
939#endif
940
941#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
942int spl_start_uboot(void)
943{
944
945 if (serial_tstc() && serial_getc() == 'c')
946 return 1;
947
948#ifdef CONFIG_SPL_ENV_SUPPORT
949 env_init();
950 env_load();
951 if (env_get_yesno("boot_os") != 1)
952 return 1;
953#endif
954
955 return 0;
956}
957#endif
958
959#ifdef CONFIG_DRIVER_TI_CPSW
960
961
962#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
963#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
964#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
965#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
966#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
967#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
968#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
969#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
970#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
971#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
972
973static void cpsw_control(int enabled)
974{
975
976}
977
978static struct cpsw_slave_data cpsw_slaves[] = {
979 {
980 .slave_reg_ofs = 0x208,
981 .sliver_reg_ofs = 0xd80,
982 .phy_addr = 1,
983 },
984 {
985 .slave_reg_ofs = 0x308,
986 .sliver_reg_ofs = 0xdc0,
987 .phy_addr = 2,
988 },
989};
990
991static struct cpsw_platform_data cpsw_data = {
992 .mdio_base = CPSW_MDIO_BASE,
993 .cpsw_base = CPSW_BASE,
994 .mdio_div = 0xff,
995 .channels = 8,
996 .cpdma_reg_ofs = 0x800,
997 .slaves = 1,
998 .slave_data = cpsw_slaves,
999 .ale_reg_ofs = 0xd00,
1000 .ale_entries = 1024,
1001 .host_port_reg_ofs = 0x108,
1002 .hw_stats_reg_ofs = 0x900,
1003 .bd_ram_ofs = 0x2000,
1004 .mac_control = (1 << 5),
1005 .control = cpsw_control,
1006 .host_port_num = 0,
1007 .version = CPSW_CTRL_VERSION_2,
1008};
1009
1010static u64 mac_to_u64(u8 mac[6])
1011{
1012 int i;
1013 u64 addr = 0;
1014
1015 for (i = 0; i < 6; i++) {
1016 addr <<= 8;
1017 addr |= mac[i];
1018 }
1019
1020 return addr;
1021}
1022
1023static void u64_to_mac(u64 addr, u8 mac[6])
1024{
1025 mac[5] = addr;
1026 mac[4] = addr >> 8;
1027 mac[3] = addr >> 16;
1028 mac[2] = addr >> 24;
1029 mac[1] = addr >> 32;
1030 mac[0] = addr >> 40;
1031}
1032
1033int board_eth_init(struct bd_info *bis)
1034{
1035 int ret;
1036 uint8_t mac_addr[6];
1037 uint32_t mac_hi, mac_lo;
1038 uint32_t ctrl_val;
1039 int i;
1040 u64 mac1, mac2;
1041 u8 mac_addr1[6], mac_addr2[6];
1042 int num_macs;
1043
1044
1045 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1046 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1047 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1048 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1049 mac_addr[2] = mac_hi & 0xFF;
1050 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1051 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1052 mac_addr[5] = mac_lo & 0xFF;
1053
1054 if (!env_get("ethaddr")) {
1055 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1056
1057 if (is_valid_ethaddr(mac_addr))
1058 eth_env_set_enetaddr("ethaddr", mac_addr);
1059 }
1060
1061 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1062 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1063 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1064 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1065 mac_addr[2] = mac_hi & 0xFF;
1066 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1067 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1068 mac_addr[5] = mac_lo & 0xFF;
1069
1070 if (!env_get("eth1addr")) {
1071 if (is_valid_ethaddr(mac_addr))
1072 eth_env_set_enetaddr("eth1addr", mac_addr);
1073 }
1074
1075 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1076 ctrl_val |= 0x22;
1077 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1078
1079
1080 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1081 board_is_am574x_idk()) {
1082 cpsw_data.slave_data[0].phy_addr = 0;
1083 cpsw_data.slave_data[1].phy_addr = 1;
1084 }
1085
1086 ret = cpsw_register(&cpsw_data);
1087 if (ret < 0)
1088 printf("Error %d registering CPSW switch\n", ret);
1089
1090
1091
1092
1093
1094 board_ti_get_eth_mac_addr(0, mac_addr1);
1095 board_ti_get_eth_mac_addr(1, mac_addr2);
1096
1097 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1098 mac1 = mac_to_u64(mac_addr1);
1099 mac2 = mac_to_u64(mac_addr2);
1100
1101
1102 num_macs = mac2 - mac1 + 1;
1103
1104 if (num_macs > 0 && num_macs <= 50) {
1105 for (i = 0; i < num_macs; i++) {
1106 u64_to_mac(mac1 + i, mac_addr);
1107 if (is_valid_ethaddr(mac_addr)) {
1108 eth_env_set_enetaddr_by_index("eth",
1109 i + 2,
1110 mac_addr);
1111 }
1112 }
1113 }
1114 }
1115
1116 return ret;
1117}
1118#endif
1119
1120#ifdef CONFIG_BOARD_EARLY_INIT_F
1121
1122static inline void vtt_regulator_enable(void)
1123{
1124 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1125 return;
1126
1127 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1128 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1129}
1130
1131int board_early_init_f(void)
1132{
1133 vtt_regulator_enable();
1134 return 0;
1135}
1136#endif
1137
1138#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1139int ft_board_setup(void *blob, struct bd_info *bd)
1140{
1141 ft_cpu_setup(blob, bd);
1142
1143 return 0;
1144}
1145#endif
1146
1147#ifdef CONFIG_SPL_LOAD_FIT
1148int board_fit_config_name_match(const char *name)
1149{
1150 if (board_is_x15()) {
1151 if (board_is_x15_revb1()) {
1152 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1153 return 0;
1154 } else if (board_is_x15_revc()) {
1155 if (!strcmp(name, "am57xx-beagle-x15-revc"))
1156 return 0;
1157 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1158 return 0;
1159 }
1160 } else if (board_is_am572x_evm() &&
1161 !strcmp(name, "am57xx-beagle-x15")) {
1162 return 0;
1163 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1164 return 0;
1165 } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1166 return 0;
1167 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1168 return 0;
1169 } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
1170 return 0;
1171 }
1172
1173 return -1;
1174}
1175#endif
1176
1177#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1178int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
1179{
1180 if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
1181 return -ENOTSUPP;
1182
1183 printf("Setting reboot to fastboot flag ...\n");
1184 env_set("dofastboot", "1");
1185 env_save();
1186 return 0;
1187}
1188#endif
1189
1190#ifdef CONFIG_SUPPORT_EMMC_BOOT
1191static int board_bootmode_has_emmc(void)
1192{
1193
1194 if (gd->arch.omap_boot_mode != 2)
1195 return -EIO;
1196
1197 return 0;
1198}
1199#endif
1200
1201#ifdef CONFIG_TI_SECURE_DEVICE
1202void board_fit_image_post_process(const void *fit, int node, void **p_image,
1203 size_t *p_size)
1204{
1205 secure_boot_verify_image(p_image, p_size);
1206}
1207
1208void board_tee_image_process(ulong tee_image, size_t tee_size)
1209{
1210 secure_tee_install((u32)tee_image);
1211}
1212
1213U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1214#endif
1215
