uboot/board/ti/beagle/beagle.h
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   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2008
   4 * Dirk Behme <dirk.behme@gmail.com>
   5 */
   6#ifndef _BEAGLE_H_
   7#define _BEAGLE_H_
   8
   9#include <asm/arch/dss.h>
  10
  11const omap3_sysinfo sysinfo = {
  12        DDR_STACKED,
  13        "OMAP3 Beagle board",
  14#if defined(CONFIG_ENV_IS_IN_ONENAND)
  15        "OneNAND",
  16#else
  17        "NAND",
  18#endif
  19};
  20
  21/* BeagleBoard revisions */
  22#define REVISION_AXBX   0x7
  23#define REVISION_CX     0x6
  24#define REVISION_C4     0x5
  25#define REVISION_XM_AB  0x0
  26#define REVISION_XM_C   0x2
  27
  28/*
  29 * IEN  - Input Enable
  30 * IDIS - Input Disable
  31 * PTD  - Pull type Down
  32 * PTU  - Pull type Up
  33 * DIS  - Pull type selection is inactive
  34 * EN   - Pull type selection is active
  35 * M0   - Mode 0
  36 * The commented string gives the final mux configuration for that pin
  37 */
  38#define MUX_BEAGLE() \
  39 /*SDRC*/\
  40        MUX_VAL(CP(SDRC_D0),            (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
  41        MUX_VAL(CP(SDRC_D1),            (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
  42        MUX_VAL(CP(SDRC_D2),            (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
  43        MUX_VAL(CP(SDRC_D3),            (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
  44        MUX_VAL(CP(SDRC_D4),            (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
  45        MUX_VAL(CP(SDRC_D5),            (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
  46        MUX_VAL(CP(SDRC_D6),            (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
  47        MUX_VAL(CP(SDRC_D7),            (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
  48        MUX_VAL(CP(SDRC_D8),            (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
  49        MUX_VAL(CP(SDRC_D9),            (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
  50        MUX_VAL(CP(SDRC_D10),           (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
  51        MUX_VAL(CP(SDRC_D11),           (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
  52        MUX_VAL(CP(SDRC_D12),           (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
  53        MUX_VAL(CP(SDRC_D13),           (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
  54        MUX_VAL(CP(SDRC_D14),           (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
  55        MUX_VAL(CP(SDRC_D15),           (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
  56        MUX_VAL(CP(SDRC_D16),           (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
  57        MUX_VAL(CP(SDRC_D17),           (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
  58        MUX_VAL(CP(SDRC_D18),           (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
  59        MUX_VAL(CP(SDRC_D19),           (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
  60        MUX_VAL(CP(SDRC_D20),           (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
  61        MUX_VAL(CP(SDRC_D21),           (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
  62        MUX_VAL(CP(SDRC_D22),           (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
  63        MUX_VAL(CP(SDRC_D23),           (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
  64        MUX_VAL(CP(SDRC_D24),           (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
  65        MUX_VAL(CP(SDRC_D25),           (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
  66        MUX_VAL(CP(SDRC_D26),           (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
  67        MUX_VAL(CP(SDRC_D27),           (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
  68        MUX_VAL(CP(SDRC_D28),           (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
  69        MUX_VAL(CP(SDRC_D29),           (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
  70        MUX_VAL(CP(SDRC_D30),           (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
  71        MUX_VAL(CP(SDRC_D31),           (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
  72        MUX_VAL(CP(SDRC_CLK),           (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
  73        MUX_VAL(CP(SDRC_DQS0),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
  74        MUX_VAL(CP(SDRC_DQS1),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
  75        MUX_VAL(CP(SDRC_DQS2),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
  76        MUX_VAL(CP(SDRC_DQS3),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
  77 /*GPMC*/\
  78        MUX_VAL(CP(GPMC_A1),            (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
  79        MUX_VAL(CP(GPMC_A2),            (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
  80        MUX_VAL(CP(GPMC_A3),            (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
  81        MUX_VAL(CP(GPMC_A4),            (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
  82        MUX_VAL(CP(GPMC_A5),            (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
  83        MUX_VAL(CP(GPMC_A6),            (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
  84        MUX_VAL(CP(GPMC_A7),            (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
  85        MUX_VAL(CP(GPMC_A8),            (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
  86        MUX_VAL(CP(GPMC_A9),            (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
  87        MUX_VAL(CP(GPMC_A10),           (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
  88        MUX_VAL(CP(GPMC_D0),            (IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
  89        MUX_VAL(CP(GPMC_D1),            (IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
  90        MUX_VAL(CP(GPMC_D2),            (IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
  91        MUX_VAL(CP(GPMC_D3),            (IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
  92        MUX_VAL(CP(GPMC_D4),            (IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
  93        MUX_VAL(CP(GPMC_D5),            (IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
  94        MUX_VAL(CP(GPMC_D6),            (IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
  95        MUX_VAL(CP(GPMC_D7),            (IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
  96        MUX_VAL(CP(GPMC_D8),            (IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
  97        MUX_VAL(CP(GPMC_D9),            (IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
  98        MUX_VAL(CP(GPMC_D10),           (IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
  99        MUX_VAL(CP(GPMC_D11),           (IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
 100        MUX_VAL(CP(GPMC_D12),           (IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
 101        MUX_VAL(CP(GPMC_D13),           (IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
 102        MUX_VAL(CP(GPMC_D14),           (IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
 103        MUX_VAL(CP(GPMC_D15),           (IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
 104        MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
 105        MUX_VAL(CP(GPMC_NCS1),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
 106        MUX_VAL(CP(GPMC_NCS2),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
 107        MUX_VAL(CP(GPMC_NCS3),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
 108        MUX_VAL(CP(GPMC_NCS4),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
 109        MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
 110        MUX_VAL(CP(GPMC_NCS6),          (IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
 111        MUX_VAL(CP(GPMC_NCS7),          (IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
 112        MUX_VAL(CP(GPMC_NBE1),          (IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
 113        MUX_VAL(CP(GPMC_WAIT2),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
 114        MUX_VAL(CP(GPMC_WAIT3),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
 115        MUX_VAL(CP(GPMC_CLK),           (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
 116        MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
 117        MUX_VAL(CP(GPMC_NOE),           (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
 118        MUX_VAL(CP(GPMC_NWE),           (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
 119        MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
 120        MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
 121        MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
 122        MUX_VAL(CP(GPMC_WAIT1),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
 123 /*DSS*/\
 124        MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
 125        MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
 126        MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
 127        MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
 128        MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
 129        MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
 130        MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
 131        MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
 132        MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
 133        MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
 134        MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
 135        MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
 136        MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
 137        MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
 138        MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
 139        MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
 140        MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
 141        MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
 142        MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
 143        MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
 144        MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
 145        MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
 146        MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
 147        MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
 148        MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
 149        MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
 150        MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
 151        MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
 152 /*CAMERA*/\
 153        MUX_VAL(CP(CAM_HS),             (IEN  | PTU | EN  | M0)) /*CAM_HS */\
 154        MUX_VAL(CP(CAM_VS),             (IEN  | PTU | EN  | M0)) /*CAM_VS */\
 155        MUX_VAL(CP(CAM_XCLKA),          (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
 156        MUX_VAL(CP(CAM_PCLK),           (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
 157        MUX_VAL(CP(CAM_FLD),            (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
 158        MUX_VAL(CP(CAM_D0),             (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
 159        MUX_VAL(CP(CAM_D1),             (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
 160        MUX_VAL(CP(CAM_D2),             (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
 161        MUX_VAL(CP(CAM_D3),             (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
 162        MUX_VAL(CP(CAM_D4),             (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
 163        MUX_VAL(CP(CAM_D5),             (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
 164        MUX_VAL(CP(CAM_D6),             (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
 165        MUX_VAL(CP(CAM_D7),             (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
 166        MUX_VAL(CP(CAM_D8),             (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
 167        MUX_VAL(CP(CAM_D9),             (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
 168        MUX_VAL(CP(CAM_D10),            (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
 169        MUX_VAL(CP(CAM_D11),            (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
 170        MUX_VAL(CP(CAM_XCLKB),          (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
 171        MUX_VAL(CP(CAM_WEN),            (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
 172        MUX_VAL(CP(CAM_STROBE),         (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
 173        MUX_VAL(CP(CSI2_DX0),           (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
 174        MUX_VAL(CP(CSI2_DY0),           (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
 175        MUX_VAL(CP(CSI2_DX1),           (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
 176        MUX_VAL(CP(CSI2_DY1),           (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
 177 /*Audio Interface */\
 178        MUX_VAL(CP(MCBSP2_FSX),         (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
 179        MUX_VAL(CP(MCBSP2_CLKX),        (IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
 180        MUX_VAL(CP(MCBSP2_DR),          (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
 181        MUX_VAL(CP(MCBSP2_DX),          (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
 182 /*Expansion card */\
 183        MUX_VAL(CP(MMC1_CLK),           (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
 184        MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
 185        MUX_VAL(CP(MMC1_DAT0),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
 186        MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
 187        MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
 188        MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
 189        MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
 190        MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
 191        MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
 192        MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
 193 /*Wireless LAN */\
 194        MUX_VAL(CP(MMC2_CLK),           (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
 195        MUX_VAL(CP(MMC2_CMD),           (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
 196        MUX_VAL(CP(MMC2_DAT0),          (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
 197        MUX_VAL(CP(MMC2_DAT1),          (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
 198        MUX_VAL(CP(MMC2_DAT2),          (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
 199        MUX_VAL(CP(MMC2_DAT3),          (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
 200        MUX_VAL(CP(MMC2_DAT4),          (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
 201        MUX_VAL(CP(MMC2_DAT5),          (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
 202        MUX_VAL(CP(MMC2_DAT6),          (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
 203        MUX_VAL(CP(MMC2_DAT7),          (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
 204 /*Bluetooth*/\
 205        MUX_VAL(CP(MCBSP3_DX),          (IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
 206        MUX_VAL(CP(MCBSP3_DR),          (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
 207        MUX_VAL(CP(MCBSP3_CLKX),        (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
 208        MUX_VAL(CP(MCBSP3_FSX),         (IEN  | PTD | DIS | M1)) /*UART2_RX*/\
 209        MUX_VAL(CP(UART2_CTS),          (IEN  | PTD | DIS | M4)) /*GPIO_144*/\
 210        MUX_VAL(CP(UART2_RTS),          (IEN  | PTD | DIS | M4)) /*GPIO_145*/\
 211        MUX_VAL(CP(UART2_TX),           (IEN  | PTD | DIS | M4)) /*GPIO_146*/\
 212        MUX_VAL(CP(UART2_RX),           (IEN  | PTD | DIS | M4)) /*GPIO_147*/\
 213 /*Modem Interface */\
 214        MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
 215        MUX_VAL(CP(UART1_RTS),          (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
 216        MUX_VAL(CP(UART1_CTS),          (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
 217        MUX_VAL(CP(UART1_RX),           (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
 218        MUX_VAL(CP(MCBSP4_CLKX),        (IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
 219        MUX_VAL(CP(MCBSP4_DR),          (IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
 220        MUX_VAL(CP(MCBSP4_DX),          (IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
 221        MUX_VAL(CP(MCBSP4_FSX),         (IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
 222        MUX_VAL(CP(MCBSP1_CLKR),        (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
 223        MUX_VAL(CP(MCBSP1_FSR),         (IDIS | PTU | EN  | M4)) /*GPIO_157*/\
 224        MUX_VAL(CP(MCBSP1_DX),          (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
 225        MUX_VAL(CP(MCBSP1_DR),          (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
 226        MUX_VAL(CP(MCBSP_CLKS),         (IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
 227        MUX_VAL(CP(MCBSP1_FSX),         (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
 228        MUX_VAL(CP(MCBSP1_CLKX),        (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
 229 /*Serial Interface*/\
 230        MUX_VAL(CP(UART3_CTS_RCTX),     (IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
 231        MUX_VAL(CP(UART3_RTS_SD),       (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
 232        MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
 233        MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
 234        MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
 235        MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
 236        MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
 237        MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
 238        MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
 239        MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
 240        MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
 241        MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
 242        MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
 243        MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
 244        MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
 245        MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
 246        MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
 247        MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
 248        MUX_VAL(CP(I2C2_SCL),           (IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
 249        MUX_VAL(CP(I2C2_SDA),           (IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
 250        MUX_VAL(CP(I2C3_SCL),           (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
 251        MUX_VAL(CP(I2C3_SDA),           (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
 252        MUX_VAL(CP(I2C4_SCL),           (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
 253        MUX_VAL(CP(I2C4_SDA),           (IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
 254        MUX_VAL(CP(HDQ_SIO),            (IDIS | PTU | EN  | M4)) /*GPIO_170*/\
 255        MUX_VAL(CP(MCSPI1_CLK),         (IEN  | PTU | EN  | M4)) /*GPIO_171*/\
 256        MUX_VAL(CP(MCSPI1_SIMO),        (IEN  | PTU | EN  | M4)) /*GPIO_172*/\
 257        MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTU | EN  | M4)) /*GPIO_173*/\
 258        MUX_VAL(CP(MCSPI1_CS0),         (IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
 259        MUX_VAL(CP(MCSPI1_CS1),         (IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
 260        MUX_VAL(CP(MCSPI1_CS2),         (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
 261 /* USB EHCI (port 2) */\
 262        MUX_VAL(CP(MCSPI1_CS3),         (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA2*/\
 263        MUX_VAL(CP(MCSPI2_CLK),         (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA7*/\
 264        MUX_VAL(CP(MCSPI2_SIMO),        (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA4*/\
 265        MUX_VAL(CP(MCSPI2_SOMI),        (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA5*/\
 266        MUX_VAL(CP(MCSPI2_CS0),         (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA6*/\
 267        MUX_VAL(CP(MCSPI2_CS1),         (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA3*/\
 268        MUX_VAL(CP(ETK_D10_ES2),        (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
 269        MUX_VAL(CP(ETK_D11_ES2),        (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
 270        MUX_VAL(CP(ETK_D12_ES2),        (IEN  | PTD | EN  | M3)) /*HSUSB2_DIR*/\
 271        MUX_VAL(CP(ETK_D13_ES2),        (IEN  | PTD | EN  | M3)) /*HSUSB2_NXT*/\
 272        MUX_VAL(CP(ETK_D14_ES2),        (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA0*/\
 273        MUX_VAL(CP(ETK_D15_ES2),        (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA1*/\
 274 /*Control and debug */\
 275        MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
 276        MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
 277        MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
 278        MUX_VAL(CP(SYS_BOOT0),          (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
 279        MUX_VAL(CP(SYS_BOOT1),          (IEN  | PTD | DIS | M4)) /*GPIO_3*/\
 280        MUX_VAL(CP(SYS_BOOT2),          (IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
 281        MUX_VAL(CP(SYS_BOOT3),          (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
 282        MUX_VAL(CP(SYS_BOOT4),          (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
 283        MUX_VAL(CP(SYS_BOOT5),          (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
 284        MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
 285        MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
 286        MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
 287        MUX_VAL(CP(SYS_CLKOUT2),        (IEN  | PTU | EN  | M4)) /*GPIO_186*/\
 288        MUX_VAL(CP(ETK_CLK_ES2),        (IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
 289        MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
 290        MUX_VAL(CP(ETK_D0_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
 291        MUX_VAL(CP(ETK_D1_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
 292        MUX_VAL(CP(ETK_D2_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
 293        MUX_VAL(CP(ETK_D3_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
 294        MUX_VAL(CP(ETK_D4_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
 295        MUX_VAL(CP(ETK_D5_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
 296        MUX_VAL(CP(ETK_D6_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
 297        MUX_VAL(CP(ETK_D7_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
 298        MUX_VAL(CP(ETK_D8_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
 299        MUX_VAL(CP(ETK_D9_ES2),         (IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
 300        MUX_VAL(CP(D2D_MCAD1),          (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
 301        MUX_VAL(CP(D2D_MCAD2),          (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
 302        MUX_VAL(CP(D2D_MCAD3),          (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
 303        MUX_VAL(CP(D2D_MCAD4),          (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
 304        MUX_VAL(CP(D2D_MCAD5),          (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
 305        MUX_VAL(CP(D2D_MCAD6),          (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
 306        MUX_VAL(CP(D2D_MCAD7),          (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
 307        MUX_VAL(CP(D2D_MCAD8),          (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
 308        MUX_VAL(CP(D2D_MCAD9),          (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
 309        MUX_VAL(CP(D2D_MCAD10),         (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
 310        MUX_VAL(CP(D2D_MCAD11),         (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
 311        MUX_VAL(CP(D2D_MCAD12),         (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
 312        MUX_VAL(CP(D2D_MCAD13),         (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
 313        MUX_VAL(CP(D2D_MCAD14),         (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
 314        MUX_VAL(CP(D2D_MCAD15),         (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
 315        MUX_VAL(CP(D2D_MCAD16),         (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
 316        MUX_VAL(CP(D2D_MCAD17),         (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
 317        MUX_VAL(CP(D2D_MCAD18),         (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
 318        MUX_VAL(CP(D2D_MCAD19),         (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
 319        MUX_VAL(CP(D2D_MCAD20),         (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
 320        MUX_VAL(CP(D2D_MCAD21),         (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
 321        MUX_VAL(CP(D2D_MCAD22),         (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
 322        MUX_VAL(CP(D2D_MCAD23),         (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
 323        MUX_VAL(CP(D2D_MCAD24),         (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
 324        MUX_VAL(CP(D2D_MCAD25),         (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
 325        MUX_VAL(CP(D2D_MCAD26),         (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
 326        MUX_VAL(CP(D2D_MCAD27),         (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
 327        MUX_VAL(CP(D2D_MCAD28),         (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
 328        MUX_VAL(CP(D2D_MCAD29),         (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
 329        MUX_VAL(CP(D2D_MCAD30),         (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
 330        MUX_VAL(CP(D2D_MCAD31),         (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
 331        MUX_VAL(CP(D2D_MCAD32),         (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
 332        MUX_VAL(CP(D2D_MCAD33),         (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
 333        MUX_VAL(CP(D2D_MCAD34),         (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
 334        MUX_VAL(CP(D2D_MCAD35),         (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
 335        MUX_VAL(CP(D2D_MCAD36),         (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
 336        MUX_VAL(CP(D2D_CLK26MI),        (IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
 337        MUX_VAL(CP(D2D_NRESPWRON),      (IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
 338        MUX_VAL(CP(D2D_NRESWARM),       (IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
 339        MUX_VAL(CP(D2D_ARM9NIRQ),       (IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
 340        MUX_VAL(CP(D2D_UMA2P6FIQ),      (IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
 341        MUX_VAL(CP(D2D_SPINT),          (IEN  | PTD | EN  | M0)) /*d2d_spint*/\
 342        MUX_VAL(CP(D2D_FRINT),          (IEN  | PTD | EN  | M0)) /*d2d_frint*/\
 343        MUX_VAL(CP(D2D_DMAREQ0),        (IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
 344        MUX_VAL(CP(D2D_DMAREQ1),        (IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
 345        MUX_VAL(CP(D2D_DMAREQ2),        (IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
 346        MUX_VAL(CP(D2D_DMAREQ3),        (IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
 347        MUX_VAL(CP(D2D_N3GTRST),        (IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
 348        MUX_VAL(CP(D2D_N3GTDI),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
 349        MUX_VAL(CP(D2D_N3GTDO),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
 350        MUX_VAL(CP(D2D_N3GTMS),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
 351        MUX_VAL(CP(D2D_N3GTCK),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
 352        MUX_VAL(CP(D2D_N3GRTCK),        (IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
 353        MUX_VAL(CP(D2D_MSTDBY),         (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
 354        MUX_VAL(CP(D2D_SWAKEUP),        (IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
 355        MUX_VAL(CP(D2D_IDLEREQ),        (IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
 356        MUX_VAL(CP(D2D_IDLEACK),        (IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
 357        MUX_VAL(CP(D2D_MWRITE),         (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
 358        MUX_VAL(CP(D2D_SWRITE),         (IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
 359        MUX_VAL(CP(D2D_MREAD),          (IEN  | PTD | DIS | M0)) /*d2d_mread*/\
 360        MUX_VAL(CP(D2D_SREAD),          (IEN  | PTD | DIS | M0)) /*d2d_sread*/\
 361        MUX_VAL(CP(D2D_MBUSFLAG),       (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
 362        MUX_VAL(CP(D2D_SBUSFLAG),       (IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
 363        MUX_VAL(CP(SDRC_CKE0),          (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
 364        MUX_VAL(CP(SDRC_CKE1),          (IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 365
 366#define MUX_BEAGLE_C() \
 367        MUX_VAL(CP(MCBSP3_DX),          (IEN  | PTD | DIS | M4)) /*GPIO_140*/\
 368        MUX_VAL(CP(MCBSP3_DR),          (IEN  | PTD | DIS | M4)) /*GPIO_142*/\
 369        MUX_VAL(CP(MCBSP3_CLKX),        (IEN  | PTD | DIS | M4)) /*GPIO_141*/\
 370        MUX_VAL(CP(UART2_CTS),          (IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
 371        MUX_VAL(CP(UART2_RTS),          (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
 372        MUX_VAL(CP(UART2_TX),           (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
 373        MUX_VAL(CP(UART2_RX),           (IDIS | PTU | EN  | M4)) /*GPIO_147*/
 374
 375#define MUX_BEAGLE_XM() \
 376        MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTD | EN  | M4)) /*GPIO_56*/\
 377        MUX_VAL(CP(GPMC_WAIT1),         (IDIS | PTU | EN  | M4)) /*GPIO_63*/\
 378        MUX_VAL(CP(MMC1_DAT7),          (IDIS | PTU | EN  | M4)) /*GPIO_129*/\
 379        MUX_VAL(CP(HDQ_SIO),            (IDIS | PTU | EN  | M4)) /*GPIO_170*/\
 380        MUX_VAL(CP(MCBSP3_DX),          (IEN  | PTD | DIS | M4)) /*GPIO_140*/\
 381        MUX_VAL(CP(MCBSP3_DR),          (IEN  | PTD | DIS | M4)) /*GPIO_142*/\
 382        MUX_VAL(CP(MCBSP3_CLKX),        (IEN  | PTD | DIS | M4)) /*GPIO_141*/\
 383        MUX_VAL(CP(UART2_CTS),          (IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
 384        MUX_VAL(CP(UART2_RTS),          (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
 385        MUX_VAL(CP(UART2_TX),           (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
 386        MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M7)) /*safe_mode*/\
 387        MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M7)) /*safe_mode*/\
 388        MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M7)) /*safe_mode*/\
 389        MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M7)) /*safe_mode*/\
 390        MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M7)) /*safe_mode*/\
 391        MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M7)) /*safe_mode*/\
 392        MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
 393        MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
 394        MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
 395        MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
 396        MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
 397        MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
 398        MUX_VAL(CP(SYS_BOOT0),          (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
 399        MUX_VAL(CP(SYS_BOOT1),          (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
 400        MUX_VAL(CP(SYS_BOOT3),          (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
 401        MUX_VAL(CP(SYS_BOOT4),          (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
 402        MUX_VAL(CP(SYS_BOOT5),          (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
 403        MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
 404
 405#define MUX_TINCANTOOLS_ZIPPY() \
 406        MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
 407        MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
 408        MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
 409        MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
 410        MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
 411        MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
 412        MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
 413        MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
 414        MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
 415        MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
 416        MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | EN  | M1)) /*MCSPI4_CLK*/\
 417        MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTU | EN  | M4)) /*GPIO_157*/\
 418        MUX_VAL(CP(MCBSP1_DX),      (IEN  | PTD | EN  | M1)) /*MCSPI4_SIMO*/\
 419        MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
 420        MUX_VAL(CP(MCBSP1_FSX),     (IEN  | PTD | EN  | M1)) /*MCSPI4_CS0*/\
 421        MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_162*/\
 422        MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_140*/\
 423        MUX_VAL(CP(MCBSP3_DR),      (IEN  | PTD | DIS | M4)) /*GPIO_142*/\
 424        MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_141*/
 425
 426#define MUX_TINCANTOOLS_TRAINER() \
 427        MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
 428        MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
 429        MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
 430        MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
 431        MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
 432        MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
 433        MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
 434        MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
 435        MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
 436        MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
 437        MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTU | EN  | M4)) /*GPIO_140*/\
 438        MUX_VAL(CP(MCBSP3_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_141*/\
 439        MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTU | EN  | M4)) /*GPIO_162*/
 440
 441#define MUX_KBADC_BEAGLEFPGA() \
 442        MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTU | DIS | M1)) /*MCSPI4_CLK*/\
 443        MUX_VAL(CP(MCBSP1_DX),      (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
 444        MUX_VAL(CP(MCBSP1_DR),      (IEN  | PTU | EN  | M1)) /*MCSPI4_SOMI*/\
 445        MUX_VAL(CP(MCBSP1_FSX),     (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
 446
 447#define MUX_BBTOYS_WIFI() \
 448        MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
 449        MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
 450        MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
 451        MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
 452        MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
 453        MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
 454        MUX_VAL(CP(MMC2_DAT4),      (IDIS | PTU | EN  | M4)) /*GPIO_136 FM_EN/BT_WU*/\
 455        MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137 WLAN_IRQ*/\
 456        MUX_VAL(CP(MMC2_DAT6),      (IDIS | PTU | EN  | M4)) /*GPIO_138 BT_EN*/\
 457        MUX_VAL(CP(MMC2_DAT7),      (IDIS | PTU | EN  | M4)) /*GPIO_139 WLAN_EN*/
 458
 459/*
 460 * Display Configuration
 461 */
 462
 463#define DVI_BEAGLE_ORANGE_COL           0x00FF8000
 464#define VENC_HEIGHT                     0x00ef
 465#define VENC_WIDTH                      0x027f
 466
 467/*
 468 * Configure VENC in DSS for Beagle to generate Color Bar
 469 *
 470 * Kindly refer to OMAP TRM for definition of these values.
 471 */
 472static const struct venc_regs venc_config_std_tv = {
 473        .status                                 = 0x0000001B,
 474        .f_control                              = 0x00000040,
 475        .vidout_ctrl                            = 0x00000000,
 476        .sync_ctrl                              = 0x00008000,
 477        .llen                                   = 0x00008359,
 478        .flens                                  = 0x0000020C,
 479        .hfltr_ctrl                             = 0x00000000,
 480        .cc_carr_wss_carr                       = 0x043F2631,
 481        .c_phase                                = 0x00000024,
 482        .gain_u                                 = 0x00000130,
 483        .gain_v                                 = 0x00000198,
 484        .gain_y                                 = 0x000001C0,
 485        .black_level                            = 0x0000006A,
 486        .blank_level                            = 0x0000005C,
 487        .x_color                                = 0x00000000,
 488        .m_control                              = 0x00000001,
 489        .bstamp_wss_data                        = 0x0000003F,
 490        .s_carr                                 = 0x21F07C1F,
 491        .line21                                 = 0x00000000,
 492        .ln_sel                                 = 0x00000015,
 493        .l21__wc_ctl                            = 0x00001400,
 494        .htrigger_vtrigger                      = 0x00000000,
 495        .savid__eavid                           = 0x069300F4,
 496        .flen__fal                              = 0x0016020C,
 497        .lal__phase_reset                       = 0x00060107,
 498        .hs_int_start_stop_x                    = 0x008D034E,
 499        .hs_ext_start_stop_x                    = 0x000F0359,
 500        .vs_int_start_x                         = 0x01A00000,
 501        .vs_int_stop_x__vs_int_start_y          = 0x020501A0,
 502        .vs_int_stop_y__vs_ext_start_x          = 0x01AC0024,
 503        .vs_ext_stop_x__vs_ext_start_y          = 0x020D01AC,
 504        .vs_ext_stop_y                          = 0x00000006,
 505        .avid_start_stop_x                      = 0x03480079,
 506        .avid_start_stop_y                      = 0x02040024,
 507        .fid_int_start_x__fid_int_start_y       = 0x0001008A,
 508        .fid_int_offset_y__fid_ext_start_x      = 0x01AC0106,
 509        .fid_ext_start_y__fid_ext_offset_y      = 0x01060006,
 510        .tvdetgp_int_start_stop_x               = 0x00140001,
 511        .tvdetgp_int_start_stop_y               = 0x00010001,
 512        .gen_ctrl                               = 0x00FF0000,
 513        .output_control                         = 0x0000000D,
 514        .dac_b__dac_c                           = 0x00000000
 515};
 516
 517/*
 518 * Configure Timings for DVI D
 519 */
 520static const struct panel_config dvid_cfg = {
 521        .timing_h       = 0x0ff03f31, /* Horizontal timing */
 522        .timing_v       = 0x01400504, /* Vertical timing */
 523        .pol_freq       = 0x00007028, /* Pol Freq */
 524        .divisor        = 0x00010006, /* 72Mhz Pixel Clock */
 525        .lcd_size       = 0x02ff03ff, /* 1024x768 */
 526        .panel_type     = 0x01, /* TFT */
 527        .data_lines     = 0x03, /* 24 Bit RGB */
 528        .load_mode      = 0x02, /* Frame Mode */
 529        .panel_color    = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
 530        .gfx_format     = GFXFORMAT_RGB24_UNPACKED,
 531};
 532
 533static const struct panel_config dvid_cfg_xm = {
 534        .timing_h       = 0x1a4024c9, /* Horizontal timing */
 535        .timing_v       = 0x02c00509, /* Vertical timing */
 536        .pol_freq       = 0x00007028, /* Pol Freq */
 537        .divisor        = 0x00010001, /* 96MHz Pixel Clock */
 538        .lcd_size       = 0x02ff03ff, /* 1024x768 */
 539        .panel_type     = 0x01, /* TFT */
 540        .data_lines     = 0x03, /* 24 Bit RGB */
 541        .load_mode      = 0x02, /* Frame Mode */
 542        .panel_color    = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
 543        .gfx_format     = GFXFORMAT_RGB24_UNPACKED,
 544};
 545#endif
 546
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.