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12#include <common.h>
13#include <env.h>
14#include <fdt_support.h>
15#include <fastboot.h>
16#include <image.h>
17#include <init.h>
18#include <spl.h>
19#include <net.h>
20#include <palmas.h>
21#include <sata.h>
22#include <serial.h>
23#include <asm/global_data.h>
24#include <linux/string.h>
25#include <asm/gpio.h>
26#include <usb.h>
27#include <linux/usb/gadget.h>
28#include <asm/omap_common.h>
29#include <asm/omap_sec_common.h>
30#include <asm/arch/gpio.h>
31#include <asm/arch/dra7xx_iodelay.h>
32#include <asm/emif.h>
33#include <asm/arch/sys_proto.h>
34#include <asm/arch/mmc_host_def.h>
35#include <asm/arch/sata.h>
36#include <dwc3-uboot.h>
37#include <dwc3-omap-uboot.h>
38#include <i2c.h>
39#include <ti-usb-phy-uboot.h>
40
41#include "mux_data.h"
42#include "../common/board_detect.h"
43
44#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
45#define board_is_dra74x_evm() board_ti_is("5777xCPU")
46#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
47#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
48#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
49 (strncmp("H", board_ti_get_rev(), 1) <= 0))
50#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
51 (strncmp("C", board_ti_get_rev(), 1) <= 0))
52#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
53 board_ti_get_emif2_size()
54
55DECLARE_GLOBAL_DATA_PTR;
56
57
58#define GPIO_DDR_VTT_EN 203
59
60#define SYSINFO_BOARD_NAME_MAX_LEN 37
61
62
63#define NAND_PCF8575_ADDR 0x21
64#define NAND_PCF8575_I2C_BUS_NUM 0
65
66const struct omap_sysinfo sysinfo = {
67 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
68};
69
70static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
71 .sdram_config_init = 0x61851ab2,
72 .sdram_config = 0x61851ab2,
73 .sdram_config2 = 0x08000000,
74 .ref_ctrl = 0x000040F1,
75 .ref_ctrl_final = 0x00001035,
76 .sdram_tim1 = 0xCCCF36B3,
77 .sdram_tim2 = 0x308F7FDA,
78 .sdram_tim3 = 0x427F88A8,
79 .read_idle_ctrl = 0x00050000,
80 .zq_config = 0x0007190B,
81 .temp_alert_config = 0x00000000,
82 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
83 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
84 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
85 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
86 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
87 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
88 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
89 .emif_rd_wr_lvl_rmp_win = 0x00000000,
90 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
91 .emif_rd_wr_lvl_ctl = 0x00000000,
92 .emif_rd_wr_exec_thresh = 0x00000305
93};
94
95static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
96 .sdram_config_init = 0x61851B32,
97 .sdram_config = 0x61851B32,
98 .sdram_config2 = 0x08000000,
99 .ref_ctrl = 0x000040F1,
100 .ref_ctrl_final = 0x00001035,
101 .sdram_tim1 = 0xCCCF36B3,
102 .sdram_tim2 = 0x308F7FDA,
103 .sdram_tim3 = 0x427F88A8,
104 .read_idle_ctrl = 0x00050000,
105 .zq_config = 0x0007190B,
106 .temp_alert_config = 0x00000000,
107 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
108 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
109 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
110 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
111 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
112 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
113 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
114 .emif_rd_wr_lvl_rmp_win = 0x00000000,
115 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
116 .emif_rd_wr_lvl_ctl = 0x00000000,
117 .emif_rd_wr_exec_thresh = 0x00000305
118};
119
120static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
121 .sdram_config_init = 0x61862B32,
122 .sdram_config = 0x61862B32,
123 .sdram_config2 = 0x08000000,
124 .ref_ctrl = 0x0000514C,
125 .ref_ctrl_final = 0x0000144A,
126 .sdram_tim1 = 0xD113781C,
127 .sdram_tim2 = 0x30717FE3,
128 .sdram_tim3 = 0x409F86A8,
129 .read_idle_ctrl = 0x00050000,
130 .zq_config = 0x5007190B,
131 .temp_alert_config = 0x00000000,
132 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
133 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
134 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
135 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
136 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
137 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
138 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
139 .emif_rd_wr_lvl_rmp_win = 0x00000000,
140 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
141 .emif_rd_wr_lvl_ctl = 0x00000000,
142 .emif_rd_wr_exec_thresh = 0x00000305
143};
144
145const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
146 .sdram_config_init = 0x61862BB2,
147 .sdram_config = 0x61862BB2,
148 .sdram_config2 = 0x00000000,
149 .ref_ctrl = 0x0000514D,
150 .ref_ctrl_final = 0x0000144A,
151 .sdram_tim1 = 0xD1137824,
152 .sdram_tim2 = 0x30B37FE3,
153 .sdram_tim3 = 0x409F8AD8,
154 .read_idle_ctrl = 0x00050000,
155 .zq_config = 0x5007190B,
156 .temp_alert_config = 0x00000000,
157 .emif_ddr_phy_ctlr_1_init = 0x0824400E,
158 .emif_ddr_phy_ctlr_1 = 0x0E24400E,
159 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
160 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
161 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
162 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
163 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
164 .emif_rd_wr_lvl_rmp_win = 0x00000000,
165 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
166 .emif_rd_wr_lvl_ctl = 0x00000000,
167 .emif_rd_wr_exec_thresh = 0x00000305
168};
169
170const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
171 .sdram_config_init = 0x61851ab2,
172 .sdram_config = 0x61851ab2,
173 .sdram_config2 = 0x08000000,
174 .ref_ctrl = 0x000040F1,
175 .ref_ctrl_final = 0x00001035,
176 .sdram_tim1 = 0xCCCF36B3,
177 .sdram_tim2 = 0x30BF7FDA,
178 .sdram_tim3 = 0x427F8BA8,
179 .read_idle_ctrl = 0x00050000,
180 .zq_config = 0x0007190B,
181 .temp_alert_config = 0x00000000,
182 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
183 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
184 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
185 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
186 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
187 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
188 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
189 .emif_rd_wr_lvl_rmp_win = 0x00000000,
190 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
191 .emif_rd_wr_lvl_ctl = 0x00000000,
192 .emif_rd_wr_exec_thresh = 0x00000305
193};
194
195const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
196 .sdram_config_init = 0x61851B32,
197 .sdram_config = 0x61851B32,
198 .sdram_config2 = 0x08000000,
199 .ref_ctrl = 0x000040F1,
200 .ref_ctrl_final = 0x00001035,
201 .sdram_tim1 = 0xCCCF36B3,
202 .sdram_tim2 = 0x308F7FDA,
203 .sdram_tim3 = 0x427F88A8,
204 .read_idle_ctrl = 0x00050000,
205 .zq_config = 0x0007190B,
206 .temp_alert_config = 0x00000000,
207 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
208 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
209 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
210 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
211 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
212 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
213 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
214 .emif_rd_wr_lvl_rmp_win = 0x00000000,
215 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
216 .emif_rd_wr_lvl_ctl = 0x00000000,
217 .emif_rd_wr_exec_thresh = 0x00000305
218};
219
220const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
221 .sdram_config_init = 0x61862B32,
222 .sdram_config = 0x61862B32,
223 .sdram_config2 = 0x00000000,
224 .ref_ctrl = 0x0000514C,
225 .ref_ctrl_final = 0x0000144A,
226 .sdram_tim1 = 0xD113783C,
227 .sdram_tim2 = 0x30B47FE3,
228 .sdram_tim3 = 0x409F8AD8,
229 .read_idle_ctrl = 0x00050000,
230 .zq_config = 0x5007190B,
231 .temp_alert_config = 0x00000000,
232 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
233 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
234 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
235 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
236 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
237 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
238 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
239 .emif_rd_wr_lvl_rmp_win = 0x00000000,
240 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
241 .emif_rd_wr_lvl_ctl = 0x00000000,
242 .emif_rd_wr_exec_thresh = 0x00000305
243};
244
245const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
246 .sdram_config_init = 0x61862B32,
247 .sdram_config = 0x61862B32,
248 .sdram_config2 = 0x00000000,
249 .ref_ctrl = 0x0000514C,
250 .ref_ctrl_final = 0x0000144A,
251 .sdram_tim1 = 0xD113781C,
252 .sdram_tim2 = 0x30B47FE3,
253 .sdram_tim3 = 0x409F8AD8,
254 .read_idle_ctrl = 0x00050000,
255 .zq_config = 0x5007190B,
256 .temp_alert_config = 0x00000000,
257 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
258 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
259 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
260 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
261 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
262 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
263 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
264 .emif_rd_wr_lvl_rmp_win = 0x00000000,
265 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
266 .emif_rd_wr_lvl_ctl = 0x00000000,
267 .emif_rd_wr_exec_thresh = 0x00000305
268};
269
270void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
271{
272 u64 ram_size;
273
274 ram_size = board_ti_get_emif_size();
275
276 switch (omap_revision()) {
277 case DRA752_ES1_0:
278 case DRA752_ES1_1:
279 case DRA752_ES2_0:
280 switch (emif_nr) {
281 case 1:
282 if (ram_size > CONFIG_MAX_MEM_MAPPED)
283 *regs = &emif1_ddr3_532_mhz_1cs_2G;
284 else
285 *regs = &emif1_ddr3_532_mhz_1cs;
286 break;
287 case 2:
288 if (ram_size > CONFIG_MAX_MEM_MAPPED)
289 *regs = &emif2_ddr3_532_mhz_1cs_2G;
290 else
291 *regs = &emif2_ddr3_532_mhz_1cs;
292 break;
293 }
294 break;
295 case DRA762_ABZ_ES1_0:
296 case DRA762_ACD_ES1_0:
297 case DRA762_ES1_0:
298 if (emif_nr == 1)
299 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
300 else
301 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
302 break;
303 case DRA722_ES1_0:
304 case DRA722_ES2_0:
305 case DRA722_ES2_1:
306 if (ram_size < CONFIG_MAX_MEM_MAPPED)
307 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
308 else
309 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
310 break;
311 default:
312 *regs = &emif1_ddr3_532_mhz_1cs;
313 }
314}
315
316static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
317 .dmm_lisa_map_0 = 0x0,
318 .dmm_lisa_map_1 = 0x80640300,
319 .dmm_lisa_map_2 = 0xC0500220,
320 .dmm_lisa_map_3 = 0xFF020100,
321 .is_ma_present = 0x1
322};
323
324static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
325 .dmm_lisa_map_0 = 0x0,
326 .dmm_lisa_map_1 = 0x0,
327 .dmm_lisa_map_2 = 0x80600100,
328 .dmm_lisa_map_3 = 0xFF020100,
329 .is_ma_present = 0x1
330};
331
332const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
333 .dmm_lisa_map_0 = 0x0,
334 .dmm_lisa_map_1 = 0x0,
335 .dmm_lisa_map_2 = 0x80740300,
336 .dmm_lisa_map_3 = 0xFF020100,
337 .is_ma_present = 0x1
338};
339
340
341
342
343
344const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
345 .dmm_lisa_map_0 = 0x0,
346 .dmm_lisa_map_1 = 0x0,
347 .dmm_lisa_map_2 = 0x80700100,
348 .dmm_lisa_map_3 = 0xFF020100,
349 .is_ma_present = 0x1
350};
351
352void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
353{
354 u64 ram_size;
355
356 ram_size = board_ti_get_emif_size();
357
358 switch (omap_revision()) {
359 case DRA762_ABZ_ES1_0:
360 case DRA762_ACD_ES1_0:
361 case DRA762_ES1_0:
362 case DRA752_ES1_0:
363 case DRA752_ES1_1:
364 case DRA752_ES2_0:
365 if (ram_size > CONFIG_MAX_MEM_MAPPED)
366 *dmm_lisa_regs = &lisa_map_dra7_2GB;
367 else
368 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
369 break;
370 case DRA722_ES1_0:
371 case DRA722_ES2_0:
372 case DRA722_ES2_1:
373 default:
374 if (ram_size < CONFIG_MAX_MEM_MAPPED)
375 *dmm_lisa_regs = &lisa_map_2G_x_2;
376 else
377 *dmm_lisa_regs = &lisa_map_2G_x_4;
378 break;
379 }
380}
381
382struct vcores_data dra752_volts = {
383 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
384 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
385 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
386 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
387 .mpu.pmic = &tps659038,
388 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
389
390 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
391 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
392 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
393 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
394 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
395 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
396 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
397 .eve.addr = TPS659038_REG_ADDR_SMPS45,
398 .eve.pmic = &tps659038,
399 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
400
401 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
402 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
403 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
404 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
405 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
406 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
407 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
408 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
409 .gpu.pmic = &tps659038,
410 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
411
412 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
413 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
414 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
415 .core.addr = TPS659038_REG_ADDR_SMPS7,
416 .core.pmic = &tps659038,
417
418 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
419 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
420 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
421 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
422 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
423 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
424 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
425 .iva.addr = TPS659038_REG_ADDR_SMPS8,
426 .iva.pmic = &tps659038,
427 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
428};
429
430struct vcores_data dra76x_volts = {
431 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
432 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
433 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
434 .mpu.addr = LP87565_REG_ADDR_BUCK01,
435 .mpu.pmic = &lp87565,
436 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
437
438 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
439 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
440 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
441 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
442 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
443 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
444 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
445 .eve.addr = TPS65917_REG_ADDR_SMPS1,
446 .eve.pmic = &tps659038,
447 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
448
449 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
450 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
451 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
452 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
453 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
454 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
455 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
456 .gpu.addr = LP87565_REG_ADDR_BUCK23,
457 .gpu.pmic = &lp87565,
458 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
459
460 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
461 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
462 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
463 .core.addr = TPS65917_REG_ADDR_SMPS3,
464 .core.pmic = &tps659038,
465
466 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
467 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
468 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
469 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
470 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
471 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
472 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
473 .iva.addr = TPS65917_REG_ADDR_SMPS4,
474 .iva.pmic = &tps659038,
475 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
476};
477
478struct vcores_data dra722_volts = {
479 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
480 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
481 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
482 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
483 .mpu.pmic = &tps659038,
484 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
485
486 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
487 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
488 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
489 .core.addr = TPS65917_REG_ADDR_SMPS2,
490 .core.pmic = &tps659038,
491
492
493
494
495
496 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
497 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
498 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
499 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
500 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
501 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
502 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
503 .gpu.addr = TPS65917_REG_ADDR_SMPS3,
504 .gpu.pmic = &tps659038,
505 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
506
507 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
508 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
509 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
510 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
511 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
512 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
513 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
514 .eve.addr = TPS65917_REG_ADDR_SMPS3,
515 .eve.pmic = &tps659038,
516 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
517
518 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
519 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
520 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
521 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
522 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
523 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
524 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
525 .iva.addr = TPS65917_REG_ADDR_SMPS3,
526 .iva.pmic = &tps659038,
527 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
528};
529
530struct vcores_data dra718_volts = {
531
532
533
534
535 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
536 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
537 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
538 .mpu.addr = LP873X_REG_ADDR_BUCK0,
539 .mpu.pmic = &lp8733,
540 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
541
542 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
543 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
544 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
545 .core.addr = LP873X_REG_ADDR_BUCK0,
546 .core.pmic = &lp8733,
547
548 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
549 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
550 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
551 .gpu.addr = LP873X_REG_ADDR_BUCK0,
552 .gpu.pmic = &lp8733,
553 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
554
555
556
557
558
559 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
560 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
561 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
562 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
563 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
564 .eve.addr = LP873X_REG_ADDR_BUCK1,
565 .eve.pmic = &lp8733,
566 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
567
568 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
569 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
570 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
571 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
572 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
573 .iva.addr = LP873X_REG_ADDR_BUCK1,
574 .iva.pmic = &lp8733,
575 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
576};
577
578int get_voltrail_opp(int rail_offset)
579{
580 int opp;
581
582 switch (rail_offset) {
583 case VOLT_MPU:
584 opp = DRA7_MPU_OPP;
585
586 if (board_is_dra71x_evm())
587 opp = OPP_NOM;
588 break;
589 case VOLT_CORE:
590 opp = DRA7_CORE_OPP;
591
592 if (board_is_dra71x_evm())
593 opp = OPP_NOM;
594 break;
595 case VOLT_GPU:
596 opp = DRA7_GPU_OPP;
597
598 if (board_is_dra71x_evm())
599 opp = OPP_NOM;
600 break;
601 case VOLT_EVE:
602 opp = DRA7_DSPEVE_OPP;
603
604
605
606
607
608 if (board_is_dra71x_evm() && opp == OPP_OD)
609 opp = OPP_NOM;
610 break;
611 case VOLT_IVA:
612 opp = DRA7_IVA_OPP;
613
614
615
616
617
618 if (board_is_dra71x_evm() && opp == OPP_OD)
619 opp = OPP_NOM;
620 break;
621 default:
622 opp = OPP_NOM;
623 }
624
625 return opp;
626}
627
628
629
630
631
632
633int board_init(void)
634{
635 gpmc_init();
636 gd->bd->bi_boot_params = (0x80000000 + 0x100);
637
638 return 0;
639}
640
641int dram_init_banksize(void)
642{
643 u64 ram_size;
644
645 ram_size = board_ti_get_emif_size();
646
647 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
648 gd->bd->bi_dram[0].size = get_effective_memsize();
649 if (ram_size > CONFIG_MAX_MEM_MAPPED) {
650 gd->bd->bi_dram[1].start = 0x200000000;
651 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
652 }
653
654 return 0;
655}
656
657#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
658static int device_okay(const char *path)
659{
660 int node;
661
662 node = fdt_path_offset(gd->fdt_blob, path);
663 if (node < 0)
664 return 0;
665
666 return fdtdec_get_is_enabled(gd->fdt_blob, node);
667}
668#endif
669
670int board_late_init(void)
671{
672#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
673 char *name = "unknown";
674
675 if (is_dra72x()) {
676 if (board_is_dra72x_revc_or_later())
677 name = "dra72x-revc";
678 else if (board_is_dra71x_evm())
679 name = "dra71x";
680 else
681 name = "dra72x";
682 } else if (is_dra76x_abz()) {
683 name = "dra76x_abz";
684 } else if (is_dra76x_acd()) {
685 name = "dra76x_acd";
686 } else {
687 name = "dra7xx";
688 }
689
690 set_board_info_env(name);
691
692
693
694
695
696 if (get_device_type() == HS_DEVICE)
697 env_set("boot_fit", "1");
698
699 omap_die_id_serial();
700 omap_set_fastboot_vars();
701
702
703
704
705
706 if (board_is_dra71x_evm())
707 palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
708#endif
709#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
710 if (device_okay("/ocp/omap_dwc3_1@48880000"))
711 enable_usb_clocks(0);
712 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
713 enable_usb_clocks(1);
714#endif
715 return 0;
716}
717
718#ifdef CONFIG_SPL_BUILD
719void do_board_detect(void)
720{
721 int rc;
722
723 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
724 CONFIG_EEPROM_CHIP_ADDRESS);
725 if (rc)
726 printf("ti_i2c_eeprom_init failed %d\n", rc);
727}
728
729#else
730
731void do_board_detect(void)
732{
733 char *bname = NULL;
734 int rc;
735
736 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
737 CONFIG_EEPROM_CHIP_ADDRESS);
738 if (rc)
739 printf("ti_i2c_eeprom_init failed %d\n", rc);
740
741 if (board_is_dra74x_evm()) {
742 bname = "DRA74x EVM";
743 } else if (board_is_dra72x_evm()) {
744 bname = "DRA72x EVM";
745 } else if (board_is_dra71x_evm()) {
746 bname = "DRA71x EVM";
747 } else if (board_is_dra76x_evm()) {
748 bname = "DRA76x EVM";
749 } else {
750
751 if (is_dra72x())
752 bname = "DRA72x EVM";
753 else
754 bname = "DRA74x EVM";
755 }
756
757 if (bname)
758 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
759 "Board: %s REV %s\n", bname, board_ti_get_rev());
760}
761#endif
762
763void vcores_init(void)
764{
765 if (board_is_dra74x_evm()) {
766 *omap_vcores = &dra752_volts;
767 } else if (board_is_dra72x_evm()) {
768 *omap_vcores = &dra722_volts;
769 } else if (board_is_dra71x_evm()) {
770 *omap_vcores = &dra718_volts;
771 } else if (board_is_dra76x_evm()) {
772 *omap_vcores = &dra76x_volts;
773 } else {
774
775 if (is_dra72x())
776 *omap_vcores = &dra722_volts;
777 else
778 *omap_vcores = &dra752_volts;
779 }
780}
781
782void set_muxconf_regs(void)
783{
784 do_set_mux32((*ctrl)->control_padconf_core_base,
785 early_padconf, ARRAY_SIZE(early_padconf));
786}
787
788#if defined(CONFIG_MTD_RAW_NAND)
789static int nand_sw_detect(void)
790{
791 int rc;
792 uchar data[2];
793 struct udevice *dev;
794
795 rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
796 NAND_PCF8575_ADDR, 0, &dev);
797 if (rc)
798 return -1;
799
800 rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
801 if (rc)
802 return -1;
803
804
805
806
807 data[1] = data[1] & 0x3;
808
809
810
811
812
813
814 if (data[1] == 0x2)
815 return 0;
816
817 return -1;
818}
819#else
820int nand_sw_detect(void)
821{
822 return -1;
823}
824#endif
825
826#ifdef CONFIG_IODELAY_RECALIBRATION
827void recalibrate_iodelay(void)
828{
829 struct pad_conf_entry const *pads, *delta_pads = NULL;
830 struct iodelay_cfg_entry const *iodelay;
831 int npads, niodelays, delta_npads = 0;
832 int ret;
833
834 switch (omap_revision()) {
835 case DRA722_ES1_0:
836 case DRA722_ES2_0:
837 case DRA722_ES2_1:
838 pads = dra72x_core_padconf_array_common;
839 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
840 if (board_is_dra71x_evm()) {
841 pads = dra71x_core_padconf_array;
842 npads = ARRAY_SIZE(dra71x_core_padconf_array);
843 iodelay = dra71_iodelay_cfg_array;
844 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
845
846
847
848 if (!nand_sw_detect()) {
849 delta_pads = dra71x_nand_padconf_array;
850 delta_npads =
851 ARRAY_SIZE(dra71x_nand_padconf_array);
852 } else {
853 delta_pads = dra71x_vout3_padconf_array;
854 delta_npads =
855 ARRAY_SIZE(dra71x_vout3_padconf_array);
856 }
857
858 } else if (board_is_dra72x_revc_or_later()) {
859 delta_pads = dra72x_rgmii_padconf_array_revc;
860 delta_npads =
861 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
862 iodelay = dra72_iodelay_cfg_array_revc;
863 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
864 } else {
865 delta_pads = dra72x_rgmii_padconf_array_revb;
866 delta_npads =
867 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
868 iodelay = dra72_iodelay_cfg_array_revb;
869 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
870 }
871 break;
872 case DRA752_ES1_0:
873 case DRA752_ES1_1:
874 pads = dra74x_core_padconf_array;
875 npads = ARRAY_SIZE(dra74x_core_padconf_array);
876 iodelay = dra742_es1_1_iodelay_cfg_array;
877 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
878 break;
879 case DRA762_ACD_ES1_0:
880 case DRA762_ES1_0:
881 pads = dra76x_core_padconf_array;
882 npads = ARRAY_SIZE(dra76x_core_padconf_array);
883 iodelay = dra76x_es1_0_iodelay_cfg_array;
884 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
885 break;
886 default:
887 case DRA752_ES2_0:
888 case DRA762_ABZ_ES1_0:
889 pads = dra74x_core_padconf_array;
890 npads = ARRAY_SIZE(dra74x_core_padconf_array);
891 iodelay = dra742_es2_0_iodelay_cfg_array;
892 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
893
894 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
895 RGMII1_ID_MODE_N_MASK);
896 break;
897 }
898
899 ret = __recalibrate_iodelay_start();
900 if (ret)
901 goto err;
902
903
904 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
905
906
907 if (delta_npads)
908 do_set_mux32((*ctrl)->control_padconf_core_base,
909 delta_pads, delta_npads);
910
911 if (is_dra76x())
912
913 clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
914 MCAN_SEL_ALT_MASK, MCAN_SEL);
915
916
917 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
918err:
919
920 __recalibrate_iodelay_end(ret);
921}
922#endif
923
924#if defined(CONFIG_MMC)
925int board_mmc_init(struct bd_info *bis)
926{
927 omap_mmc_init(0, 0, 0, -1, -1);
928 omap_mmc_init(1, 0, 0, -1, -1);
929 return 0;
930}
931
932void board_mmc_poweron_ldo(uint voltage)
933{
934 if (board_is_dra71x_evm()) {
935 if (voltage == LDO_VOLT_3V0)
936 voltage = 0x19;
937 else if (voltage == LDO_VOLT_1V8)
938 voltage = 0xa;
939 lp873x_mmc1_poweron_ldo(voltage);
940 } else if (board_is_dra76x_evm()) {
941 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
942 } else {
943 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
944 }
945}
946
947static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
948 .hw_rev = "rev11",
949 .unsupported_caps = MMC_CAP(MMC_HS_200) |
950 MMC_CAP(UHS_SDR104),
951 .max_freq = 96000000,
952};
953
954static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
955 .hw_rev = "rev11",
956 .unsupported_caps = MMC_CAP(MMC_HS_200) |
957 MMC_CAP(UHS_SDR104) |
958 MMC_CAP(UHS_SDR50),
959 .max_freq = 48000000,
960};
961
962const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
963{
964 switch (omap_revision()) {
965 case DRA752_ES1_0:
966 case DRA752_ES1_1:
967 if (addr == OMAP_HSMMC1_BASE)
968 return &dra7x_es1_1_mmc1_fixups;
969 else
970 return &dra7x_es1_1_mmc23_fixups;
971 default:
972 return NULL;
973 }
974}
975#endif
976
977#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
978int spl_start_uboot(void)
979{
980
981 if (serial_tstc() && serial_getc() == 'c')
982 return 1;
983
984#ifdef CONFIG_SPL_ENV_SUPPORT
985 env_init();
986 env_load();
987 if (env_get_yesno("boot_os") != 1)
988 return 1;
989#endif
990
991 return 0;
992}
993#endif
994
995#ifdef CONFIG_BOARD_EARLY_INIT_F
996
997static inline void vtt_regulator_enable(void)
998{
999 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1000 return;
1001
1002
1003 if (is_dra72x() || is_dra76x())
1004 return;
1005
1006
1007
1008
1009
1010 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1011 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1012}
1013
1014int board_early_init_f(void)
1015{
1016 vtt_regulator_enable();
1017 return 0;
1018}
1019#endif
1020
1021#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1022int ft_board_setup(void *blob, struct bd_info *bd)
1023{
1024 ft_cpu_setup(blob, bd);
1025
1026 return 0;
1027}
1028#endif
1029
1030#ifdef CONFIG_SPL_LOAD_FIT
1031int board_fit_config_name_match(const char *name)
1032{
1033 if (is_dra72x()) {
1034 if (board_is_dra71x_evm()) {
1035 if (!strcmp(name, "dra71-evm"))
1036 return 0;
1037 }else if(board_is_dra72x_revc_or_later()) {
1038 if (!strcmp(name, "dra72-evm-revc"))
1039 return 0;
1040 } else if (!strcmp(name, "dra72-evm")) {
1041 return 0;
1042 }
1043 } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
1044 return 0;
1045 } else if (!is_dra72x() && !is_dra76x_acd() &&
1046 !strcmp(name, "dra7-evm")) {
1047 return 0;
1048 }
1049
1050 return -1;
1051}
1052#endif
1053
1054#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1055int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
1056{
1057 if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
1058 return -ENOTSUPP;
1059
1060 printf("Setting reboot to fastboot flag ...\n");
1061 env_set("dofastboot", "1");
1062 env_save();
1063 return 0;
1064}
1065#endif
1066
1067#ifdef CONFIG_TI_SECURE_DEVICE
1068void board_fit_image_post_process(const void *fit, int node, void **p_image,
1069 size_t *p_size)
1070{
1071 secure_boot_verify_image(p_image, p_size);
1072}
1073
1074void board_tee_image_process(ulong tee_image, size_t tee_size)
1075{
1076 secure_tee_install((u32)tee_image);
1077}
1078
1079U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1080#endif
1081
