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8#include <common.h>
9#include <eeprom.h>
10#include <env.h>
11#include <hang.h>
12#include <image.h>
13#include <init.h>
14#include <asm/arch/clock.h>
15#include <asm/ti-common/keystone_net.h>
16#include <asm/arch/psc_defs.h>
17#include <asm/arch/mmc_host_def.h>
18#include <fdtdec.h>
19#include <i2c.h>
20#include <remoteproc.h>
21#include <linux/bitops.h>
22#include <linux/delay.h>
23#include "mux-k2g.h"
24#include "../common/board_detect.h"
25
26#define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
27
28const unsigned int sysclk_array[MAX_SYSCLK] = {
29 19200000,
30 24000000,
31 25000000,
32 26000000,
33};
34
35unsigned int get_external_clk(u32 clk)
36{
37 unsigned int clk_freq;
38 u8 sysclk_index = get_sysclk_index();
39
40 switch (clk) {
41 case sys_clk:
42 clk_freq = sysclk_array[sysclk_index];
43 break;
44 case pa_clk:
45 clk_freq = sysclk_array[sysclk_index];
46 break;
47 case tetris_clk:
48 clk_freq = sysclk_array[sysclk_index];
49 break;
50 case ddr3a_clk:
51 clk_freq = sysclk_array[sysclk_index];
52 break;
53 case uart_clk:
54 clk_freq = sysclk_array[sysclk_index];
55 break;
56 default:
57 clk_freq = 0;
58 break;
59 }
60
61 return clk_freq;
62}
63
64int speeds[DEVSPEED_NUMSPDS] = {
65 SPD400,
66 SPD600,
67 SPD800,
68 SPD900,
69 SPD1000,
70 SPD900,
71 SPD800,
72 SPD600,
73 SPD400,
74 SPD200,
75};
76
77static int dev_speeds[DEVSPEED_NUMSPDS] = {
78 SPD600,
79 SPD800,
80 SPD900,
81 SPD1000,
82 SPD900,
83 SPD800,
84 SPD600,
85 SPD400,
86};
87
88static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
89 [SYSCLK_19MHz] = {
90 [SPD400] = {MAIN_PLL, 125, 3, 2},
91 [SPD600] = {MAIN_PLL, 125, 2, 2},
92 [SPD800] = {MAIN_PLL, 250, 3, 2},
93 [SPD900] = {MAIN_PLL, 187, 2, 2},
94 [SPD1000] = {MAIN_PLL, 104, 1, 2},
95 },
96 [SYSCLK_24MHz] = {
97 [SPD400] = {MAIN_PLL, 100, 3, 2},
98 [SPD600] = {MAIN_PLL, 300, 6, 2},
99 [SPD800] = {MAIN_PLL, 200, 3, 2},
100 [SPD900] = {MAIN_PLL, 75, 1, 2},
101 [SPD1000] = {MAIN_PLL, 250, 3, 2},
102 },
103 [SYSCLK_25MHz] = {
104 [SPD400] = {MAIN_PLL, 32, 1, 2},
105 [SPD600] = {MAIN_PLL, 48, 1, 2},
106 [SPD800] = {MAIN_PLL, 64, 1, 2},
107 [SPD900] = {MAIN_PLL, 72, 1, 2},
108 [SPD1000] = {MAIN_PLL, 80, 1, 2},
109 },
110 [SYSCLK_26MHz] = {
111 [SPD400] = {MAIN_PLL, 400, 13, 2},
112 [SPD600] = {MAIN_PLL, 230, 5, 2},
113 [SPD800] = {MAIN_PLL, 123, 2, 2},
114 [SPD900] = {MAIN_PLL, 69, 1, 2},
115 [SPD1000] = {MAIN_PLL, 384, 5, 2},
116 },
117};
118
119static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
120 [SYSCLK_19MHz] = {
121 [SPD200] = {TETRIS_PLL, 625, 6, 10},
122 [SPD400] = {TETRIS_PLL, 125, 1, 6},
123 [SPD600] = {TETRIS_PLL, 125, 1, 4},
124 [SPD800] = {TETRIS_PLL, 333, 2, 4},
125 [SPD900] = {TETRIS_PLL, 187, 2, 2},
126 [SPD1000] = {TETRIS_PLL, 104, 1, 2},
127 },
128 [SYSCLK_24MHz] = {
129 [SPD200] = {TETRIS_PLL, 250, 3, 10},
130 [SPD400] = {TETRIS_PLL, 100, 1, 6},
131 [SPD600] = {TETRIS_PLL, 100, 1, 4},
132 [SPD800] = {TETRIS_PLL, 400, 3, 4},
133 [SPD900] = {TETRIS_PLL, 75, 1, 2},
134 [SPD1000] = {TETRIS_PLL, 250, 3, 2},
135 },
136 [SYSCLK_25MHz] = {
137 [SPD200] = {TETRIS_PLL, 80, 1, 10},
138 [SPD400] = {TETRIS_PLL, 96, 1, 6},
139 [SPD600] = {TETRIS_PLL, 96, 1, 4},
140 [SPD800] = {TETRIS_PLL, 128, 1, 4},
141 [SPD900] = {TETRIS_PLL, 72, 1, 2},
142 [SPD1000] = {TETRIS_PLL, 80, 1, 2},
143 },
144 [SYSCLK_26MHz] = {
145 [SPD200] = {TETRIS_PLL, 307, 4, 10},
146 [SPD400] = {TETRIS_PLL, 369, 4, 6},
147 [SPD600] = {TETRIS_PLL, 369, 4, 4},
148 [SPD800] = {TETRIS_PLL, 123, 1, 4},
149 [SPD900] = {TETRIS_PLL, 69, 1, 2},
150 [SPD1000] = {TETRIS_PLL, 384, 5, 2},
151 },
152};
153
154static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
155 [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
156 [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
157 [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
158 [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
159};
160
161static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
162 [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
163 [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
164 [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
165 [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
166};
167
168static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
169 [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
170 [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
171 [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
172 [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
173};
174
175static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
176 [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
177 [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
178 [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
179 [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
180};
181
182struct pll_init_data *get_pll_init_data(int pll)
183{
184 int speed;
185 struct pll_init_data *data = NULL;
186 u8 sysclk_index = get_sysclk_index();
187
188 switch (pll) {
189 case MAIN_PLL:
190 speed = get_max_dev_speed(dev_speeds);
191 data = &main_pll_config[sysclk_index][speed];
192 break;
193 case TETRIS_PLL:
194 speed = get_max_arm_speed(speeds);
195 data = &tetris_pll_config[sysclk_index][speed];
196 break;
197 case NSS_PLL:
198 data = &nss_pll_config[sysclk_index];
199 break;
200 case UART_PLL:
201 data = &uart_pll_config[sysclk_index];
202 break;
203 case DDR3_PLL:
204 if (cpu_revision() & CPU_66AK2G1x) {
205 speed = get_max_arm_speed(speeds);
206 if (speed == SPD1000)
207 data = &ddr3_pll_config_1066[sysclk_index];
208 else
209 data = &ddr3_pll_config_800[sysclk_index];
210 } else {
211 data = &ddr3_pll_config_800[sysclk_index];
212 }
213 break;
214 default:
215 data = NULL;
216 }
217
218 return data;
219}
220
221s16 divn_val[16] = {
222 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
223};
224
225#if defined(CONFIG_MMC)
226int board_mmc_init(struct bd_info *bis)
227{
228 if (psc_enable_module(KS2_LPSC_MMC)) {
229 printf("%s module enabled failed\n", __func__);
230 return -1;
231 }
232
233 if (board_is_k2g_gp() || board_is_k2g_g1())
234 omap_mmc_init(0, 0, 0, -1, -1);
235
236 omap_mmc_init(1, 0, 0, -1, -1);
237 return 0;
238}
239#endif
240
241#if defined(CONFIG_MULTI_DTB_FIT)
242int board_fit_config_name_match(const char *name)
243{
244 bool eeprom_read = board_ti_was_eeprom_read();
245
246 if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
247 return 0;
248 else if (!strcmp(name, "keystone-k2g-evm") &&
249 (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
250 return 0;
251 else if (!strcmp(name, "keystone-k2g-ice") &&
252 (board_ti_is("66AK2GIC") || board_is_k2g_i1()))
253 return 0;
254 else
255 return -1;
256}
257#endif
258
259#if defined(CONFIG_DTB_RESELECT)
260static int k2g_alt_board_detect(void)
261{
262#if !CONFIG_IS_ENABLED(DM_I2C)
263 int rc;
264
265 rc = i2c_set_bus_num(1);
266 if (rc)
267 return rc;
268
269 rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
270 if (rc)
271 return rc;
272#else
273 struct udevice *bus, *dev;
274 int rc;
275
276 rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
277 if (rc)
278 return rc;
279 rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
280 if (rc)
281 return rc;
282#endif
283 ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
284
285 return 0;
286}
287
288static void k2g_reset_mux_config(void)
289{
290
291 clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
292
293
294 clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
295 RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
296
297
298 setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
299}
300
301int embedded_dtb_select(void)
302{
303 int rc;
304 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
305 CONFIG_EEPROM_CHIP_ADDRESS);
306 if (rc) {
307 rc = k2g_alt_board_detect();
308 if (rc) {
309 printf("Unable to do board detection\n");
310 return -1;
311 }
312 }
313
314 fdtdec_setup();
315
316 k2g_mux_config();
317
318 k2g_reset_mux_config();
319
320 if (board_is_k2g_gp() || board_is_k2g_g1()) {
321
322 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
323 BIT(9));
324 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
325 BIT(9));
326 } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
327
328
329
330
331
332
333 clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
334 BIT(10));
335 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
336 BIT(10));
337
338 udelay(100);
339 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
340 BIT(10));
341 }
342
343 return 0;
344}
345#endif
346
347#ifdef CONFIG_BOARD_LATE_INIT
348int board_late_init(void)
349{
350#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
351 int rc;
352
353 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
354 CONFIG_EEPROM_CHIP_ADDRESS);
355 if (rc)
356 printf("ti_i2c_eeprom_init failed %d\n", rc);
357
358 board_ti_set_ethaddr(1);
359#endif
360
361#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
362 if (board_is_k2g_gp())
363 env_set("board_name", "66AK2GGP\0");
364 else if (board_is_k2g_g1())
365 env_set("board_name", "66AK2GG1\0");
366 else if (board_is_k2g_ice())
367 env_set("board_name", "66AK2GIC\0");
368 else if (board_is_k2g_i1())
369 env_set("board_name", "66AK2GI1\0");
370#endif
371 return 0;
372}
373#endif
374
375#ifdef CONFIG_BOARD_EARLY_INIT_F
376int board_early_init_f(void)
377{
378 init_plls();
379
380 k2g_mux_config();
381
382 return 0;
383}
384#endif
385
386#ifdef CONFIG_SPL_BUILD
387void spl_init_keystone_plls(void)
388{
389 init_plls();
390}
391#endif
392
393#ifdef CONFIG_TI_SECURE_DEVICE
394void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
395{
396 int id = env_get_ulong("dev_pmmc", 10, 0);
397 int ret;
398
399 if (!rproc_is_initialized())
400 rproc_init();
401
402 ret = rproc_load(id, pmmc_image, pmmc_size);
403 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
404 id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
405
406 if (!ret)
407 rproc_start(id);
408}
409
410U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
411#endif
412
