LXR uboot/board/ti/ks2_evm/ddr3

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Keystone2: DDR3 initialization
   4 *
   5 * (C) Copyright 2014-2015
   6 *     Texas Instruments Incorporated, <www.ti.com>
   7 */
   8
   9#include <common.h>
  10#include "ddr3_cfg.h"
  11#include <asm/arch/ddr3.h>
  12
  13static struct pll_init_data ddr3_400 = DDR3_PLL_400;
  14static struct pll_init_data ddr3_333 = DDR3_PLL_333;
  15
  16u32 ddr3_init(void)
  17{
  18        struct ddr3_spd_cb spd_cb;
  19
  20        if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
  21                printf("Sorry, I don't know how to configure DDR3A.\n"
  22                       "Bye :(\n");
  23                for (;;)
  24                        ;
  25        }
  26
  27        printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
  28
  29        printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
  30        if (spd_cb.ddrspdclock == 1600)
  31                init_pll(&ddr3_400);
  32        else
  33                init_pll(&ddr3_333);
  34
  35        /* Reset DDR3 PHY after PLL enabled */
  36        ddr3_reset_ddrphy();
  37
  38        spd_cb.phy_cfg.zq0cr1 |= 0x10000;
  39        spd_cb.phy_cfg.zq1cr1 |= 0x10000;
  40        spd_cb.phy_cfg.zq2cr1 |= 0x10000;
  41        ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
  42        ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
  43
  44        printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
  45
  46        return (u32)spd_cb.ddr_size_gbyte;
  47}
  48