LXR uboot/board/ti/ks2

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * K2G EVM: Pinmux configuration
   4 *
   5 * (C) Copyright 2015
   6 *     Texas Instruments Incorporated, <www.ti.com>
   7 */
   8
   9#include <common.h>
  10#include <hang.h>
  11#include <asm/io.h>
  12#include <asm/arch/mux-k2g.h>
  13#include <asm/arch/hardware.h>
  14#include "board.h"
  15
  16struct pin_cfg k2g_generic_pin_cfg[] = {
  17        /* UART0 */
  18        { 115,  MODE(0) },      /* SOC_UART0_RXD */
  19        { 116,  MODE(0) },      /* SOC_UART0_TXD */
  20
  21        /* I2C 0 */
  22        { 223,  MODE(0) },      /* SOC_I2C0_SCL */
  23        { 224,  MODE(0) },      /* SOC_I2C0_SDA */
  24
  25        /* I2C 1 */
  26        { 225,  MODE(0) },      /* SOC_I2C1_SCL */
  27        { 226,  MODE(0) },      /* SOC_I2C1_SDA */
  28        { MAX_PIN_N, }
  29};
  30
  31struct pin_cfg k2g_evm_pin_cfg[] = {
  32        /* GPMC */
  33        { 0,    MODE(0) },      /* GPMCAD0 */
  34        { 1,    MODE(0) },      /* GPMCAD1 */
  35        { 2,    MODE(0) },      /* GPMCAD2 */
  36        { 3,    MODE(0) },      /* GPMCAD3 */
  37        { 4,    MODE(0) },      /* GPMCAD4 */
  38        { 5,    MODE(0) },      /* GPMCAD5 */
  39        { 6,    MODE(0) },      /* GPMCAD6 */
  40        { 7,    MODE(0) },      /* GPMCAD7 */
  41        { 8,    MODE(0) },      /* GPMCAD8 */
  42        { 9,    MODE(0) },      /* GPMCAD9 */
  43        { 10,   MODE(0) },      /* GPMCAD10 */
  44        { 11,   MODE(0) },      /* GPMCAD11 */
  45        { 12,   MODE(0) },      /* GPMCAD12 */
  46        { 13,   MODE(0) },      /* GPMCAD13 */
  47        { 14,   MODE(0) },      /* GPMCAD14 */
  48        { 15,   MODE(0) },      /* GPMCAD15 */
  49        { 17,   MODE(0) },      /* GPMCADVNALE */
  50        { 18,   MODE(0) },      /* GPMCOENREN */
  51        { 19,   MODE(0) },      /* GPMCWEN */
  52        { 20,   MODE(0) },      /* GPMCBE0NCLE */
  53        { 22,   MODE(0) },      /* GPMCWAIT0 */
  54        { 24,   MODE(0) },      /* GPMCWPN */
  55        { 26,   MODE(0) },      /* GPMCCSN0 */
  56
  57        /* GPIOs */
  58        { 16,   MODE(3) | PIN_IEN },    /* GPIO0_16 - PRSNT1# */
  59        { 21,   MODE(3) | PIN_IEN },    /* GPIO0_21 - DC_BRD_DET */
  60        { 82,   MODE(3) | PIN_IEN },    /* GPIO0_82 - TPS_INT1 */
  61        { 83,   MODE(3) },              /* GPIO0_83 - TPS_SLEEP */
  62        { 84,   MODE(3) },              /* GPIO0_84 - SEL_HDMIn_GPIO */
  63        { 87,   MODE(3) },              /* GPIO0_87 - SD_LP2996A */
  64        { 106,  MODE(3) | PIN_IEN},     /* GPIO0_100 - SOC_INT */
  65        { 201,  MODE(3) | PIN_IEN},     /* GPIO1_26 - GPIO_EXP_INT */
  66        { 202,  MODE(3) },              /* GPIO1_27 - SEL_LCDn_GPIO */
  67        { 203,  MODE(3) | PIN_IEN},     /* GPIO1_28 - SOC_MLB_GPIO2 */
  68        { 204,  MODE(3) | PIN_IEN},     /* GPIO1_29 - SOC_PCIE_WAKEn */
  69        { 205,  MODE(3) | PIN_IEN},     /* GPIO1_30 - BMC_INT1 */
  70        { 206,  MODE(3) | PIN_IEN},     /* GPIO1_31 - HDMI_INTn*/
  71        { 207,  MODE(3) | PIN_IEN},     /* GPIO1_32 - CS2000_AUX_OUT */
  72        { 208,  MODE(3) | PIN_IEN},     /* GPIO1_33 - TEMP_INT */
  73        { 209,  MODE(3) | PIN_IEN},     /* GPIO1_34 - WLAN_IRQ */
  74        { 216,  MODE(3) },              /* GPIO1_41 - FLASH_HOLD */
  75        { 217,  MODE(3) | PIN_IEN},     /* GPIO1_42 - TOUCH_INTn */
  76
  77        /* MLB */
  78        { 23,   MODE(2) },      /* SOC_MLBCLK */
  79        { 25,   MODE(2) },      /* SOC_MLBSIG */
  80        { 27,   MODE(2) },      /* SOC_MLBDAT */
  81
  82        /* DSS */
  83        { 30,   MODE(0) },      /* SOC_DSSDATA23 */
  84        { 31,   MODE(0) },      /* SOC_DSSDATA22 */
  85        { 32,   MODE(0) },      /* SOC_DSSDATA21 */
  86        { 33,   MODE(0) },      /* SOC_DSSDATA20 */
  87        { 34,   MODE(0) },      /* SOC_DSSDATA19 */
  88        { 35,   MODE(0) },      /* SOC_DSSDATA18 */
  89        { 36,   MODE(0) },      /* SOC_DSSDATA17 */
  90        { 37,   MODE(0) },      /* SOC_DSSDATA16 */
  91        { 38,   MODE(0) },      /* SOC_DSSDATA15 */
  92        { 39,   MODE(0) },      /* SOC_DSSDATA14 */
  93        { 40,   MODE(0) },      /* SOC_DSSDATA13 */
  94        { 41,   MODE(0) },      /* SOC_DSSDATA12 */
  95        { 42,   MODE(0) },      /* SOC_DSSDATA11 */
  96        { 43,   MODE(0) },      /* SOC_DSSDATA10 */
  97        { 44,   MODE(0) },      /* SOC_DSSDATA9 */
  98        { 45,   MODE(0) },      /* SOC_DSSDATA8 */
  99        { 46,   MODE(0) },      /* SOC_DSSDATA7 */
 100        { 47,   MODE(0) },      /* SOC_DSSDATA6 */
 101        { 48,   MODE(0) },      /* SOC_DSSDATA5 */
 102        { 49,   MODE(0) },      /* SOC_DSSDATA4 */
 103        { 50,   MODE(0) },      /* SOC_DSSDATA3 */
 104        { 51,   MODE(0) },      /* SOC_DSSDATA2 */
 105        { 52,   MODE(0) },      /* SOC_DSSDATA1 */
 106        { 53,   MODE(0) },      /* SOC_DSSDATA0 */
 107        { 54,   MODE(0) },      /* SOC_DSSVSYNC */
 108        { 55,   MODE(0) },      /* SOC_DSSHSYNC */
 109        { 56,   MODE(0) },      /* SOC_DSSPCLK */
 110        { 57,   MODE(0) },      /* SOC_DSS_DE */
 111        { 58,   MODE(0) },      /* SOC_DSS_FID */
 112        { 221,  MODE(4) },      /* PWM0 - SOC_BACKLIGHT_PWM */
 113
 114        /* MMC1 */
 115        { 59,   MODE(0) },      /* SOC_MMC1_DAT7 */
 116        { 60,   MODE(0) },      /* SOC_MMC1_DAT6 */
 117        { 61,   MODE(0) },      /* SOC_MMC1_DAT5 */
 118        { 62,   MODE(0) },      /* SOC_MMC1_DAT4 */
 119        { 63,   MODE(0) },      /* SOC_MMC1_DAT3 */
 120        { 64,   MODE(0) },      /* SOC_MMC1_DAT2 */
 121        { 65,   MODE(0) },      /* SOC_MMC1_DAT1 */
 122        { 66,   MODE(0) },      /* SOC_MMC1_DAT0 */
 123        { 67,   MODE(0) },      /* SOC_MMC1_CLK */
 124        { 68,   MODE(0) },      /* SOC_MMC1_CMD */
 125        { 69,   MODE(0) },      /* MMC1SDCD TP125 */
 126        { 70,   MODE(0) },      /* SOC_MMC1_SDWP */
 127        { 71,   MODE(0) },      /* MMC1POW TP124 */
 128
 129                /* EMAC */
 130        { 72,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXC */
 131        { 77,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD3 */
 132        { 78,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD2 */
 133        { 79,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD1 */
 134        { 80,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD0 */
 135        { 81,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXCTL */
 136        { 85,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXC */
 137        { 91,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD3 */
 138        { 92,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD2 */
 139        { 93,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD1 */
 140        { 94,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD0 */
 141        { 95,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXCTL */
 142
 143        /* MDIO */
 144        { 98,   BUFFER_CLASS_B | PIN_PDIS | MODE(0) },  /* MDIO_DATA */
 145        { 99,   BUFFER_CLASS_B | PIN_PDIS | MODE(0) },  /* MDIO_CLK */
 146
 147        /* PWM */
 148        { 73,   MODE(4) },      /* SOC_EHRPWM3A */
 149        { 74,   MODE(4) },      /* SOC_EHRPWM3B */
 150        { 75,   MODE(4) },      /* SOC_EHRPWM3_SYNCI */
 151        { 76,   MODE(4) },      /* SOC_EHRPWM3_SYNCO */
 152        { 96,   MODE(4) },      /* SOC_EHRPWM_TRIPZONE_INPUT3 */
 153        { 198,  MODE(4) },      /* SOC_EHRPWM_TRIPZONE_INPUT4 */
 154        { 199,  MODE(4) },      /* SOC_EHRPWM4A */
 155        { 200,  MODE(4) },      /* SOC_EHRPWM4B */
 156        { 218,  MODE(4) },      /* SOC_EHRPWM_TRIPZONE_INPUT5 */
 157        { 219,  MODE(4) },      /* SOC_EHRPWM5A */
 158        { 220,  MODE(4) },      /* SOC_EHRPWM5B */
 159        { 222,  MODE(4) },      /* SOC_ECAP1_IN_PWM1_OUT */
 160
 161        /* SPI3 */
 162        { 86,   MODE(1) },      /* SOC_SPI3_SCS0 */
 163        { 88,   MODE(1) },      /* SOC_SPI3_CLK */
 164        { 89,   MODE(1) },      /* SOC_SPI3_MISO */
 165        { 90,   MODE(1) },      /* SOC_SPI3_MOSI */
 166
 167        /* CLK */
 168        { 97,   MODE(0) },      /* SMD - TP132 */
 169
 170        /* SPI0 */
 171        { 100,  MODE(0) },      /* SOC_SPI0_SCS0 */
 172        { 101,  MODE(0) },      /* SOC_SPI0_SCS1 */
 173        { 102,  MODE(0) },      /* SOC_SPI0_CLK */
 174        { 103,  MODE(0) },      /* SOC_SPI0_MISO */
 175        { 104,  MODE(0) },      /* SOC_SPI0_MOSI */
 176
 177        /* SPI1 NORFLASH */
 178        { 105,  MODE(0) },      /* SOC_SPI1_SCS0 */
 179        { 107,  MODE(0) },      /* SOC_SPI1_CLK */
 180        { 108,  MODE(0) },      /* SOC_SPI1_MISO */
 181        { 109,  MODE(0) },      /* SOC_SPI1_MOSI */
 182
 183        /* SPI2 */
 184        { 110,  MODE(0) },      /* SOC_SPI2_SCS0 */
 185        { 111,  MODE(1) },      /* SOC_HOUT */
 186        { 112,  MODE(0) },      /* SOC_SPI2_CLK */
 187        { 113,  MODE(0) },      /* SOC_SPI2_MISO */
 188        { 114,  MODE(0) },      /* SOC_SPI2_MOSI */
 189
 190        /* UART0 */
 191        { 115,  MODE(0) },      /* SOC_UART0_RXD */
 192        { 116,  MODE(0) },      /* SOC_UART0_TXD */
 193        { 117,  MODE(0) },      /* SOC_UART0_CTSn */
 194        { 118,  MODE(0) },      /* SOC_UART0_RTSn */
 195
 196        /* UART1 */
 197        { 119,  MODE(0) },      /* SOC_UART1_RXD */
 198        { 120,  MODE(0) },      /* SOC_UART1_TXD */
 199        { 121,  MODE(0) },      /* SOC_UART1_CTSn */
 200        { 122,  MODE(0) },      /* SOC_UART1_RTSn */
 201
 202        /* UART2 */
 203        { 123,  MODE(0) },      /* SOC_UART2_RXD */
 204        { 124,  MODE(0) },      /* SOC_UART2_TXD */
 205        { 125,  MODE(0) },      /* UART0_TXVR_EN */
 206        { 126,  MODE(4) },      /* SOC_CPTS_TS_COMP */
 207
 208        /* DCAN */
 209        { 127,  MODE(0) },      /* SOC_DCAN0_TX */
 210        { 128,  MODE(0) },      /* SOC_DCAN0_RX */
 211        { 137,  MODE(1) },      /* SOC_DCAN1_TX */
 212        { 138,  MODE(1) },      /* SOC_DCAN1_RX */
 213
 214        /* QSPI */
 215        { 129,  MODE(0) },      /* SOC_QSPI_CLK */
 216        { 130,  MODE(0) },      /* SOC_QSPI_RTCLK */
 217        { 131,  MODE(0) },      /* SOC_QSPI_D0 */
 218        { 132,  MODE(0) },      /* SOC_QSPI_D1 */
 219        { 133,  MODE(0) },      /* SOC_QSPI_D2 */
 220        { 134,  MODE(0) },      /* SOC_QSPI_D3 */
 221        { 135,  MODE(0) },      /* SOC_QSPI_CSN0 */
 222        { 136,  MODE(1) },      /* DNI <-> WLAN_SLOW_CLK */
 223
 224        /* MCASP2 */
 225        { 139,  MODE(3) },      /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */
 226        { 140,  MODE(4) },      /* SOC_MCASP2AXR1 */
 227        { 141,  MODE(4) },      /* SOC_MCASP2AXR2 */
 228        { 142,  MODE(4) },      /* SOC_MCASP2AXR3 */
 229        { 143,  MODE(4) },      /* SOC_MCASP2AXR4 */
 230        { 144,  MODE(4) },      /* SOC_MCASP2AXR5 */
 231        { 145,  MODE(4) },      /* SOC_McASP2ACLKR */
 232        { 146,  MODE(4) },      /* SOC_McASP2FSR */
 233        { 147,  MODE(4) },      /* SOC_McASP2AHCLKR */
 234        { 148,  MODE(3) },      /* GPIO0_117 - WLAN_TRANS_EN */
 235        { 149,  MODE(4) },      /* SOC_McASP2FSX */
 236        { 150,  MODE(4) },      /* SOC_McASP2AHCLKX */
 237        { 151,  MODE(4) },      /* SOC_McASP2ACLKX */
 238
 239        /* MCASP1 */
 240        { 152,  MODE(4) },      /* SOC_MCASP1ACLKR */
 241        { 153,  MODE(4) },      /* SOC_MCASP1FSR */
 242        { 154,  MODE(4) },      /* SOC_MCASP1AHCLKR */
 243        { 155,  MODE(4) },      /* SOC_MCASP1ACLKX */
 244        { 156,  MODE(4) },      /* SOC_MCASP1FSX */
 245        { 157,  MODE(4) },      /* SOC_MCASP1AHCLKX */
 246        { 158,  MODE(4) },      /* SOC_MCASP1AMUTE */
 247        { 159,  MODE(4) },      /* SOC_MCASP1AXR0 */
 248        { 160,  MODE(4) },      /* SOC_MCASP1AXR1 */
 249        { 161,  MODE(4) },      /* SOC_MCASP1AXR2 */
 250        { 162,  MODE(4) },      /* SOC_MCASP1AXR3 */
 251        { 163,  MODE(4) },      /* SOC_MCASP1AXR4 */
 252        { 164,  MODE(4) },      /* SOC_MCASP1AXR5 */
 253        { 165,  MODE(4) },      /* SOC_MCASP1AXR6 */
 254        { 166,  MODE(4) },      /* SOC_MCASP1AXR7 */
 255        { 167,  MODE(4) },      /* SOC_MCASP1AXR8 */
 256        { 168,  MODE(4) },      /* SOC_MCASP1AXR9 */
 257
 258        /* MCASP0 */
 259        { 169,  MODE(4) },      /* SOC_MCASP0AMUTE */
 260        { 170,  MODE(4) },      /* SOC_MCASP0ACLKR */
 261        { 171,  MODE(4) },      /* SOC_MCASP0FSR */
 262        { 172,  MODE(4) },      /* SOC_MCASP0AHCLKR */
 263        { 173,  MODE(4) },      /* SOC_MCASP0ACLKX */
 264        { 174,  MODE(4) },      /* SOC_MCASP0FSX */
 265        { 175,  MODE(4) },      /* SOC_MCASP0AHCLKX */
 266        { 176,  MODE(4) },      /* SOC_MCASP0AXR0 */
 267        { 177,  MODE(4) },      /* SOC_MCASP0AXR1 */
 268        { 178,  MODE(4) },      /* SOC_MCASP0AXR2 */
 269        { 179,  MODE(4) },      /* SOC_MCASP0AXR3 */
 270        { 180,  MODE(4) },      /* SOC_MCASP0AXR4 */
 271        { 181,  MODE(4) },      /* SOC_MCASP0AXR5 */
 272        { 182,  MODE(4) },      /* SOC_MCASP0AXR6 */
 273        { 183,  MODE(4) },      /* SOC_MCASP0AXR7 */
 274        { 184,  MODE(4) },      /* SOC_MCASP0AXR8 */
 275        { 185,  MODE(4) },      /* SOC_MCASP0AXR9 */
 276        { 186,  MODE(3) },      /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */
 277        { 188,  MODE(4) },      /* SOC_MCASP0AXR12 */
 278        { 189,  MODE(4) },      /* SOC_MCASP0AXR13 */
 279        { 190,  MODE(4) },      /* SOC_MCASP0AXR14 */
 280        { 191,  MODE(4) },      /* SOC_MCASP0AXR15 */
 281
 282        /* MMC0 */
 283        { 192,  MODE(2) },      /* SOC_MMC0_DAT3 */
 284        { 193,  MODE(2) },      /* SOC_MMC0_DAT2 */
 285        { 194,  MODE(2) },      /* SOC_MMC0_DAT1 */
 286        { 195,  MODE(2) },      /* SOC_MMC0_DAT0 */
 287        { 196,  MODE(2) },      /* SOC_MMC0_CLK */
 288        { 197,  MODE(2) },      /* SOC_MMC0_CMD */
 289        { 187,  MODE(2) },      /* SOC_MMC0_SDCD */
 290
 291        /* McBSP */
 292        { 28,   MODE(2) | PIN_IEN },    /* SOC_TIMI1 */
 293        { 29,   MODE(2) },              /* SOC_TIMO1 */
 294        { 210,  MODE(2) },      /* SOC_MCBSPDR */
 295        { 211,  MODE(2) },      /* SOC_MCBSPDX */
 296        { 212,  MODE(2) },      /* SOC_MCBSPFSX */
 297        { 213,  MODE(2) },      /* SOC_MCBSPCLKX */
 298        { 214,  MODE(2) },      /* SOC_MCBSPFSR */
 299        { 215,  MODE(2) },      /* SOC_MCBSPCLKR */
 300
 301        /* I2C */
 302        { 223,  MODE(0) },      /* SOC_I2C0_SCL */
 303        { 224,  MODE(0) },      /* SOC_I2C0_SDA */
 304        { 225,  MODE(0) },      /* SOC_I2C1_SCL */
 305        { 226,  MODE(0) },      /* SOC_I2C1_SDA */
 306        { 227,  MODE(0) },      /* SOC_I2C2_SCL */
 307        { 228,  MODE(0) },      /* SOC_I2C2_SDA */
 308        { 229,  MODE(0) },      /* NMIz */
 309        { 230,  MODE(0) },      /* LRESETz */
 310        { 231,  MODE(0) },      /* LRESETNMIENz */
 311
 312        { 235,  MODE(0) },
 313        { 236,  MODE(0) },
 314        { 237,  MODE(0) },
 315        { 238,  MODE(0) },
 316        { 239,  MODE(0) },
 317        { 240,  MODE(0) },
 318        { 241,  MODE(0) },
 319        { 242,  MODE(0) },
 320        { 243,  MODE(0) },
 321        { 244,  MODE(0) },
 322
 323        { 258,  MODE(0) },      /* USB0DRVVBUS */
 324        { 259,  MODE(0) },      /* USB1DRVVBUS */
 325        { MAX_PIN_N, }
 326};
 327
 328struct pin_cfg k2g_ice_evm_pin_cfg[] = {
 329        /* MMC 1 */
 330        { 63, MODE(0) | PIN_PTD },      /* MMC1_DAT3.MMC1_DAT3 */
 331        { 64, MODE(0) | PIN_PTU },      /* MMC1_DAT2.MMC1_DAT2 */
 332        { 65, MODE(0) | PIN_PTU },      /* MMC1_DAT1.MMC1_DAT1 */
 333        { 66, MODE(0) | PIN_PTD },      /* MMC1_DAT0.MMC1_DAT0 */
 334        { 67, MODE(0) | PIN_PTD },      /* MMC1_CLK.MMC1_CLK   */
 335        { 68, MODE(0) | PIN_PTD },      /* MMC1_CMD.MMC1_CMD   */
 336        { 69, MODE(3) | PIN_PTU },      /* MMC1_SDCD.GPIO0_69  */
 337        { 70, MODE(0) | PIN_PTU },      /* MMC1_SDWP.MMC1_SDWP */
 338        { 71, MODE(0) | PIN_PTD },      /* MMC1_POW.MMC1_POW   */
 339
 340        /* I2C 0 */
 341        { 223,  MODE(0) },              /* SOC_I2C0_SCL */
 342        { 224,  MODE(0) },              /* SOC_I2C0_SDA */
 343
 344        /* QSPI */
 345        { 129,  MODE(0) },      /* SOC_QSPI_CLK */
 346        { 130,  MODE(0) },      /* SOC_QSPI_RTCLK */
 347        { 131,  MODE(0) },      /* SOC_QSPI_D0 */
 348        { 132,  MODE(0) },      /* SOC_QSPI_D1 */
 349        { 133,  MODE(0) },      /* SOC_QSPI_D2 */
 350        { 134,  MODE(0) },      /* SOC_QSPI_D3 */
 351        { 135,  MODE(0) },      /* SOC_QSPI_CSN0 */
 352
 353        /* EMAC */
 354        { 72,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXC */
 355        { 77,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD3 */
 356        { 78,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD2 */
 357        { 79,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD1 */
 358        { 80,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD0 */
 359        { 81,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXCTL */
 360        { 85,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXC */
 361        { 91,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD3 */
 362        { 92,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD2 */
 363        { 93,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD1 */
 364        { 94,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD0 */
 365        { 95,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXCTL */
 366
 367        /* MDIO */
 368        { 98,   BUFFER_CLASS_B | PIN_PDIS | MODE(0) },  /* MDIO_DATA */
 369        { 99,   BUFFER_CLASS_B | PIN_PDIS | MODE(0) },  /* MDIO_CLK */
 370
 371        /* ICSS1 Padconf Workaround */
 372        { 202, MODE(1) | PIN_PDIS },    /* PR1_PRU1_GPO1.PR1_PRU1_GPI1 (PR1_MII1_RXD1) */
 373
 374        { MAX_PIN_N, }
 375};
 376
 377void k2g_mux_config(void)
 378{
 379        if (!board_ti_was_eeprom_read()) {
 380                configure_pin_mux(k2g_generic_pin_cfg);
 381        } else if (board_is_k2g_gp() || board_is_k2g_g1()) {
 382                configure_pin_mux(k2g_evm_pin_cfg);
 383        } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
 384                configure_pin_mux(k2g_ice_evm_pin_cfg);
 385        } else {
 386                puts("Unknown board, cannot configure pinmux.");
 387                hang();
 388        }
 389}
 390