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10#include <init.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/iomux.h>
15#include <asm/arch/sys_proto.h>
16#include <env.h>
17#include <fdt_support.h>
18#include <asm/global_data.h>
19#include <linux/errno.h>
20#include <asm/gpio.h>
21#include <asm/io.h>
22#include <asm/mach-imx/mxc_i2c.h>
23#include <asm/mach-imx/spi.h>
24#include <common.h>
25#include <fsl_esdhc_imx.h>
26#include <linux/libfdt.h>
27#include <i2c.h>
28#include <mmc.h>
29#include <power/pfuze100_pmic.h>
30#include <power/pmic.h>
31#include <spi_flash.h>
32
33#include "tqma6_bb.h"
34
35DECLARE_GLOBAL_DATA_PTR;
36
37#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
38 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39
40#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
44 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
45
46#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
47 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48
49#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
51
52#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
53 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
54 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
55
56int dram_init(void)
57{
58 gd->ram_size = imx_ddr_size();
59
60 return 0;
61}
62
63static const uint16_t tqma6_emmc_dsr = 0x0100;
64
65#ifndef CONFIG_DM_MMC
66
67static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
68 NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
69 NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
70 NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
71 NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
72 NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
73 NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
74 NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
75 NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
76 NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
77 NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
78
79 NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
80};
81
82
83
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85
86
87
88struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
89 .esdhc_base = USDHC3_BASE_ADDR,
90 .max_bus_width = 8,
91};
92
93int board_mmc_getcd(struct mmc *mmc)
94{
95 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
96 int ret = 0;
97
98 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
99
100 ret = 1;
101 else
102 ret = tqma6_bb_board_mmc_getcd(mmc);
103
104 return ret;
105}
106
107int board_mmc_getwp(struct mmc *mmc)
108{
109 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
110 int ret = 0;
111
112 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
113
114 ret = 0;
115 else
116 ret = tqma6_bb_board_mmc_getwp(mmc);
117
118 return ret;
119}
120
121int board_mmc_init(struct bd_info *bis)
122{
123 imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
124 ARRAY_SIZE(tqma6_usdhc3_pads));
125 tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
126 if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
127 puts("Warning: failed to initialize eMMC dev\n");
128 } else {
129 struct mmc *mmc = find_mmc_device(0);
130 if (mmc)
131 mmc_set_dsr(mmc, tqma6_emmc_dsr);
132 }
133
134 tqma6_bb_board_mmc_init(bis);
135
136 return 0;
137}
138#endif
139
140#ifndef CONFIG_DM_SPI
141static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
142
143 NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
144 NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
145 NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
146 NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
147};
148
149#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
150
151static unsigned const tqma6_ecspi1_cs[] = {
152 TQMA6_SF_CS_GPIO,
153};
154
155__weak void tqma6_iomuxc_spi(void)
156{
157 unsigned i;
158
159 for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
160 gpio_direction_output(tqma6_ecspi1_cs[i], 1);
161 imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
162 ARRAY_SIZE(tqma6_ecspi1_pads));
163}
164
165#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
166int board_spi_cs_gpio(unsigned bus, unsigned cs)
167{
168 return ((bus == CONFIG_SF_DEFAULT_BUS) &&
169 (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
170}
171#endif
172#endif
173
174#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
175static struct i2c_pads_info tqma6_i2c3_pads = {
176
177 .scl = {
178 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
179 I2C_PAD_CTRL),
180 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
181 I2C_PAD_CTRL),
182 .gp = IMX_GPIO_NR(1, 5)
183 },
184 .sda = {
185 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
186 I2C_PAD_CTRL),
187 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
188 I2C_PAD_CTRL),
189 .gp = IMX_GPIO_NR(1, 6)
190 }
191};
192
193static void tqma6_setup_i2c(void)
194{
195 int ret;
196
197
198
199
200 ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
201 if (ret)
202 printf("setup I2C3 failed: %d\n", ret);
203}
204#endif
205
206int board_early_init_f(void)
207{
208 return tqma6_bb_board_early_init_f();
209}
210
211int board_init(void)
212{
213
214 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
215
216#ifndef CONFIG_DM_SPI
217 tqma6_iomuxc_spi();
218#endif
219#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
220 tqma6_setup_i2c();
221#endif
222
223 tqma6_bb_board_init();
224
225 return 0;
226}
227
228static const char *tqma6_get_boardname(void)
229{
230 u32 cpurev = get_cpu_rev();
231
232 switch ((cpurev & 0xFF000) >> 12) {
233 case MXC_CPU_MX6SOLO:
234 return "TQMa6S";
235 break;
236 case MXC_CPU_MX6DL:
237 return "TQMa6DL";
238 break;
239 case MXC_CPU_MX6D:
240 return "TQMa6D";
241 break;
242 case MXC_CPU_MX6Q:
243 return "TQMa6Q";
244 break;
245 default:
246 return "??";
247 };
248}
249
250#if CONFIG_IS_ENABLED(POWER_LEGACY)
251
252int power_init_board(void)
253{
254 struct pmic *p;
255 u32 reg, rev;
256
257 power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
258 p = pmic_get("PFUZE100");
259 if (p && !pmic_probe(p)) {
260 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
261 pmic_reg_read(p, PFUZE100_REVID, &rev);
262 printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
263 }
264
265 return 0;
266}
267#endif
268
269int board_late_init(void)
270{
271 env_set("board_name", tqma6_get_boardname());
272
273 tqma6_bb_board_late_init();
274
275 return 0;
276}
277
278int checkboard(void)
279{
280 printf("Board: %s on a %s\n", tqma6_get_boardname(),
281 tqma6_bb_get_boardname());
282 return 0;
283}
284
285
286
287
288#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
289#define MODELSTRLEN 32u
290int ft_board_setup(void *blob, struct bd_info *bd)
291{
292 char modelstr[MODELSTRLEN];
293
294 snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
295 tqma6_bb_get_boardname());
296 do_fixup_by_path_string(blob, "/", "model", modelstr);
297 fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
298
299 do_fixup_by_path_u32(blob,
300 "/soc/aips-bus@02100000/usdhc@02198000",
301 "dsr", tqma6_emmc_dsr, 2);
302 tqma6_bb_ft_board_setup(blob, bd);
303
304 return 0;
305}
306#endif
307
