1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2019 Xilinx, Inc. 4 * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> 5 */ 6 7#ifndef __FRU_H 8#define __FRU_H 9 10struct fru_common_hdr { 11 u8 version; 12 u8 off_internal; 13 u8 off_chassis; 14 u8 off_board; 15 u8 off_product; 16 u8 off_multirec; 17 u8 pad; 18 u8 crc; 19}; 20 21#define FRU_BOARD_MAX_LEN 32 22 23struct __packed fru_board_info_header { 24 u8 ver; 25 u8 len; 26 u8 lang_code; 27 u8 time[3]; 28}; 29 30struct __packed fru_board_info_member { 31 u8 type_len; 32 u8 *name; 33}; 34 35struct fru_board_data { 36 u8 ver; 37 u8 len; 38 u8 lang_code; 39 u8 time[3]; 40 u8 manufacturer_type_len; 41 u8 manufacturer_name[FRU_BOARD_MAX_LEN]; 42 u8 product_name_type_len; 43 u8 product_name[FRU_BOARD_MAX_LEN]; 44 u8 serial_number_type_len; 45 u8 serial_number[FRU_BOARD_MAX_LEN]; 46 u8 part_number_type_len; 47 u8 part_number[FRU_BOARD_MAX_LEN]; 48 u8 file_id_type_len; 49 u8 file_id[FRU_BOARD_MAX_LEN]; 50 /* Xilinx custom fields */ 51 u8 rev_type_len; 52 u8 rev[FRU_BOARD_MAX_LEN]; 53 u8 pcie_type_len; 54 u8 pcie[FRU_BOARD_MAX_LEN]; 55 u8 uuid_type_len; 56 u8 uuid[FRU_BOARD_MAX_LEN]; 57}; 58 59struct fru_table { 60 struct fru_common_hdr hdr; 61 struct fru_board_data brd; 62 bool captured; 63}; 64 65#define FRU_TYPELEN_CODE_MASK 0xC0 66#define FRU_TYPELEN_LEN_MASK 0x3F 67#define FRU_COMMON_HDR_VER_MASK 0xF 68#define FRU_COMMON_HDR_LEN_MULTIPLIER 8 69#define FRU_LANG_CODE_ENGLISH 0 70#define FRU_LANG_CODE_ENGLISH_1 25 71#define FRU_TYPELEN_EOF 0xC1 72 73/* This should be minimum of fields */ 74#define FRU_BOARD_AREA_TOTAL_FIELDS 5 75#define FRU_TYPELEN_TYPE_SHIFT 6 76#define FRU_TYPELEN_TYPE_BINARY 0 77#define FRU_TYPELEN_TYPE_ASCII8 3 78 79int fru_display(int verbose); 80int fru_capture(unsigned long addr); 81int fru_generate(unsigned long addr, char *manufacturer, char *board_name, 82 char *serial_no, char *part_no, char *revision); 83u8 fru_checksum(u8 *addr, u8 len); 84 85extern struct fru_table fru_data; 86 87#endif /* FRU_H */ 88