LXR uboot/drivers/axi/ihs

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2016
   4 * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5 *
   6 * (C) Copyright 2017, 2018
   7 * Mario Six,  Guntermann & Drunck GmbH, mario.six@gdsys.cc
   8 */
   9
  10#include <common.h>
  11#include <axi.h>
  12#include <dm.h>
  13#include <log.h>
  14#include <regmap.h>
  15#include <linux/bitops.h>
  16#include <linux/delay.h>
  17
  18/**
  19 * struct ihs_axi_regs - Structure for the register map of a IHS AXI device
  20 * @interrupt_status:         Status register to indicate certain events (e.g.
  21 *                            error during transfer, transfer complete, etc.)
  22 * @interrupt_enable_control: Register to both control which statuses will be
  23 *                            indicated in the interrupt_status register, and
  24 *                            to change bus settings
  25 * @address_lsb:              Least significant 16-bit word of the address of a
  26 *                            device to transfer data from/to
  27 * @address_msb:              Most significant 16-bit word of the address of a
  28 *                            device to transfer data from/to
  29 * @write_data_lsb:           Least significant 16-bit word of the data to be
  30 *                            written to a device
  31 * @write_data_msb:           Most significant 16-bit word of the data to be
  32 *                            written to a device
  33 * @read_data_lsb:            Least significant 16-bit word of the data read
  34 *                            from a device
  35 * @read_data_msb:            Most significant 16-bit word of the data read
  36 *                            from a device
  37 */
  38struct ihs_axi_regs {
  39        u16 interrupt_status;
  40        u16 interrupt_enable_control;
  41        u16 address_lsb;
  42        u16 address_msb;
  43        u16 write_data_lsb;
  44        u16 write_data_msb;
  45        u16 read_data_lsb;
  46        u16 read_data_msb;
  47};
  48
  49/**
  50 * ihs_axi_set() - Convenience macro to set values in register map
  51 * @map:    The register map to write to
  52 * @member: The member of the ihs_axi_regs structure to write
  53 * @val:    The value to write to the register map
  54 */
  55#define ihs_axi_set(map, member, val) \
  56        regmap_set(map, struct ihs_axi_regs, member, val)
  57
  58/**
  59 * ihs_axi_get() - Convenience macro to read values from register map
  60 * @map:    The register map to read from
  61 * @member: The member of the ihs_axi_regs structure to read
  62 * @valp:   Pointer to a buffer to receive the value read
  63 */
  64#define ihs_axi_get(map, member, valp) \
  65        regmap_get(map, struct ihs_axi_regs, member, valp)
  66
  67/**
  68 * struct ihs_axi_priv - Private data structure of IHS AXI devices
  69 * @map: Register map for the IHS AXI device
  70 */
  71struct ihs_axi_priv {
  72        struct regmap *map;
  73};
  74
  75/**
  76 * enum status_reg - Description of bits in the interrupt_status register
  77 * @STATUS_READ_COMPLETE_EVENT:  A read transfer was completed
  78 * @STATUS_WRITE_COMPLETE_EVENT: A write transfer was completed
  79 * @STATUS_TIMEOUT_EVENT:        A timeout has occurred during the transfer
  80 * @STATUS_ERROR_EVENT:          A error has occurred during the transfer
  81 * @STATUS_AXI_INT:              A AXI interrupt has occurred
  82 * @STATUS_READ_DATA_AVAILABLE:  Data is available to be read
  83 * @STATUS_BUSY:                 The bus is busy
  84 * @STATUS_INIT_DONE:            The bus has finished initializing
  85 */
  86enum status_reg {
  87        STATUS_READ_COMPLETE_EVENT = BIT(15),
  88        STATUS_WRITE_COMPLETE_EVENT = BIT(14),
  89        STATUS_TIMEOUT_EVENT = BIT(13),
  90        STATUS_ERROR_EVENT = BIT(12),
  91        STATUS_AXI_INT = BIT(11),
  92        STATUS_READ_DATA_AVAILABLE = BIT(7),
  93        STATUS_BUSY = BIT(6),
  94        STATUS_INIT_DONE = BIT(5),
  95};
  96
  97/**
  98 * enum control_reg - Description of bit fields in the interrupt_enable_control
  99 *                    register
 100 * @CONTROL_READ_COMPLETE_EVENT_ENABLE:  STATUS_READ_COMPLETE_EVENT will be
 101 *                                       raised in the interrupt_status register
 102 * @CONTROL_WRITE_COMPLETE_EVENT_ENABLE: STATUS_WRITE_COMPLETE_EVENT will be
 103 *                                       raised in the interrupt_status register
 104 * @CONTROL_TIMEOUT_EVENT_ENABLE:        STATUS_TIMEOUT_EVENT will be raised in
 105 *                                       the interrupt_status register
 106 * @CONTROL_ERROR_EVENT_ENABLE:          STATUS_ERROR_EVENT will be raised in
 107 *                                       the interrupt_status register
 108 * @CONTROL_AXI_INT_ENABLE:              STATUS_AXI_INT will be raised in the
 109 *                                       interrupt_status register
 110 * @CONTROL_CMD_NOP:                     Configure bus to send a NOP command
 111 *                                       for the next transfer
 112 * @CONTROL_CMD_WRITE:                   Configure bus to do a write transfer
 113 * @CONTROL_CMD_WRITE_POST_INC:          Auto-increment address after write
 114 *                                       transfer
 115 * @CONTROL_CMD_READ:                    Configure bus to do a read transfer
 116 * @CONTROL_CMD_READ_POST_INC:           Auto-increment address after read
 117 *                                       transfer
 118 */
 119enum control_reg {
 120        CONTROL_READ_COMPLETE_EVENT_ENABLE = BIT(15),
 121        CONTROL_WRITE_COMPLETE_EVENT_ENABLE = BIT(14),
 122        CONTROL_TIMEOUT_EVENT_ENABLE = BIT(13),
 123        CONTROL_ERROR_EVENT_ENABLE = BIT(12),
 124        CONTROL_AXI_INT_ENABLE = BIT(11),
 125
 126        CONTROL_CMD_NOP = 0x0,
 127        CONTROL_CMD_WRITE = 0x8,
 128        CONTROL_CMD_WRITE_POST_INC = 0x9,
 129        CONTROL_CMD_READ = 0xa,
 130        CONTROL_CMD_READ_POST_INC = 0xb,
 131};
 132
 133/**
 134 * enum axi_cmd - Determine if transfer is read or write transfer
 135 * @AXI_CMD_READ:  The transfer should be a read transfer
 136 * @AXI_CMD_WRITE: The transfer should be a write transfer
 137 */
 138enum axi_cmd {
 139        AXI_CMD_READ,
 140        AXI_CMD_WRITE,
 141};
 142
 143/**
 144 * ihs_axi_transfer() - Run transfer on the AXI bus
 145 * @bus:           The AXI bus device on which to run the transfer on
 146 * @address:       The address to use in the transfer (i.e. which address to
 147 *                 read/write from/to)
 148 * @cmd:           Should the transfer be a read or write transfer?
 149 *
 150 * Return: 0 if OK, -ve on error
 151 */
 152static int ihs_axi_transfer(struct udevice *bus, ulong address,
 153                            enum axi_cmd cmd)
 154{
 155        struct ihs_axi_priv *priv = dev_get_priv(bus);
 156        /* Try waiting for events up to 10 times */
 157        const uint WAIT_TRIES = 10;
 158        u16 wait_mask = STATUS_TIMEOUT_EVENT |
 159                        STATUS_ERROR_EVENT;
 160        u16 complete_flag;
 161        u16 status;
 162        uint k;
 163
 164        if (cmd == AXI_CMD_READ) {
 165                complete_flag = STATUS_READ_COMPLETE_EVENT;
 166                cmd = CONTROL_CMD_READ;
 167        } else {
 168                complete_flag = STATUS_WRITE_COMPLETE_EVENT;
 169                cmd = CONTROL_CMD_WRITE;
 170        }
 171
 172        wait_mask |= complete_flag;
 173
 174        /* Lower 16 bit */
 175        ihs_axi_set(priv->map, address_lsb, address & 0xffff);
 176        /* Upper 16 bit */
 177        ihs_axi_set(priv->map, address_msb, (address >> 16) & 0xffff);
 178
 179        ihs_axi_set(priv->map, interrupt_status, wait_mask);
 180        ihs_axi_set(priv->map, interrupt_enable_control, cmd);
 181
 182        for (k = WAIT_TRIES; k > 0; --k) {
 183                ihs_axi_get(priv->map, interrupt_status, &status);
 184                if (status & wait_mask)
 185                        break;
 186                udelay(1);
 187        }
 188
 189        /*
 190         * k == 0 -> Tries ran out with no event we were waiting for actually
 191         * occurring.
 192         */
 193        if (!k)
 194                ihs_axi_get(priv->map, interrupt_status, &status);
 195
 196        if (status & complete_flag)
 197                return 0;
 198
 199        if (status & STATUS_ERROR_EVENT) {
 200                debug("%s: Error occurred during transfer\n", bus->name);
 201                return -EIO;
 202        }
 203
 204        debug("%s: Transfer timed out\n", bus->name);
 205        return -ETIMEDOUT;
 206}
 207
 208/*
 209 * API
 210 */
 211
 212static int ihs_axi_read(struct udevice *dev, ulong address, void *data,
 213                        enum axi_size_t size)
 214{
 215        struct ihs_axi_priv *priv = dev_get_priv(dev);
 216        int ret;
 217        u16 data_lsb, data_msb;
 218        u32 *p = data;
 219
 220        if (size != AXI_SIZE_32) {
 221                debug("%s: transfer size '%d' not supported\n",
 222                      dev->name, size);
 223                return -ENOSYS;
 224        }
 225
 226        ret = ihs_axi_transfer(dev, address, AXI_CMD_READ);
 227        if (ret < 0) {
 228                debug("%s: Error during AXI transfer (err = %d)\n",
 229                      dev->name, ret);
 230                return ret;
 231        }
 232
 233        ihs_axi_get(priv->map, read_data_lsb, &data_lsb);
 234        ihs_axi_get(priv->map, read_data_msb, &data_msb);
 235
 236        /* Assemble data from two 16-bit words */
 237        *p = (data_msb << 16) | data_lsb;
 238
 239        return 0;
 240}
 241
 242static int ihs_axi_write(struct udevice *dev, ulong address, void *data,
 243                         enum axi_size_t size)
 244{
 245        struct ihs_axi_priv *priv = dev_get_priv(dev);
 246        int ret;
 247        u32 *p = data;
 248
 249        if (size != AXI_SIZE_32) {
 250                debug("%s: transfer size '%d' not supported\n",
 251                      dev->name, size);
 252                return -ENOSYS;
 253        }
 254
 255        /* Lower 16 bit */
 256        ihs_axi_set(priv->map, write_data_lsb, *p & 0xffff);
 257        /* Upper 16 bit */
 258        ihs_axi_set(priv->map, write_data_msb, (*p >> 16) & 0xffff);
 259
 260        ret = ihs_axi_transfer(dev, address, AXI_CMD_WRITE);
 261        if (ret < 0) {
 262                debug("%s: Error during AXI transfer (err = %d)\n",
 263                      dev->name, ret);
 264                return ret;
 265        }
 266
 267        return 0;
 268}
 269
 270static const struct udevice_id ihs_axi_ids[] = {
 271        { .compatible = "gdsys,ihs_axi" },
 272        { /* sentinel */ }
 273};
 274
 275static const struct axi_ops ihs_axi_ops = {
 276        .read = ihs_axi_read,
 277        .write = ihs_axi_write,
 278};
 279
 280static int ihs_axi_probe(struct udevice *dev)
 281{
 282        struct ihs_axi_priv *priv = dev_get_priv(dev);
 283
 284        regmap_init_mem(dev_ofnode(dev), &priv->map);
 285
 286        return 0;
 287}
 288
 289U_BOOT_DRIVER(ihs_axi_bus) = {
 290        .name           = "ihs_axi_bus",
 291        .id             = UCLASS_AXI,
 292        .of_match       = ihs_axi_ids,
 293        .ops            = &ihs_axi_ops,
 294        .priv_auto      = sizeof(struct ihs_axi_priv),
 295        .probe          = ihs_axi_probe,
 296};
 297