LXR uboot/drivers/clk/clk

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2020 Stefan Roese <sr@denx.de>
   4 */
   5
   6#include <clk-uclass.h>
   7#include <dm.h>
   8#include <asm/global_data.h>
   9#include <dt-bindings/clock/octeon-clock.h>
  10
  11DECLARE_GLOBAL_DATA_PTR;
  12
  13struct octeon_clk_priv {
  14        u64 core_clk;
  15        u64 io_clk;
  16};
  17
  18static int octeon_clk_enable(struct clk *clk)
  19{
  20        /* Nothing to do on Octeon */
  21        return 0;
  22}
  23
  24static ulong octeon_clk_get_rate(struct clk *clk)
  25{
  26        struct octeon_clk_priv *priv = dev_get_priv(clk->dev);
  27
  28        switch (clk->id) {
  29        case OCTEON_CLK_CORE:
  30                return priv->core_clk;
  31
  32        case OCTEON_CLK_IO:
  33                return priv->io_clk;
  34
  35        default:
  36                return 0;
  37        }
  38
  39        return 0;
  40}
  41
  42static struct clk_ops octeon_clk_ops = {
  43        .enable = octeon_clk_enable,
  44        .get_rate = octeon_clk_get_rate,
  45};
  46
  47static const struct udevice_id octeon_clk_ids[] = {
  48        { .compatible = "mrvl,octeon-clk" },
  49        { /* sentinel */ }
  50};
  51
  52static int octeon_clk_probe(struct udevice *dev)
  53{
  54        struct octeon_clk_priv *priv = dev_get_priv(dev);
  55
  56        /*
  57         * The clock values are already read into GD, lets just store them
  58         * in priv data
  59         */
  60        priv->core_clk = gd->cpu_clk;
  61        priv->io_clk = gd->bus_clk;
  62
  63        return 0;
  64}
  65
  66U_BOOT_DRIVER(clk_octeon) = {
  67        .name = "clk_octeon",
  68        .id = UCLASS_CLK,
  69        .of_match = octeon_clk_ids,
  70        .ops = &octeon_clk_ops,
  71        .probe = octeon_clk_probe,
  72        .priv_auto      = sizeof(struct octeon_clk_priv),
  73};
  74