LXR uboot/drivers/clk/clk

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   5 */
   6
   7#define LOG_CATEGORY UCLASS_CLK
   8
   9#include <common.h>
  10#include <clk-uclass.h>
  11#include <dm.h>
  12#include <log.h>
  13#include <stm32_rcc.h>
  14#include <asm/io.h>
  15#include <asm/arch/stm32.h>
  16#include <asm/arch/stm32_pwr.h>
  17#include <dm/device_compat.h>
  18#include <dt-bindings/mfd/stm32f7-rcc.h>
  19#include <linux/bitops.h>
  20
  21#define RCC_CR_HSION                    BIT(0)
  22#define RCC_CR_HSEON                    BIT(16)
  23#define RCC_CR_HSERDY                   BIT(17)
  24#define RCC_CR_HSEBYP                   BIT(18)
  25#define RCC_CR_CSSON                    BIT(19)
  26#define RCC_CR_PLLON                    BIT(24)
  27#define RCC_CR_PLLRDY                   BIT(25)
  28#define RCC_CR_PLLSAION                 BIT(28)
  29#define RCC_CR_PLLSAIRDY                BIT(29)
  30
  31#define RCC_PLLCFGR_PLLM_MASK           GENMASK(5, 0)
  32#define RCC_PLLCFGR_PLLN_MASK           GENMASK(14, 6)
  33#define RCC_PLLCFGR_PLLP_MASK           GENMASK(17, 16)
  34#define RCC_PLLCFGR_PLLQ_MASK           GENMASK(27, 24)
  35#define RCC_PLLCFGR_PLLSRC              BIT(22)
  36#define RCC_PLLCFGR_PLLM_SHIFT          0
  37#define RCC_PLLCFGR_PLLN_SHIFT          6
  38#define RCC_PLLCFGR_PLLP_SHIFT          16
  39#define RCC_PLLCFGR_PLLQ_SHIFT          24
  40
  41#define RCC_CFGR_AHB_PSC_MASK           GENMASK(7, 4)
  42#define RCC_CFGR_APB1_PSC_MASK          GENMASK(12, 10)
  43#define RCC_CFGR_APB2_PSC_MASK          GENMASK(15, 13)
  44#define RCC_CFGR_SW0                    BIT(0)
  45#define RCC_CFGR_SW1                    BIT(1)
  46#define RCC_CFGR_SW_MASK                GENMASK(1, 0)
  47#define RCC_CFGR_SW_HSI                 0
  48#define RCC_CFGR_SW_HSE                 RCC_CFGR_SW0
  49#define RCC_CFGR_SW_PLL                 RCC_CFGR_SW1
  50#define RCC_CFGR_SWS0                   BIT(2)
  51#define RCC_CFGR_SWS1                   BIT(3)
  52#define RCC_CFGR_SWS_MASK               GENMASK(3, 2)
  53#define RCC_CFGR_SWS_HSI                0
  54#define RCC_CFGR_SWS_HSE                RCC_CFGR_SWS0
  55#define RCC_CFGR_SWS_PLL                RCC_CFGR_SWS1
  56#define RCC_CFGR_HPRE_SHIFT             4
  57#define RCC_CFGR_PPRE1_SHIFT            10
  58#define RCC_CFGR_PPRE2_SHIFT            13
  59
  60#define RCC_PLLSAICFGR_PLLSAIN_MASK     GENMASK(14, 6)
  61#define RCC_PLLSAICFGR_PLLSAIP_MASK     GENMASK(17, 16)
  62#define RCC_PLLSAICFGR_PLLSAIQ_MASK     GENMASK(27, 24)
  63#define RCC_PLLSAICFGR_PLLSAIR_MASK     GENMASK(30, 28)
  64#define RCC_PLLSAICFGR_PLLSAIN_SHIFT    6
  65#define RCC_PLLSAICFGR_PLLSAIP_SHIFT    16
  66#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT    24
  67#define RCC_PLLSAICFGR_PLLSAIR_SHIFT    28
  68#define RCC_PLLSAICFGR_PLLSAIP_4        BIT(16)
  69#define RCC_PLLSAICFGR_PLLSAIQ_4        BIT(26)
  70#define RCC_PLLSAICFGR_PLLSAIR_3        BIT(29) | BIT(28)
  71
  72#define RCC_DCKCFGRX_TIMPRE             BIT(24)
  73#define RCC_DCKCFGRX_CK48MSEL           BIT(27)
  74#define RCC_DCKCFGRX_SDMMC1SEL          BIT(28)
  75#define RCC_DCKCFGR2_SDMMC2SEL          BIT(29)
  76
  77#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT    16
  78#define RCC_DCKCFGR_PLLSAIDIVR_MASK     GENMASK(17, 16)
  79#define RCC_DCKCFGR_PLLSAIDIVR_2        0
  80
  81/*
  82 * RCC AHB1ENR specific definitions
  83 */
  84#define RCC_AHB1ENR_ETHMAC_EN           BIT(25)
  85#define RCC_AHB1ENR_ETHMAC_TX_EN        BIT(26)
  86#define RCC_AHB1ENR_ETHMAC_RX_EN        BIT(27)
  87
  88/*
  89 * RCC APB1ENR specific definitions
  90 */
  91#define RCC_APB1ENR_TIM2EN              BIT(0)
  92#define RCC_APB1ENR_PWREN               BIT(28)
  93
  94/*
  95 * RCC APB2ENR specific definitions
  96 */
  97#define RCC_APB2ENR_SYSCFGEN            BIT(14)
  98#define RCC_APB2ENR_SAI1EN              BIT(22)
  99
 100enum pllsai_div {
 101        PLLSAIP,
 102        PLLSAIQ,
 103        PLLSAIR,
 104};
 105
 106static const struct stm32_clk_info stm32f4_clk_info = {
 107        /* 180 MHz */
 108        .sys_pll_psc = {
 109                .pll_n = 360,
 110                .pll_p = 2,
 111                .pll_q = 8,
 112                .ahb_psc = AHB_PSC_1,
 113                .apb1_psc = APB_PSC_4,
 114                .apb2_psc = APB_PSC_2,
 115        },
 116        .has_overdrive = false,
 117        .v2 = false,
 118};
 119
 120static const struct stm32_clk_info stm32f7_clk_info = {
 121        /* 200 MHz */
 122        .sys_pll_psc = {
 123                .pll_n = 400,
 124                .pll_p = 2,
 125                .pll_q = 8,
 126                .ahb_psc = AHB_PSC_1,
 127                .apb1_psc = APB_PSC_4,
 128                .apb2_psc = APB_PSC_2,
 129        },
 130        .has_overdrive = true,
 131        .v2 = true,
 132};
 133
 134struct stm32_clk {
 135        struct stm32_rcc_regs *base;
 136        struct stm32_pwr_regs *pwr_regs;
 137        struct stm32_clk_info info;
 138        unsigned long hse_rate;
 139        bool pllsaip;
 140};
 141
 142#ifdef CONFIG_VIDEO_STM32
 143static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
 144#endif
 145static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
 146
 147static int configure_clocks(struct udevice *dev)
 148{
 149        struct stm32_clk *priv = dev_get_priv(dev);
 150        struct stm32_rcc_regs *regs = priv->base;
 151        struct stm32_pwr_regs *pwr = priv->pwr_regs;
 152        struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
 153
 154        /* Reset RCC configuration */
 155        setbits_le32(&regs->cr, RCC_CR_HSION);
 156        writel(0, &regs->cfgr); /* Reset CFGR */
 157        clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
 158                | RCC_CR_PLLON | RCC_CR_PLLSAION));
 159        writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
 160        clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
 161        writel(0, &regs->cir); /* Disable all interrupts */
 162
 163        /* Configure for HSE+PLL operation */
 164        setbits_le32(&regs->cr, RCC_CR_HSEON);
 165        while (!(readl(&regs->cr) & RCC_CR_HSERDY))
 166                ;
 167
 168        setbits_le32(&regs->cfgr, ((
 169                sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
 170                | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
 171                | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 172
 173        /* Configure the main PLL */
 174        setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
 175        clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
 176                        sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
 177        clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
 178                        sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
 179        clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
 180                        ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
 181        clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
 182                        sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
 183
 184        /* configure SDMMC clock */
 185        if (priv->info.v2) { /*stm32f7 case */
 186                if (priv->pllsaip)
 187                        /* select PLLSAIP as 48MHz clock source */
 188                        setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
 189                else
 190                        /* select PLLQ as 48MHz clock source */
 191                        clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
 192
 193                /* select 48MHz as SDMMC1 clock source */
 194                clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
 195
 196                /* select 48MHz as SDMMC2 clock source */
 197                clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
 198        } else  { /* stm32f4 case */
 199                if (priv->pllsaip)
 200                        /* select PLLSAIP as 48MHz clock source */
 201                        setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
 202                else
 203                        /* select PLLQ as 48MHz clock source */
 204                        clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
 205
 206                /* select 48MHz as SDMMC1 clock source */
 207                clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
 208        }
 209
 210        /*
 211         * Configure the SAI PLL to generate LTDC pixel clock and
 212         * 48 Mhz for SDMMC and USB
 213         */
 214        clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIP_MASK,
 215                        RCC_PLLSAICFGR_PLLSAIP_4);
 216        clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
 217                        RCC_PLLSAICFGR_PLLSAIR_3);
 218        clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
 219                        195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
 220
 221        clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
 222                        RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
 223
 224        /* Enable the main PLL */
 225        setbits_le32(&regs->cr, RCC_CR_PLLON);
 226        while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
 227                ;
 228
 229        /* Enable the SAI PLL */
 230        setbits_le32(&regs->cr, RCC_CR_PLLSAION);
 231        while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
 232                ;
 233        setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
 234
 235        if (priv->info.has_overdrive) {
 236                /*
 237                 * Enable high performance mode
 238                 * System frequency up to 200 MHz
 239                 */
 240                setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
 241                /* Infinite wait! */
 242                while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
 243                        ;
 244                /* Enable the Over-drive switch */
 245                setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
 246                /* Infinite wait! */
 247                while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
 248                        ;
 249        }
 250
 251        stm32_flash_latency_cfg(5);
 252        clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 253        setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
 254
 255        while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
 256                        RCC_CFGR_SWS_PLL)
 257                ;
 258
 259#ifdef CONFIG_ETH_DESIGNWARE
 260        /* gate the SYSCFG clock, needed to set RMII ethernet interface */
 261        setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
 262#endif
 263
 264        return 0;
 265}
 266
 267static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
 268{
 269        struct stm32_rcc_regs *regs = priv->base;
 270
 271        if (priv->info.v2) /*stm32f7 case */
 272                return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
 273        else
 274
 275                return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
 276}
 277
 278static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
 279{
 280        struct stm32_rcc_regs *regs = priv->base;
 281        u16 pllm, pllsain;
 282
 283        pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 284        pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
 285                  >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
 286
 287        return ((priv->hse_rate / pllm) * pllsain);
 288}
 289
 290static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
 291                                               enum pllsai_div output)
 292{
 293        struct stm32_rcc_regs *regs = priv->base;
 294        u16 pll_div_output;
 295
 296        switch (output) {
 297        case PLLSAIP:
 298                pll_div_output = ((((readl(&regs->pllsaicfgr)
 299                                  & RCC_PLLSAICFGR_PLLSAIP_MASK)
 300                                  >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
 301                break;
 302        case PLLSAIQ:
 303                pll_div_output = (readl(&regs->pllsaicfgr)
 304                                  & RCC_PLLSAICFGR_PLLSAIQ_MASK)
 305                                  >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
 306                break;
 307        case PLLSAIR:
 308                pll_div_output = (readl(&regs->pllsaicfgr)
 309                                  & RCC_PLLSAICFGR_PLLSAIR_MASK)
 310                                  >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
 311                break;
 312        default:
 313                log_err("incorrect PLLSAI output %d\n", output);
 314                return -EINVAL;
 315        }
 316
 317        return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
 318}
 319
 320static bool stm32_get_timpre(struct stm32_clk *priv)
 321{
 322        struct stm32_rcc_regs *regs = priv->base;
 323        u32 val;
 324
 325        if (priv->info.v2) /*stm32f7 case */
 326                val = readl(&regs->dckcfgr2);
 327        else
 328                val = readl(&regs->dckcfgr);
 329        /* get timer prescaler */
 330        return !!(val & RCC_DCKCFGRX_TIMPRE);
 331}
 332
 333static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
 334{
 335        u8 shift;
 336        /* Prescaler table lookups for clock computation */
 337        u8 ahb_psc_table[16] = {
 338                0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 339        };
 340
 341        shift = ahb_psc_table[(
 342                (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 343                >> RCC_CFGR_HPRE_SHIFT)];
 344
 345        return sysclk >> shift;
 346};
 347
 348static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
 349{
 350        /* Prescaler table lookups for clock computation */
 351        u8 apb_psc_table[8] = {
 352                0, 0, 0, 0, 1, 2, 3, 4
 353        };
 354
 355        if (apb == APB1)
 356                return apb_psc_table[(
 357                       (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 358                       >> RCC_CFGR_PPRE1_SHIFT)];
 359        else /* APB2 */
 360                return apb_psc_table[(
 361                       (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 362                       >> RCC_CFGR_PPRE2_SHIFT)];
 363};
 364
 365static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
 366                                enum apb apb)
 367{
 368        struct stm32_rcc_regs *regs = priv->base;
 369        u8 shift = stm32_get_apb_shift(regs, apb);
 370
 371        if (stm32_get_timpre(priv))
 372                /*
 373                 * if APB prescaler is configured to a
 374                 * division factor of 1, 2 or 4
 375                 */
 376                switch (shift) {
 377                case 0:
 378                case 1:
 379                case 2:
 380                        return stm32_get_hclk_rate(regs, sysclk);
 381                default:
 382                        return (sysclk >> shift) * 4;
 383                }
 384        else
 385                /*
 386                 * if APB prescaler is configured to a
 387                 * division factor of 1
 388                 */
 389                if (shift == 0)
 390                        return sysclk;
 391                else
 392                        return (sysclk >> shift) * 2;
 393};
 394
 395static ulong stm32_clk_get_rate(struct clk *clk)
 396{
 397        struct stm32_clk *priv = dev_get_priv(clk->dev);
 398        struct stm32_rcc_regs *regs = priv->base;
 399        u32 sysclk = 0;
 400        u32 vco;
 401        u32 sdmmcxsel_bit;
 402        u32 saidivr;
 403        u32 pllsai_rate;
 404        u16 pllm, plln, pllp, pllq;
 405
 406        if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
 407                        RCC_CFGR_SWS_PLL) {
 408                pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 409                plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 410                        >> RCC_PLLCFGR_PLLN_SHIFT);
 411                pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 412                        >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 413                pllq = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
 414                        >> RCC_PLLCFGR_PLLQ_SHIFT);
 415                vco = (priv->hse_rate / pllm) * plln;
 416                sysclk = vco / pllp;
 417        } else {
 418                return -EINVAL;
 419        }
 420
 421        switch (clk->id) {
 422        /*
 423         * AHB CLOCK: 3 x 32 bits consecutive registers are used :
 424         * AHB1, AHB2 and AHB3
 425         */
 426        case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
 427                return stm32_get_hclk_rate(regs, sysclk);
 428        /* APB1 CLOCK */
 429        case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
 430                /* For timer clock, an additionnal prescaler is used*/
 431                switch (clk->id) {
 432                case STM32F7_APB1_CLOCK(TIM2):
 433                case STM32F7_APB1_CLOCK(TIM3):
 434                case STM32F7_APB1_CLOCK(TIM4):
 435                case STM32F7_APB1_CLOCK(TIM5):
 436                case STM32F7_APB1_CLOCK(TIM6):
 437                case STM32F7_APB1_CLOCK(TIM7):
 438                case STM32F7_APB1_CLOCK(TIM12):
 439                case STM32F7_APB1_CLOCK(TIM13):
 440                case STM32F7_APB1_CLOCK(TIM14):
 441                        return stm32_get_timer_rate(priv, sysclk, APB1);
 442                }
 443                return (sysclk >> stm32_get_apb_shift(regs, APB1));
 444
 445        /* APB2 CLOCK */
 446        case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
 447                switch (clk->id) {
 448                /*
 449                 * particular case for SDMMC1 and SDMMC2 :
 450                 * 48Mhz source clock can be from main PLL or from
 451                 * PLLSAIP
 452                 */
 453                case STM32F7_APB2_CLOCK(SDMMC1):
 454                case STM32F7_APB2_CLOCK(SDMMC2):
 455                        if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
 456                                sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
 457                        else
 458                                sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
 459
 460                        if (readl(&regs->dckcfgr2) & sdmmcxsel_bit)
 461                                /* System clock is selected as SDMMC1 clock */
 462                                return sysclk;
 463                        /*
 464                         * 48 MHz can be generated by either PLLSAIP
 465                         * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
 466                         */
 467                        if (stm32_clk_get_ck48msel(priv))
 468                                return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
 469                        else
 470                                return (vco / pllq);
 471                        break;
 472
 473                /* For timer clock, an additionnal prescaler is used*/
 474                case STM32F7_APB2_CLOCK(TIM1):
 475                case STM32F7_APB2_CLOCK(TIM8):
 476                case STM32F7_APB2_CLOCK(TIM9):
 477                case STM32F7_APB2_CLOCK(TIM10):
 478                case STM32F7_APB2_CLOCK(TIM11):
 479                        return stm32_get_timer_rate(priv, sysclk, APB2);
 480                break;
 481
 482                /* particular case for LTDC clock */
 483                case STM32F7_APB2_CLOCK(LTDC):
 484                        saidivr = readl(&regs->dckcfgr);
 485                        saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
 486                                  >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
 487                        pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
 488
 489                        return pllsai_rate / pllsaidivr_table[saidivr];
 490                }
 491                return (sysclk >> stm32_get_apb_shift(regs, APB2));
 492
 493        default:
 494                dev_err(clk->dev, "clock index %ld out of range\n", clk->id);
 495                return -EINVAL;
 496        }
 497}
 498
 499static ulong stm32_set_rate(struct clk *clk, ulong rate)
 500{
 501#ifdef CONFIG_VIDEO_STM32
 502        struct stm32_clk *priv = dev_get_priv(clk->dev);
 503        struct stm32_rcc_regs *regs = priv->base;
 504        u32 pllsair_rate, pllsai_vco_rate, current_rate;
 505        u32 best_div, best_diff, diff;
 506        u16 div;
 507        u8 best_plldivr, best_pllsaidivr;
 508        u8 i, j;
 509        bool found = false;
 510
 511        /* Only set_rate for LTDC clock is implemented */
 512        if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
 513                dev_err(clk->dev,
 514                        "set_rate not implemented for clock index %ld\n",
 515                        clk->id);
 516                return 0;
 517        }
 518
 519        if (rate == stm32_clk_get_rate(clk))
 520                /* already set to requested rate */
 521                return rate;
 522
 523        /* get the current PLLSAIR output freq */
 524        pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
 525        best_div = pllsair_rate / rate;
 526
 527        /* look into pllsaidivr_table if this divider is available*/
 528        for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
 529                if (best_div == pllsaidivr_table[i]) {
 530                        /* set pll_saidivr with found value */
 531                        clrsetbits_le32(&regs->dckcfgr,
 532                                        RCC_DCKCFGR_PLLSAIDIVR_MASK,
 533                                        pllsaidivr_table[i]);
 534                        return rate;
 535                }
 536
 537        /*
 538         * As no pllsaidivr value is suitable to obtain requested freq,
 539         * test all combination of pllsaidivr * pllsair and find the one
 540         * which give freq closest to requested rate.
 541         */
 542
 543        pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
 544        best_diff = ULONG_MAX;
 545        best_pllsaidivr = 0;
 546        best_plldivr = 0;
 547        /*
 548         * start at index 2 of plldivr_table as divider value at index 0
 549         * and 1 are 0)
 550         */
 551        for (i = 2; i < sizeof(plldivr_table); i++) {
 552                for (j = 0; j < sizeof(pllsaidivr_table); j++) {
 553                        div = plldivr_table[i] * pllsaidivr_table[j];
 554                        current_rate = pllsai_vco_rate / div;
 555                        /* perfect combination is found ? */
 556                        if (current_rate == rate) {
 557                                best_pllsaidivr = j;
 558                                best_plldivr = i;
 559                                found = true;
 560                                break;
 561                        }
 562
 563                        diff = (current_rate > rate) ?
 564                               current_rate - rate : rate - current_rate;
 565
 566                        /* found a better combination ? */
 567                        if (diff < best_diff) {
 568                                best_diff = diff;
 569                                best_pllsaidivr = j;
 570                                best_plldivr = i;
 571                        }
 572                }
 573
 574                if (found)
 575                        break;
 576        }
 577
 578        /* Disable the SAI PLL */
 579        clrbits_le32(&regs->cr, RCC_CR_PLLSAION);
 580
 581        /* set pll_saidivr with found value */
 582        clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
 583                        best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
 584
 585        /* set pllsair with found value */
 586        clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
 587                        plldivr_table[best_plldivr]
 588                        << RCC_PLLSAICFGR_PLLSAIR_SHIFT);
 589
 590        /* Enable the SAI PLL */
 591        setbits_le32(&regs->cr, RCC_CR_PLLSAION);
 592        while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
 593                ;
 594
 595        div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
 596        return pllsai_vco_rate / div;
 597#else
 598        return 0;
 599#endif
 600}
 601
 602static int stm32_clk_enable(struct clk *clk)
 603{
 604        struct stm32_clk *priv = dev_get_priv(clk->dev);
 605        struct stm32_rcc_regs *regs = priv->base;
 606        u32 offset = clk->id / 32;
 607        u32 bit_index = clk->id % 32;
 608
 609        dev_dbg(clk->dev, "clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
 610                clk->id, offset, bit_index);
 611        setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
 612
 613        return 0;
 614}
 615
 616static int stm32_clk_probe(struct udevice *dev)
 617{
 618        struct ofnode_phandle_args args;
 619        struct udevice *fixed_clock_dev = NULL;
 620        struct clk clk;
 621        int err;
 622
 623        dev_dbg(dev, "%s\n", __func__);
 624
 625        struct stm32_clk *priv = dev_get_priv(dev);
 626        fdt_addr_t addr;
 627
 628        addr = dev_read_addr(dev);
 629        if (addr == FDT_ADDR_T_NONE)
 630                return -EINVAL;
 631
 632        priv->base = (struct stm32_rcc_regs *)addr;
 633        priv->pllsaip = true;
 634
 635        switch (dev_get_driver_data(dev)) {
 636        case STM32F42X:
 637                priv->pllsaip = false;
 638                /* fallback into STM32F469 case */
 639        case STM32F469:
 640                memcpy(&priv->info, &stm32f4_clk_info,
 641                       sizeof(struct stm32_clk_info));
 642                break;
 643
 644        case STM32F7:
 645                memcpy(&priv->info, &stm32f7_clk_info,
 646                       sizeof(struct stm32_clk_info));
 647                break;
 648        default:
 649                return -EINVAL;
 650        }
 651
 652        /* retrieve HSE frequency (external oscillator) */
 653        err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
 654                                        &fixed_clock_dev);
 655
 656        if (err) {
 657                dev_err(dev, "Can't find fixed clock (%d)", err);
 658                return err;
 659        }
 660
 661        err = clk_request(fixed_clock_dev, &clk);
 662        if (err) {
 663                dev_err(dev, "Can't request %s clk (%d)",
 664                        fixed_clock_dev->name, err);
 665                return err;
 666        }
 667
 668        /*
 669         * set pllm factor accordingly to the external oscillator
 670         * frequency (HSE). For STM32F4 and STM32F7, we want VCO
 671         * freq at 1MHz
 672         * if input PLL frequency is 25Mhz, divide it by 25
 673         */
 674        clk.id = 0;
 675        priv->hse_rate = clk_get_rate(&clk);
 676
 677        if (priv->hse_rate < 1000000) {
 678                dev_err(dev, "unexpected HSE clock rate = %ld \"n",
 679                        priv->hse_rate);
 680                return -EINVAL;
 681        }
 682
 683        priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
 684
 685        if (priv->info.has_overdrive) {
 686                err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
 687                                                 &args);
 688                if (err) {
 689                        dev_err(dev, "can't find syscon device (%d)\n", err);
 690                        return err;
 691                }
 692
 693                priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
 694        }
 695
 696        configure_clocks(dev);
 697
 698        return 0;
 699}
 700
 701static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 702{
 703        dev_dbg(clk->dev, "clk=%p\n", clk);
 704
 705        if (args->args_count != 2) {
 706                dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count);
 707                return -EINVAL;
 708        }
 709
 710        if (args->args_count)
 711                clk->id = args->args[1];
 712        else
 713                clk->id = 0;
 714
 715        return 0;
 716}
 717
 718static struct clk_ops stm32_clk_ops = {
 719        .of_xlate       = stm32_clk_of_xlate,
 720        .enable         = stm32_clk_enable,
 721        .get_rate       = stm32_clk_get_rate,
 722        .set_rate       = stm32_set_rate,
 723};
 724
 725U_BOOT_DRIVER(stm32fx_clk) = {
 726        .name                   = "stm32fx_rcc_clock",
 727        .id                     = UCLASS_CLK,
 728        .ops                    = &stm32_clk_ops,
 729        .probe                  = stm32_clk_probe,
 730        .priv_auto      = sizeof(struct stm32_clk),
 731        .flags                  = DM_FLAG_PRE_RELOC,
 732};
 733