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7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <log.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <dt-bindings/clock/imx6qdl-clock.h>
14
15#include "clk.h"
16
17static int imx6q_check_id(ulong id)
18{
19 if (id < IMX6QDL_CLK_DUMMY || id >= IMX6QDL_CLK_END) {
20 printf("%s: Invalid clk ID #%lu\n", __func__, id);
21 return -EINVAL;
22 }
23
24 return 0;
25}
26
27static ulong imx6q_clk_get_rate(struct clk *clk)
28{
29 struct clk *c;
30 int ret;
31
32 debug("%s(#%lu)\n", __func__, clk->id);
33
34 ret = imx6q_check_id(clk->id);
35 if (ret)
36 return ret;
37
38 ret = clk_get_by_id(clk->id, &c);
39 if (ret)
40 return ret;
41
42 return clk_get_rate(c);
43}
44
45static ulong imx6q_clk_set_rate(struct clk *clk, unsigned long rate)
46{
47 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
48
49 return rate;
50}
51
52static int __imx6q_clk_enable(struct clk *clk, bool enable)
53{
54 struct clk *c;
55 int ret = 0;
56
57 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
58
59 ret = imx6q_check_id(clk->id);
60 if (ret)
61 return ret;
62
63 ret = clk_get_by_id(clk->id, &c);
64 if (ret)
65 return ret;
66
67 if (enable)
68 ret = clk_enable(c);
69 else
70 ret = clk_disable(c);
71
72 return ret;
73}
74
75static int imx6q_clk_disable(struct clk *clk)
76{
77 return __imx6q_clk_enable(clk, 0);
78}
79
80static int imx6q_clk_enable(struct clk *clk)
81{
82 return __imx6q_clk_enable(clk, 1);
83}
84
85static struct clk_ops imx6q_clk_ops = {
86 .set_rate = imx6q_clk_set_rate,
87 .get_rate = imx6q_clk_get_rate,
88 .enable = imx6q_clk_enable,
89 .disable = imx6q_clk_disable,
90};
91
92static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
93static const char *const periph_sels[] = { "periph_pre", "periph_clk2", };
94static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
95 "pll2_pfd0_352m", "pll2_198m", };
96
97static int imx6q_clk_probe(struct udevice *dev)
98{
99 void *base;
100
101
102 base = (void *)ANATOP_BASE_ADDR;
103
104 clk_dm(IMX6QDL_CLK_PLL2,
105 imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
106 base + 0x30, 0x1));
107 clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
108 imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
109 base + 0x10, 0x3));
110 clk_dm(IMX6QDL_CLK_PLL3_60M,
111 imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
112 clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
113 imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
114 clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
115 imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
116 clk_dm(IMX6QDL_CLK_PLL6,
117 imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
118 clk_dm(IMX6QDL_CLK_PLL6_ENET,
119 imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
120
121
122 base = dev_read_addr_ptr(dev);
123 if (!base)
124 return -EINVAL;
125
126 clk_dm(IMX6QDL_CLK_USDHC1_SEL,
127 imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
128 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
129 clk_dm(IMX6QDL_CLK_USDHC2_SEL,
130 imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
131 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
132 clk_dm(IMX6QDL_CLK_USDHC3_SEL,
133 imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
134 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
135 clk_dm(IMX6QDL_CLK_USDHC4_SEL,
136 imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
137 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
138
139 clk_dm(IMX6QDL_CLK_USDHC1_PODF,
140 imx_clk_divider("usdhc1_podf", "usdhc1_sel",
141 base + 0x24, 11, 3));
142 clk_dm(IMX6QDL_CLK_USDHC2_PODF,
143 imx_clk_divider("usdhc2_podf", "usdhc2_sel",
144 base + 0x24, 16, 3));
145 clk_dm(IMX6QDL_CLK_USDHC3_PODF,
146 imx_clk_divider("usdhc3_podf", "usdhc3_sel",
147 base + 0x24, 19, 3));
148 clk_dm(IMX6QDL_CLK_USDHC4_PODF,
149 imx_clk_divider("usdhc4_podf", "usdhc4_sel",
150 base + 0x24, 22, 3));
151
152 clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
153 imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
154
155 clk_dm(IMX6QDL_CLK_ECSPI1,
156 imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
157 clk_dm(IMX6QDL_CLK_ECSPI2,
158 imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
159 clk_dm(IMX6QDL_CLK_ECSPI3,
160 imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
161 clk_dm(IMX6QDL_CLK_ECSPI4,
162 imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
163 clk_dm(IMX6QDL_CLK_USDHC1,
164 imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
165 clk_dm(IMX6QDL_CLK_USDHC2,
166 imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
167 clk_dm(IMX6QDL_CLK_USDHC3,
168 imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
169 clk_dm(IMX6QDL_CLK_USDHC4,
170 imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
171
172 clk_dm(IMX6QDL_CLK_PERIPH_PRE,
173 imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels,
174 ARRAY_SIZE(periph_pre_sels)));
175 clk_dm(IMX6QDL_CLK_PERIPH,
176 imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48,
177 5, periph_sels, ARRAY_SIZE(periph_sels)));
178 clk_dm(IMX6QDL_CLK_AHB,
179 imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3,
180 base + 0x48, 1));
181 clk_dm(IMX6QDL_CLK_IPG,
182 imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2));
183 clk_dm(IMX6QDL_CLK_IPG_PER,
184 imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6));
185 clk_dm(IMX6QDL_CLK_I2C1,
186 imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6));
187 clk_dm(IMX6QDL_CLK_I2C2,
188 imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
189
190 clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));
191 clk_dm(IMX6QDL_CLK_ENET_REF,
192 imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1));
193
194 return 0;
195}
196
197static const struct udevice_id imx6q_clk_ids[] = {
198 { .compatible = "fsl,imx6q-ccm" },
199 { },
200};
201
202U_BOOT_DRIVER(imx6q_clk) = {
203 .name = "clk_imx6q",
204 .id = UCLASS_CLK,
205 .of_match = imx6q_clk_ids,
206 .ops = &imx6q_clk_ops,
207 .probe = imx6q_clk_probe,
208 .flags = DM_FLAG_PRE_RELOC,
209};
210
