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6#include <common.h>
7#include <clk.h>
8#include <clk-uclass.h>
9#include <asm/io.h>
10#include <dm/device.h>
11#include <dm/devres.h>
12#include <dm/uclass.h>
13#include <dt-bindings/clock/microchip-mpfs-clock.h>
14#include <linux/err.h>
15
16#include "mpfs_clk.h"
17
18#define MPFS_PERIPH_CLOCK "mpfs_periph_clock"
19
20#define REG_CLOCK_CONFIG_CR 0x08
21#define REG_SUBBLK_CLOCK_CR 0x84
22#define REG_SUBBLK_RESET_CR 0x88
23
24#define CFG_CPU_SHIFT 0x0
25#define CFG_AXI_SHIFT 0x2
26#define CFG_AHB_SHIFT 0x4
27#define CFG_WIDTH 0x2
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35
36struct mpfs_periph_clock {
37 unsigned int id;
38 const char *name;
39 u8 shift;
40 unsigned long flags;
41};
42
43
44
45
46
47
48
49
50struct mpfs_periph_hw_clock {
51 struct mpfs_periph_clock periph;
52 void __iomem *sys_base;
53 u32 prate;
54 struct clk hw;
55};
56
57#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)
58
59static int mpfs_periph_clk_enable(struct clk *hw)
60{
61 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
62 struct mpfs_periph_clock *periph = &periph_hw->periph;
63 void __iomem *base_addr = periph_hw->sys_base;
64 u32 reg, val;
65
66 if (periph->flags != CLK_IS_CRITICAL) {
67 reg = readl(base_addr + REG_SUBBLK_RESET_CR);
68 val = reg & ~(1u << periph->shift);
69 writel(val, base_addr + REG_SUBBLK_RESET_CR);
70
71 reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
72 val = reg | (1u << periph->shift);
73 writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
74 }
75
76 return 0;
77}
78
79static int mpfs_periph_clk_disable(struct clk *hw)
80{
81 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
82 struct mpfs_periph_clock *periph = &periph_hw->periph;
83 void __iomem *base_addr = periph_hw->sys_base;
84 u32 reg, val;
85
86 if (periph->flags != CLK_IS_CRITICAL) {
87 reg = readl(base_addr + REG_SUBBLK_RESET_CR);
88 val = reg | (1u << periph->shift);
89 writel(val, base_addr + REG_SUBBLK_RESET_CR);
90
91 reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
92 val = reg & ~(1u << periph->shift);
93 writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
94 }
95
96 return 0;
97}
98
99static ulong mpfs_periph_clk_recalc_rate(struct clk *hw)
100{
101 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
102 void __iomem *base_addr = periph_hw->sys_base;
103 unsigned long rate;
104 u32 val;
105
106 val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> CFG_AHB_SHIFT;
107 val &= clk_div_mask(CFG_WIDTH);
108 rate = periph_hw->prate / (1u << val);
109 hw->rate = rate;
110
111 return rate;
112}
113
114#define CLK_PERIPH(_id, _name, _shift, _flags) { \
115 .periph.id = _id, \
116 .periph.name = _name, \
117 .periph.shift = _shift, \
118 .periph.flags = _flags, \
119 }
120
121static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
122 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", 0, CLK_IS_CRITICAL),
123 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", 1, 0),
124 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", 2, 0),
125 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", 3, 0),
126 CLK_PERIPH(CLK_TIMER, "clk_periph_timer", 4, 0),
127 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", 5, 0),
128 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", 6, 0),
129 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", 7, 0),
130 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", 8, 0),
131 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", 9, 0),
132 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", 10, 0),
133 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", 11, 0),
134 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", 12, 0),
135 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", 13, 0),
136 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", 14, 0),
137 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", 15, 0),
138 CLK_PERIPH(CLK_USB, "clk_periph_usb", 16, 0),
139 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", 18, 0),
140 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", 19, 0),
141 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", 20, 0),
142 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", 21, 0),
143 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", 22, 0),
144 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", 23, CLK_IS_CRITICAL),
145 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", 24, 0),
146 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", 25, 0),
147 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", 26, 0),
148 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", 27, 0),
149 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", 28, 0),
150 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", 29, 0),
151};
152
153int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
154 const char *parent_name)
155{
156 int ret;
157 int i, id, num_clks;
158 const char *name;
159 struct clk *hw;
160
161 num_clks = ARRAY_SIZE(mpfs_periph_clks);
162 for (i = 0; i < num_clks; i++) {
163 hw = &mpfs_periph_clks[i].hw;
164 mpfs_periph_clks[i].sys_base = base;
165 mpfs_periph_clks[i].prate = clk_rate;
166 name = mpfs_periph_clks[i].periph.name;
167 ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent_name);
168 if (ret)
169 ERR_PTR(ret);
170 id = mpfs_periph_clks[i].periph.id;
171 clk_dm(id, hw);
172 }
173
174 return 0;
175}
176
177const struct clk_ops mpfs_periph_clk_ops = {
178 .enable = mpfs_periph_clk_enable,
179 .disable = mpfs_periph_clk_disable,
180 .get_rate = mpfs_periph_clk_recalc_rate,
181};
182
183U_BOOT_DRIVER(mpfs_periph_clock) = {
184 .name = MPFS_PERIPH_CLOCK,
185 .id = UCLASS_CLK,
186 .ops = &mpfs_periph_clk_ops,
187};
188
