LXR uboot/drivers/clk/mpc83xx

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2018
   4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
   5 */
   6
   7/**
   8 * enum ratio - Description of a core clock ratio
   9 * @RAT_UNK:      Unknown ratio
  10 * @RAT_BYP:      Bypass
  11 * @RAT_1_TO_8:   Ratio 1:8
  12 * @RAT_1_TO_4:   Ratio 1:4
  13 * @RAT_1_TO_2:   Ratio 1:2
  14 * @RAT_1_TO_1:   Ratio 1:1
  15 * @RAT_1_5_TO_1: Ratio 1.5:1
  16 * @RAT_2_TO_1:   Ratio 2:1
  17 * @RAT_2_5_TO_1: Ratio 2.5:1
  18 * @RAT_3_TO_1:   Ratio 3:1
  19 */
  20#include <linux/bitops.h>
  21enum ratio {
  22        RAT_UNK,
  23        RAT_BYP,
  24        RAT_1_TO_8,
  25        RAT_1_TO_4,
  26        RAT_1_TO_2,
  27        RAT_1_TO_1,
  28        RAT_1_5_TO_1,
  29        RAT_2_TO_1,
  30        RAT_2_5_TO_1,
  31        RAT_3_TO_1
  32};
  33
  34/**
  35 * struct corecnf - Description for a core clock configuration
  36 * @core_csb_ratio: Core clock frequency to CSB clock frequency ratio
  37 * @vco_divider: VCO divider (Core VCO frequency = Core frequency * VCO divider)
  38 */
  39struct corecnf {
  40        int core_csb_ratio;
  41        int vco_divider;
  42};
  43
  44/*
  45 * Table with all valid Core CSB frequency ratio / VCO divider combinations as
  46 * indexed by the COREPLL field of the SPMR
  47 */
  48static const struct corecnf corecnf_tab[] = {
  49        {RAT_BYP, RAT_BYP},                     /* 0x00 */
  50        {RAT_BYP, RAT_BYP},                     /* 0x01 */
  51        {RAT_BYP, RAT_BYP},                     /* 0x02 */
  52        {RAT_BYP, RAT_BYP},                     /* 0x03 */
  53        {RAT_BYP, RAT_BYP},                     /* 0x04 */
  54        {RAT_BYP, RAT_BYP},                     /* 0x05 */
  55        {RAT_BYP, RAT_BYP},                     /* 0x06 */
  56        {RAT_BYP, RAT_BYP},                     /* 0x07 */
  57        {RAT_1_TO_1, RAT_1_TO_2},               /* 0x08 */
  58        {RAT_1_TO_1, RAT_1_TO_4},               /* 0x09 */
  59        {RAT_1_TO_1, RAT_1_TO_8},               /* 0x0A */
  60        {RAT_1_TO_1, RAT_1_TO_8},               /* 0x0B */
  61        {RAT_1_5_TO_1, RAT_1_TO_2},             /* 0x0C */
  62        {RAT_1_5_TO_1, RAT_1_TO_4},             /* 0x0D */
  63        {RAT_1_5_TO_1, RAT_1_TO_8},             /* 0x0E */
  64        {RAT_1_5_TO_1, RAT_1_TO_8},             /* 0x0F */
  65        {RAT_2_TO_1, RAT_1_TO_2},               /* 0x10 */
  66        {RAT_2_TO_1, RAT_1_TO_4},               /* 0x11 */
  67        {RAT_2_TO_1, RAT_1_TO_8},               /* 0x12 */
  68        {RAT_2_TO_1, RAT_1_TO_8},               /* 0x13 */
  69        {RAT_2_5_TO_1, RAT_1_TO_2},             /* 0x14 */
  70        {RAT_2_5_TO_1, RAT_1_TO_4},             /* 0x15 */
  71        {RAT_2_5_TO_1, RAT_1_TO_8},             /* 0x16 */
  72        {RAT_2_5_TO_1, RAT_1_TO_8},             /* 0x17 */
  73        {RAT_3_TO_1, RAT_1_TO_2},               /* 0x18 */
  74        {RAT_3_TO_1, RAT_1_TO_4},               /* 0x19 */
  75        {RAT_3_TO_1, RAT_1_TO_8},               /* 0x1A */
  76        {RAT_3_TO_1, RAT_1_TO_8},               /* 0x1B */
  77};
  78
  79/**
  80 * enum reg_type - Register to read a field from
  81 * @REG_SCCR: Use the SCCR register
  82 * @REG_SPMR: Use the SPMR register
  83 */
  84enum reg_type {
  85        REG_SCCR,
  86        REG_SPMR,
  87};
  88
  89/**
  90 * enum mode_type - Description of how to read a specific frequency value
  91 * @TYPE_INVALID: Unknown type, will provoke error
  92 * @TYPE_SCCR_STANDARD:        Read a field from the SCCR register, and use it
  93 *                             as a divider for the CSB clock to compute the
  94 *                             frequency
  95 * @TYPE_SCCR_ONOFF:           The field describes a bit flag that can turn the
  96 *                             clock on or off
  97 * @TYPE_SPMR_DIRECT_MULTIPLY: Read a field from the SPMR register, and use it
  98 *                             as a multiplier for the CSB clock to compute the
  99 *                             frequency
 100 * @TYPE_SPECIAL:              The frequency is calculated in a non-standard way
 101 */
 102enum mode_type {
 103        TYPE_INVALID = 0,
 104        TYPE_SCCR_STANDARD,
 105        TYPE_SCCR_ONOFF,
 106        TYPE_SPMR_DIRECT_MULTIPLY,
 107        TYPE_SPECIAL,
 108};
 109
 110/* Map of each clock index to its human-readable name */
 111static const char * const names[] = {
 112        [MPC83XX_CLK_CORE] = "Core",
 113        [MPC83XX_CLK_CSB] = "Coherent System Bus",
 114        [MPC83XX_CLK_QE] = "QE",
 115        [MPC83XX_CLK_BRG] = "BRG",
 116        [MPC83XX_CLK_LBIU] = "Local Bus Controller",
 117        [MPC83XX_CLK_LCLK] = "Local Bus",
 118        [MPC83XX_CLK_MEM] = "DDR",
 119        [MPC83XX_CLK_MEM_SEC] = "DDR Secondary",
 120        [MPC83XX_CLK_ENC] = "SEC",
 121        [MPC83XX_CLK_I2C1] = "I2C1",
 122        [MPC83XX_CLK_I2C2] = "I2C2",
 123        [MPC83XX_CLK_TDM] = "TDM",
 124        [MPC83XX_CLK_SDHC] = "SDHC",
 125        [MPC83XX_CLK_TSEC1] = "TSEC1",
 126        [MPC83XX_CLK_TSEC2] = "TSEC2",
 127        [MPC83XX_CLK_USBDR] = "USB DR",
 128        [MPC83XX_CLK_USBMPH] = "USB MPH",
 129        [MPC83XX_CLK_PCIEXP1] = "PCIEXP1",
 130        [MPC83XX_CLK_PCIEXP2] = "PCIEXP2",
 131        [MPC83XX_CLK_SATA] = "SATA",
 132        [MPC83XX_CLK_DMAC] = "DMAC",
 133        [MPC83XX_CLK_PCI] = "PCI",
 134};
 135
 136/**
 137 * struct clk_mode - Structure for clock mode descriiptions
 138 * @low:  The low bit of the data field to read for this mode (may not apply to
 139 *        some modes)
 140 * @high: The high bit of the data field to read for this mode (may not apply to
 141 *        some modes)
 142 * @type: The type of the mode description (one of enum mode_type)
 143 */
 144struct clk_mode {
 145        u8 low;
 146        u8 high;
 147        int type;
 148};
 149
 150/**
 151 * set_mode() - Build a clock mode description from data
 152 * @mode: The clock mode description to be filled out
 153 * @low:  The low bit of the data field to read for this mode (may not apply to
 154 *        some modes)
 155 * @high: The high bit of the data field to read for this mode (may not apply to
 156 *        some modes)
 157 * @type: The type of the mode description (one of enum mode_type)
 158 *
 159 * Clock mode descriptions are a succinct description of how to read a specific
 160 * clock's rate from the hardware; usually by reading a specific field of a
 161 * register, such a s the SCCR register, but some types use different methods
 162 * for obtaining the clock rate.
 163 */
 164static void set_mode(struct clk_mode *mode, u8 low, u8 high, int type)
 165{
 166        mode->low = low;
 167        mode->high = high;
 168        mode->type = type;
 169}
 170
 171/**
 172 * retrieve_mode() - Get the clock mode description for a specific clock
 173 * @clk:      The identifier of the clock for which the clock description should
 174 *            be retrieved
 175 * @soc_type: The type of MPC83xx SoC for which the clock description should be
 176 *            retrieved
 177 * @mode:     Pointer to a clk_mode structure to be filled with data for the
 178 *            clock
 179 *
 180 * Since some clock rate are stored in different places on different MPC83xx
 181 * SoCs, the SoC type has to be supplied along with the clock's identifier.
 182 *
 183 * Return: 0 if OK, -ve on error
 184 */
 185static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
 186{
 187        switch (clk) {
 188        case MPC83XX_CLK_CORE:
 189        case MPC83XX_CLK_CSB:
 190        case MPC83XX_CLK_QE:
 191        case MPC83XX_CLK_BRG:
 192        case MPC83XX_CLK_LCLK:
 193        case MPC83XX_CLK_I2C2:
 194                set_mode(mode, 0, 0, TYPE_SPECIAL);
 195                break;
 196        case MPC83XX_CLK_MEM:
 197                set_mode(mode, 1, 1, TYPE_SPMR_DIRECT_MULTIPLY);
 198                break;
 199        case MPC83XX_CLK_LBIU:
 200        case MPC83XX_CLK_MEM_SEC:
 201                set_mode(mode, 0, 0, TYPE_SPMR_DIRECT_MULTIPLY);
 202                break;
 203        case MPC83XX_CLK_TSEC1:
 204                set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
 205                break;
 206        case MPC83XX_CLK_TSEC2:
 207                if (soc_type == SOC_MPC8313) /* I2C and TSEC2 are the same register */
 208                        set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
 209                else /* FIXME(mario.six@gdsys.cc): This has separate enable/disable bit! */
 210                        set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
 211                break;
 212        case MPC83XX_CLK_SDHC:
 213                set_mode(mode, 4, 5, TYPE_SCCR_STANDARD);
 214                break;
 215        case MPC83XX_CLK_ENC:
 216                set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
 217                break;
 218        case MPC83XX_CLK_I2C1:
 219                if (soc_type == SOC_MPC8349)
 220                        set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
 221                else /* I2C and ENC are the same register */
 222                        set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
 223                break;
 224        case MPC83XX_CLK_PCIEXP1:
 225                set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
 226                break;
 227        case MPC83XX_CLK_PCIEXP2:
 228                set_mode(mode, 12, 13, TYPE_SCCR_STANDARD);
 229                break;
 230        case MPC83XX_CLK_USBDR:
 231                if (soc_type == SOC_MPC8313 || soc_type == SOC_MPC8349)
 232                        set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
 233                else
 234                        set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
 235                break;
 236        case MPC83XX_CLK_USBMPH:
 237                set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
 238                break;
 239        case MPC83XX_CLK_PCI:
 240                set_mode(mode, 15, 15, TYPE_SCCR_ONOFF);
 241                break;
 242        case MPC83XX_CLK_DMAC:
 243                set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
 244                break;
 245        case MPC83XX_CLK_SATA:
 246                /* FIXME(mario.six@gdsys.cc): All SATA controllers must have the same clock ratio */
 247                if (soc_type == SOC_MPC8379) {
 248                        set_mode(mode, 24, 25, TYPE_SCCR_STANDARD);
 249                        set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
 250                        set_mode(mode, 28, 29, TYPE_SCCR_STANDARD);
 251                        set_mode(mode, 30, 31, TYPE_SCCR_STANDARD);
 252                } else {
 253                        set_mode(mode, 18, 19, TYPE_SCCR_STANDARD);
 254                        set_mode(mode, 20, 21, TYPE_SCCR_STANDARD);
 255                }
 256                break;
 257        case MPC83XX_CLK_TDM:
 258                set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
 259                break;
 260        default:
 261                debug("%s: Unknown clock type %d on soc type %d\n",
 262                      __func__, clk, soc_type);
 263                set_mode(mode, 0, 0, TYPE_INVALID);
 264                return -EINVAL;
 265        }
 266
 267        return 0;
 268}
 269
 270/**
 271 * get_spmr() - Read the SPMR (System PLL Mode Register)
 272 * @im: Pointer to the MPC83xx main register map in question
 273 *
 274 * Return: The SPMR value as a 32-bit number.
 275 */
 276static inline u32 get_spmr(immap_t *im)
 277{
 278        u32 res = in_be32(&im->clk.spmr);
 279
 280        return res;
 281}
 282
 283/**
 284 * get_sccr() - Read the SCCR (System Clock Control Register)
 285 * @im: Pointer to the MPC83xx main register map in question
 286 *
 287 * Return: The SCCR value as a 32-bit number.
 288 */
 289static inline u32 get_sccr(immap_t *im)
 290{
 291        u32 res = in_be32(&im->clk.sccr);
 292
 293        return res;
 294}
 295
 296/**
 297 * get_lcrr() - Read the LCRR (Clock Ratio Register)
 298 * @im: Pointer to the MPC83xx main register map in question
 299 *
 300 * Return: The LCRR value as a 32-bit number.
 301 */
 302static inline u32 get_lcrr(immap_t *im)
 303{
 304        u32 res = in_be32(&im->im_lbc.lcrr);
 305
 306        return res;
 307}
 308
 309/**
 310 * get_pci_sync_in() - Read the PCI synchronization clock speed
 311 * @im: Pointer to the MPC83xx main register map in question
 312 *
 313 * Return: The PCI synchronization clock speed value as a 32-bit number.
 314 */
 315static inline u32 get_pci_sync_in(immap_t *im)
 316{
 317        u8 clkin_div;
 318
 319        clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT;
 320        return CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
 321}
 322
 323/**
 324 * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
 325 * @im: Pointer to the MPC83xx main register map in question
 326 *
 327 * Return: The CSB clock speed value as a 32-bit number.
 328 */
 329static inline u32 get_csb_clk(immap_t *im)
 330{
 331        u8 spmf;
 332
 333        spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 334        return CONFIG_SYS_CLK_FREQ * spmf;
 335}
 336
 337/**
 338 * spmr_field() - Read a specific SPMR field
 339 * @im:   Pointer to the MPC83xx main register map in question
 340 * @mask: A bitmask that describes the bitfield to be read
 341 *
 342 * Return: The value of the bit field as a 32-bit number.
 343 */
 344static inline uint spmr_field(immap_t *im, u32 mask)
 345{
 346        /* Extract shift from bitmask */
 347        uint shift = mask ? ffs(mask) - 1 : 0;
 348
 349        return (get_spmr(im) & mask) >> shift;
 350}
 351
 352/**
 353 * sccr_field() - Read a specific SCCR field
 354 * @im:   Pointer to the MPC83xx main register map in question
 355 * @mask: A bitmask that describes the bitfield to be read
 356 *
 357 * Return: The value of the bit field as a 32-bit number.
 358 */
 359static inline uint sccr_field(immap_t *im, u32 mask)
 360{
 361        /* Extract shift from bitmask */
 362        uint shift = mask ? ffs(mask) - 1 : 0;
 363
 364        return (get_sccr(im) & mask) >> shift;
 365}
 366
 367/**
 368 * lcrr_field() - Read a specific LCRR field
 369 * @im:   Pointer to the MPC83xx main register map in question
 370 * @mask: A bitmask that describes the bitfield to be read
 371 *
 372 * Return: The value of the bit field as a 32-bit number.
 373 */
 374static inline uint lcrr_field(immap_t *im, u32 mask)
 375{
 376        /* Extract shift from bitmask */
 377        uint shift = mask ? ffs(mask) - 1 : 0;
 378
 379        return (get_lcrr(im) & mask) >> shift;
 380}
 381