uboot/drivers/clk/renesas/r8a77965-cpg-mssr.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
   4 *
   5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
   6 *
   7 * Based on r8a7795-cpg-mssr.c
   8 *
   9 * Copyright (C) 2015 Glider bvba
  10 * Copyright (C) 2015 Renesas Electronics Corp.
  11 */
  12
  13#include <common.h>
  14#include <clk-uclass.h>
  15#include <dm.h>
  16#include <linux/bitops.h>
  17
  18#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
  19
  20#include "renesas-cpg-mssr.h"
  21#include "rcar-gen3-cpg.h"
  22
  23enum clk_ids {
  24        /* Core Clock Outputs exported to DT */
  25        LAST_DT_CORE_CLK = R8A77965_CLK_OSC,
  26
  27        /* External Input Clocks */
  28        CLK_EXTAL,
  29        CLK_EXTALR,
  30
  31        /* Internal Core Clocks */
  32        CLK_MAIN,
  33        CLK_PLL0,
  34        CLK_PLL1,
  35        CLK_PLL3,
  36        CLK_PLL4,
  37        CLK_PLL1_DIV2,
  38        CLK_PLL1_DIV4,
  39        CLK_S0,
  40        CLK_S1,
  41        CLK_S2,
  42        CLK_S3,
  43        CLK_SDSRC,
  44        CLK_SSPSRC,
  45        CLK_RPCSRC,
  46        CLK_RINT,
  47
  48        /* Module Clocks */
  49        MOD_CLK_BASE
  50};
  51
  52static const struct cpg_core_clk r8a77965_core_clks[] = {
  53        /* External Clock Inputs */
  54        DEF_INPUT("extal",      CLK_EXTAL),
  55        DEF_INPUT("extalr",     CLK_EXTALR),
  56
  57        /* Internal Core Clocks */
  58        DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  59        DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  60        DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  61        DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  62        DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
  63
  64        DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,          CLK_PLL1,       2, 1),
  65        DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,          CLK_PLL1_DIV2,  2, 1),
  66        DEF_FIXED(".s0",        CLK_S0,                 CLK_PLL1_DIV2,  2, 1),
  67        DEF_FIXED(".s1",        CLK_S1,                 CLK_PLL1_DIV2,  3, 1),
  68        DEF_FIXED(".s2",        CLK_S2,                 CLK_PLL1_DIV2,  4, 1),
  69        DEF_FIXED(".s3",        CLK_S3,                 CLK_PLL1_DIV2,  6, 1),
  70        DEF_FIXED(".sdsrc",     CLK_SDSRC,              CLK_PLL1_DIV2,  2, 1),
  71        DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
  72
  73        DEF_BASE("rpc",         R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
  74                 CLK_RPCSRC),
  75        DEF_BASE("rpcd2",       R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
  76                 R8A77965_CLK_RPC),
  77
  78        DEF_GEN3_OSC(".r",      CLK_RINT,               CLK_EXTAL,      32),
  79
  80        /* Core Clock Outputs */
  81        DEF_GEN3_Z("z",         R8A77965_CLK_Z,         CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
  82        DEF_FIXED("ztr",        R8A77965_CLK_ZTR,       CLK_PLL1_DIV2,  6, 1),
  83        DEF_FIXED("ztrd2",      R8A77965_CLK_ZTRD2,     CLK_PLL1_DIV2,  12, 1),
  84        DEF_FIXED("zt",         R8A77965_CLK_ZT,        CLK_PLL1_DIV2,  4, 1),
  85        DEF_FIXED("zx",         R8A77965_CLK_ZX,        CLK_PLL1_DIV2,  2, 1),
  86        DEF_FIXED("s0d1",       R8A77965_CLK_S0D1,      CLK_S0,         1, 1),
  87        DEF_FIXED("s0d2",       R8A77965_CLK_S0D2,      CLK_S0,         2, 1),
  88        DEF_FIXED("s0d3",       R8A77965_CLK_S0D3,      CLK_S0,         3, 1),
  89        DEF_FIXED("s0d4",       R8A77965_CLK_S0D4,      CLK_S0,         4, 1),
  90        DEF_FIXED("s0d6",       R8A77965_CLK_S0D6,      CLK_S0,         6, 1),
  91        DEF_FIXED("s0d8",       R8A77965_CLK_S0D8,      CLK_S0,         8, 1),
  92        DEF_FIXED("s0d12",      R8A77965_CLK_S0D12,     CLK_S0,         12, 1),
  93        DEF_FIXED("s1d1",       R8A77965_CLK_S1D1,      CLK_S1,         1, 1),
  94        DEF_FIXED("s1d2",       R8A77965_CLK_S1D2,      CLK_S1,         2, 1),
  95        DEF_FIXED("s1d4",       R8A77965_CLK_S1D4,      CLK_S1,         4, 1),
  96        DEF_FIXED("s2d1",       R8A77965_CLK_S2D1,      CLK_S2,         1, 1),
  97        DEF_FIXED("s2d2",       R8A77965_CLK_S2D2,      CLK_S2,         2, 1),
  98        DEF_FIXED("s2d4",       R8A77965_CLK_S2D4,      CLK_S2,         4, 1),
  99        DEF_FIXED("s3d1",       R8A77965_CLK_S3D1,      CLK_S3,         1, 1),
 100        DEF_FIXED("s3d2",       R8A77965_CLK_S3D2,      CLK_S3,         2, 1),
 101        DEF_FIXED("s3d4",       R8A77965_CLK_S3D4,      CLK_S3,         4, 1),
 102
 103        DEF_GEN3_SD("sd0",      R8A77965_CLK_SD0,       CLK_SDSRC,      0x074),
 104        DEF_GEN3_SD("sd1",      R8A77965_CLK_SD1,       CLK_SDSRC,      0x078),
 105        DEF_GEN3_SD("sd2",      R8A77965_CLK_SD2,       CLK_SDSRC,      0x268),
 106        DEF_GEN3_SD("sd3",      R8A77965_CLK_SD3,       CLK_SDSRC,      0x26c),
 107
 108        DEF_FIXED("cl",         R8A77965_CLK_CL,        CLK_PLL1_DIV2, 48, 1),
 109        DEF_FIXED("cr",         R8A77965_CLK_CR,        CLK_PLL1_DIV4,  2, 1),
 110        DEF_FIXED("cp",         R8A77965_CLK_CP,        CLK_EXTAL,      2, 1),
 111        DEF_FIXED("cpex",       R8A77965_CLK_CPEX,      CLK_EXTAL,      2, 1),
 112
 113        DEF_DIV6P1("canfd",     R8A77965_CLK_CANFD,     CLK_PLL1_DIV4,  0x244),
 114        DEF_DIV6P1("csi0",      R8A77965_CLK_CSI0,      CLK_PLL1_DIV4,  0x00c),
 115        DEF_DIV6P1("mso",       R8A77965_CLK_MSO,       CLK_PLL1_DIV4,  0x014),
 116        DEF_DIV6P1("hdmi",      R8A77965_CLK_HDMI,      CLK_PLL1_DIV4,  0x250),
 117
 118        DEF_GEN3_OSC("osc",     R8A77965_CLK_OSC,       CLK_EXTAL,      8),
 119
 120        DEF_BASE("r",           R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
 121};
 122
 123static const struct mssr_mod_clk r8a77965_mod_clks[] = {
 124        DEF_MOD("fdp1-0",               119,    R8A77965_CLK_S0D1),
 125        DEF_MOD("tmu4",                 121,    R8A77965_CLK_S0D6),
 126        DEF_MOD("tmu3",                 122,    R8A77965_CLK_S3D2),
 127        DEF_MOD("tmu2",                 123,    R8A77965_CLK_S3D2),
 128        DEF_MOD("tmu1",                 124,    R8A77965_CLK_S3D2),
 129        DEF_MOD("tmu0",                 125,    R8A77965_CLK_CP),
 130        DEF_MOD("scif5",                202,    R8A77965_CLK_S3D4),
 131        DEF_MOD("scif4",                203,    R8A77965_CLK_S3D4),
 132        DEF_MOD("scif3",                204,    R8A77965_CLK_S3D4),
 133        DEF_MOD("scif1",                206,    R8A77965_CLK_S3D4),
 134        DEF_MOD("scif0",                207,    R8A77965_CLK_S3D4),
 135        DEF_MOD("msiof3",               208,    R8A77965_CLK_MSO),
 136        DEF_MOD("msiof2",               209,    R8A77965_CLK_MSO),
 137        DEF_MOD("msiof1",               210,    R8A77965_CLK_MSO),
 138        DEF_MOD("msiof0",               211,    R8A77965_CLK_MSO),
 139        DEF_MOD("sys-dmac2",            217,    R8A77965_CLK_S3D1),
 140        DEF_MOD("sys-dmac1",            218,    R8A77965_CLK_S3D1),
 141        DEF_MOD("sys-dmac0",            219,    R8A77965_CLK_S0D3),
 142        DEF_MOD("sceg-pub",             229,    R8A77965_CLK_CR),
 143
 144        DEF_MOD("cmt3",                 300,    R8A77965_CLK_R),
 145        DEF_MOD("cmt2",                 301,    R8A77965_CLK_R),
 146        DEF_MOD("cmt1",                 302,    R8A77965_CLK_R),
 147        DEF_MOD("cmt0",                 303,    R8A77965_CLK_R),
 148        DEF_MOD("tpu0",                 304,    R8A77965_CLK_S3D4),
 149        DEF_MOD("scif2",                310,    R8A77965_CLK_S3D4),
 150        DEF_MOD("sdif3",                311,    R8A77965_CLK_SD3),
 151        DEF_MOD("sdif2",                312,    R8A77965_CLK_SD2),
 152        DEF_MOD("sdif1",                313,    R8A77965_CLK_SD1),
 153        DEF_MOD("sdif0",                314,    R8A77965_CLK_SD0),
 154        DEF_MOD("pcie1",                318,    R8A77965_CLK_S3D1),
 155        DEF_MOD("pcie0",                319,    R8A77965_CLK_S3D1),
 156        DEF_MOD("usb3-if0",             328,    R8A77965_CLK_S3D1),
 157        DEF_MOD("usb-dmac0",            330,    R8A77965_CLK_S3D1),
 158        DEF_MOD("usb-dmac1",            331,    R8A77965_CLK_S3D1),
 159
 160        DEF_MOD("rwdt",                 402,    R8A77965_CLK_R),
 161        DEF_MOD("intc-ex",              407,    R8A77965_CLK_CP),
 162        DEF_MOD("intc-ap",              408,    R8A77965_CLK_S0D3),
 163
 164        DEF_MOD("audmac1",              501,    R8A77965_CLK_S1D2),
 165        DEF_MOD("audmac0",              502,    R8A77965_CLK_S1D2),
 166        DEF_MOD("drif31",               508,    R8A77965_CLK_S3D2),
 167        DEF_MOD("drif30",               509,    R8A77965_CLK_S3D2),
 168        DEF_MOD("drif21",               510,    R8A77965_CLK_S3D2),
 169        DEF_MOD("drif20",               511,    R8A77965_CLK_S3D2),
 170        DEF_MOD("drif11",               512,    R8A77965_CLK_S3D2),
 171        DEF_MOD("drif10",               513,    R8A77965_CLK_S3D2),
 172        DEF_MOD("drif01",               514,    R8A77965_CLK_S3D2),
 173        DEF_MOD("drif00",               515,    R8A77965_CLK_S3D2),
 174        DEF_MOD("hscif4",               516,    R8A77965_CLK_S3D1),
 175        DEF_MOD("hscif3",               517,    R8A77965_CLK_S3D1),
 176        DEF_MOD("hscif2",               518,    R8A77965_CLK_S3D1),
 177        DEF_MOD("hscif1",               519,    R8A77965_CLK_S3D1),
 178        DEF_MOD("hscif0",               520,    R8A77965_CLK_S3D1),
 179        DEF_MOD("thermal",              522,    R8A77965_CLK_CP),
 180        DEF_MOD("pwm",                  523,    R8A77965_CLK_S0D12),
 181
 182        DEF_MOD("fcpvd1",               602,    R8A77965_CLK_S0D2),
 183        DEF_MOD("fcpvd0",               603,    R8A77965_CLK_S0D2),
 184        DEF_MOD("fcpvb0",               607,    R8A77965_CLK_S0D1),
 185        DEF_MOD("fcpvi0",               611,    R8A77965_CLK_S0D1),
 186        DEF_MOD("fcpf0",                615,    R8A77965_CLK_S0D1),
 187        DEF_MOD("fcpcs",                619,    R8A77965_CLK_S0D2),
 188        DEF_MOD("vspd1",                622,    R8A77965_CLK_S0D2),
 189        DEF_MOD("vspd0",                623,    R8A77965_CLK_S0D2),
 190        DEF_MOD("vspb",                 626,    R8A77965_CLK_S0D1),
 191        DEF_MOD("vspi0",                631,    R8A77965_CLK_S0D1),
 192
 193        DEF_MOD("ehci1",                702,    R8A77965_CLK_S3D2),
 194        DEF_MOD("ehci0",                703,    R8A77965_CLK_S3D2),
 195        DEF_MOD("hsusb",                704,    R8A77965_CLK_S3D2),
 196        DEF_MOD("cmm3",                 708,    R8A77965_CLK_S2D1),
 197        DEF_MOD("cmm1",                 710,    R8A77965_CLK_S2D1),
 198        DEF_MOD("cmm0",                 711,    R8A77965_CLK_S2D1),
 199        DEF_MOD("csi20",                714,    R8A77965_CLK_CSI0),
 200        DEF_MOD("csi40",                716,    R8A77965_CLK_CSI0),
 201        DEF_MOD("du3",                  721,    R8A77965_CLK_S2D1),
 202        DEF_MOD("du1",                  723,    R8A77965_CLK_S2D1),
 203        DEF_MOD("du0",                  724,    R8A77965_CLK_S2D1),
 204        DEF_MOD("lvds",                 727,    R8A77965_CLK_S2D1),
 205        DEF_MOD("hdmi0",                729,    R8A77965_CLK_HDMI),
 206
 207        DEF_MOD("vin7",                 804,    R8A77965_CLK_S0D2),
 208        DEF_MOD("vin6",                 805,    R8A77965_CLK_S0D2),
 209        DEF_MOD("vin5",                 806,    R8A77965_CLK_S0D2),
 210        DEF_MOD("vin4",                 807,    R8A77965_CLK_S0D2),
 211        DEF_MOD("vin3",                 808,    R8A77965_CLK_S0D2),
 212        DEF_MOD("vin2",                 809,    R8A77965_CLK_S0D2),
 213        DEF_MOD("vin1",                 810,    R8A77965_CLK_S0D2),
 214        DEF_MOD("vin0",                 811,    R8A77965_CLK_S0D2),
 215        DEF_MOD("etheravb",             812,    R8A77965_CLK_S0D6),
 216        DEF_MOD("sata0",                815,    R8A77965_CLK_S3D2),
 217        DEF_MOD("imr1",                 822,    R8A77965_CLK_S0D2),
 218        DEF_MOD("imr0",                 823,    R8A77965_CLK_S0D2),
 219
 220        DEF_MOD("gpio7",                905,    R8A77965_CLK_S3D4),
 221        DEF_MOD("gpio6",                906,    R8A77965_CLK_S3D4),
 222        DEF_MOD("gpio5",                907,    R8A77965_CLK_S3D4),
 223        DEF_MOD("gpio4",                908,    R8A77965_CLK_S3D4),
 224        DEF_MOD("gpio3",                909,    R8A77965_CLK_S3D4),
 225        DEF_MOD("gpio2",                910,    R8A77965_CLK_S3D4),
 226        DEF_MOD("gpio1",                911,    R8A77965_CLK_S3D4),
 227        DEF_MOD("gpio0",                912,    R8A77965_CLK_S3D4),
 228        DEF_MOD("can-fd",               914,    R8A77965_CLK_S3D2),
 229        DEF_MOD("can-if1",              915,    R8A77965_CLK_S3D4),
 230        DEF_MOD("can-if0",              916,    R8A77965_CLK_S3D4),
 231        DEF_MOD("rpc-if",               917,    R8A77965_CLK_RPCD2),
 232        DEF_MOD("i2c6",                 918,    R8A77965_CLK_S0D6),
 233        DEF_MOD("i2c5",                 919,    R8A77965_CLK_S0D6),
 234        DEF_MOD("i2c-dvfs",             926,    R8A77965_CLK_CP),
 235        DEF_MOD("i2c4",                 927,    R8A77965_CLK_S0D6),
 236        DEF_MOD("i2c3",                 928,    R8A77965_CLK_S0D6),
 237        DEF_MOD("i2c2",                 929,    R8A77965_CLK_S3D2),
 238        DEF_MOD("i2c1",                 930,    R8A77965_CLK_S3D2),
 239        DEF_MOD("i2c0",                 931,    R8A77965_CLK_S3D2),
 240
 241        DEF_MOD("ssi-all",              1005,   R8A77965_CLK_S3D4),
 242        DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 243        DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 244        DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 245        DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 246        DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 247        DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 248        DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 249        DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 250        DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 251        DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 252        DEF_MOD("scu-all",              1017,   R8A77965_CLK_S3D4),
 253        DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 254        DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 255        DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 256        DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 257        DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 258        DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 259        DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 260        DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 261        DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 262        DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 263        DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 264        DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 265        DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 266        DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 267};
 268
 269/*
 270 * CPG Clock Data
 271 */
 272
 273/*
 274 *   MD         EXTAL           PLL0    PLL1    PLL3    PLL4    OSC
 275 * 14 13 19 17  (MHz)
 276 *-----------------------------------------------------------------
 277 * 0  0  0  0   16.66 x 1       x180    x192    x192    x144    /16
 278 * 0  0  0  1   16.66 x 1       x180    x192    x128    x144    /16
 279 * 0  0  1  0   Prohibited setting
 280 * 0  0  1  1   16.66 x 1       x180    x192    x192    x144    /16
 281 * 0  1  0  0   20    x 1       x150    x160    x160    x120    /19
 282 * 0  1  0  1   20    x 1       x150    x160    x106    x120    /19
 283 * 0  1  1  0   Prohibited setting
 284 * 0  1  1  1   20    x 1       x150    x160    x160    x120    /19
 285 * 1  0  0  0   25    x 1       x120    x128    x128    x96     /24
 286 * 1  0  0  1   25    x 1       x120    x128    x84     x96     /24
 287 * 1  0  1  0   Prohibited setting
 288 * 1  0  1  1   25    x 1       x120    x128    x128    x96     /24
 289 * 1  1  0  0   33.33 / 2       x180    x192    x192    x144    /32
 290 * 1  1  0  1   33.33 / 2       x180    x192    x128    x144    /32
 291 * 1  1  1  0   Prohibited setting
 292 * 1  1  1  1   33.33 / 2       x180    x192    x192    x144    /32
 293 */
 294#define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 11) | \
 295                                         (((md) & BIT(13)) >> 11) | \
 296                                         (((md) & BIT(19)) >> 18) | \
 297                                         (((md) & BIT(17)) >> 17))
 298
 299static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
 300        /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
 301        { 1,            192,    1,      192,    1,      16,     },
 302        { 1,            192,    1,      128,    1,      16,     },
 303        { 0, /* Prohibited setting */                           },
 304        { 1,            192,    1,      192,    1,      16,     },
 305        { 1,            160,    1,      160,    1,      19,     },
 306        { 1,            160,    1,      106,    1,      19,     },
 307        { 0, /* Prohibited setting */                           },
 308        { 1,            160,    1,      160,    1,      19,     },
 309        { 1,            128,    1,      128,    1,      24,     },
 310        { 1,            128,    1,      84,     1,      24,     },
 311        { 0, /* Prohibited setting */                           },
 312        { 1,            128,    1,      128,    1,      24,     },
 313        { 2,            192,    1,      192,    1,      32,     },
 314        { 2,            192,    1,      128,    1,      32,     },
 315        { 0, /* Prohibited setting */                           },
 316        { 2,            192,    1,      192,    1,      32,     },
 317};
 318
 319static const struct mstp_stop_table r8a77965_mstp_table[] = {
 320        { 0x00210000, 0x0, 0x00210000, 0 },
 321        { 0xc3e813a0, 0x0, 0xc3e813a0, 0 },
 322        { 0x040e2fdc, 0x2000, 0x040e2fdc, 0 },
 323        { 0xd0cc7cdf, 0x400, 0xd0cc7cdf, 0 },
 324        { 0x80000004, 0x180, 0x80000004, 0 },
 325        { 0x40dfff46, 0x0, 0x40dfff46, 0 },
 326        { 0x84c8888c, 0x0, 0x84c8888c, 0 },
 327        { 0x29bf5d1c, 0x0, 0x29bf5d1c, 0 },
 328        { 0x00c09ff7, 0x0, 0x01c09ff7, 0 },
 329        { 0xfddfdffe, 0x0, 0xfddfdffe, 0 },
 330        { 0xfffeffe0, 0x0, 0xfffeffe0, 0 },
 331        { 0x00000000, 0x0, 0x00000000, 0 },
 332};
 333
 334static const void *r8a77965_get_pll_config(const u32 cpg_mode)
 335{
 336        return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 337}
 338
 339static const struct cpg_mssr_info r8a77965_cpg_mssr_info = {
 340        .core_clk               = r8a77965_core_clks,
 341        .core_clk_size          = ARRAY_SIZE(r8a77965_core_clks),
 342        .mod_clk                = r8a77965_mod_clks,
 343        .mod_clk_size           = ARRAY_SIZE(r8a77965_mod_clks),
 344        .mstp_table             = r8a77965_mstp_table,
 345        .mstp_table_size        = ARRAY_SIZE(r8a77965_mstp_table),
 346        .reset_node             = "renesas,r8a77965-rst",
 347        .reset_modemr_offset    = CPG_RST_MODEMR,
 348        .extalr_node            = "extalr",
 349        .mod_clk_base           = MOD_CLK_BASE,
 350        .clk_extal_id           = CLK_EXTAL,
 351        .clk_extalr_id          = CLK_EXTALR,
 352        .get_pll_config         = r8a77965_get_pll_config,
 353};
 354
 355static const struct udevice_id r8a77965_clk_ids[] = {
 356        {
 357                .compatible     = "renesas,r8a77965-cpg-mssr",
 358                .data           = (ulong)&r8a77965_cpg_mssr_info,
 359        },
 360        { }
 361};
 362
 363U_BOOT_DRIVER(clk_r8a77965) = {
 364        .name           = "clk_r8a77965",
 365        .id             = UCLASS_CLK,
 366        .of_match       = r8a77965_clk_ids,
 367        .priv_auto      = sizeof(struct gen3_clk_priv),
 368        .ops            = &gen3_clk_ops,
 369        .probe          = gen3_clk_probe,
 370        .remove         = gen3_clk_remove,
 371};
 372