LXR uboot/drivers/ddr/marvell/a38x/ddr3

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) Marvell International Ltd. and its affiliates
   4 */
   5
   6#include "ddr3_init.h"
   7#include "mv_ddr_common.h"
   8
   9static char *ddr_type = "DDR3";
  10
  11/*
  12 * generic_init_controller controls D-unit configuration:
  13 * '1' - dynamic D-unit configuration,
  14 */
  15u8 generic_init_controller = 1;
  16
  17static int mv_ddr_training_params_set(u8 dev_num);
  18
  19/*
  20 * Name:     ddr3_init - Main DDR3 Init function
  21 * Desc:     This routine initialize the DDR3 MC and runs HW training.
  22 * Args:     None.
  23 * Notes:
  24 * Returns:  None.
  25 */
  26int ddr3_init(void)
  27{
  28        int status;
  29        int is_manual_cal_done;
  30
  31        /* Print mv_ddr version */
  32        mv_ddr_ver_print();
  33
  34        mv_ddr_pre_training_fixup();
  35
  36        /* SoC/Board special initializations */
  37        mv_ddr_pre_training_soc_config(ddr_type);
  38
  39        /* Set log level for training library */
  40        mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
  41
  42        mv_ddr_early_init();
  43
  44        if (mv_ddr_topology_map_update()) {
  45                printf("mv_ddr: failed to update topology\n");
  46                return MV_FAIL;
  47        }
  48
  49        if (mv_ddr_early_init2() != MV_OK)
  50                return MV_FAIL;
  51
  52        /* Set training algorithm's parameters */
  53        status = mv_ddr_training_params_set(0);
  54        if (MV_OK != status)
  55                return status;
  56
  57        mv_ddr_mc_config();
  58
  59        is_manual_cal_done = mv_ddr_manual_cal_do();
  60
  61        mv_ddr_mc_init();
  62
  63        if (!is_manual_cal_done) {
  64        }
  65
  66
  67        status = ddr3_silicon_post_init();
  68        if (MV_OK != status) {
  69                printf("DDR3 Post Init - FAILED 0x%x\n", status);
  70                return status;
  71        }
  72
  73        /* PHY initialization (Training) */
  74        status = hws_ddr3_tip_run_alg(0, ALGO_TYPE_DYNAMIC);
  75        if (MV_OK != status) {
  76                printf("%s Training Sequence - FAILED\n", ddr_type);
  77                return status;
  78        }
  79
  80
  81        /* Post MC/PHY initializations */
  82        mv_ddr_post_training_soc_config(ddr_type);
  83
  84        mv_ddr_post_training_fixup();
  85
  86        if (mv_ddr_is_ecc_ena())
  87                mv_ddr_mem_scrubbing();
  88
  89        printf("mv_ddr: completed successfully\n");
  90
  91        return MV_OK;
  92}
  93
  94/*
  95 * Name:        mv_ddr_training_params_set
  96 * Desc:
  97 * Args:
  98 * Notes:       sets internal training params
  99 * Returns:
 100 */
 101static int mv_ddr_training_params_set(u8 dev_num)
 102{
 103        struct tune_train_params params;
 104        struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 105        int status;
 106        u32 cs_num;
 107        int ck_delay;
 108
 109        cs_num = mv_ddr_cs_num_get();
 110        ck_delay = mv_ddr_ck_delay_get();
 111
 112        /* NOTE: do not remove any field initilization */
 113        params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
 114        params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
 115        params.g_zpri_data = TUNE_TRAINING_PARAMS_PRI_DATA;
 116        params.g_znri_data = TUNE_TRAINING_PARAMS_NRI_DATA;
 117        params.g_zpri_ctrl = TUNE_TRAINING_PARAMS_PRI_CTRL;
 118        params.g_znri_ctrl = TUNE_TRAINING_PARAMS_NRI_CTRL;
 119        params.g_znodt_data = TUNE_TRAINING_PARAMS_N_ODT_DATA;
 120        params.g_zpodt_ctrl = TUNE_TRAINING_PARAMS_P_ODT_CTRL;
 121        params.g_znodt_ctrl = TUNE_TRAINING_PARAMS_N_ODT_CTRL;
 122
 123        params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA;
 124        params.g_dic = TUNE_TRAINING_PARAMS_DIC;
 125        params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM;
 126        if (cs_num == 1) {
 127                params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS;
 128                params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS;
 129        } else {
 130                params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS;
 131                params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
 132        }
 133
 134        if (ck_delay > 0)
 135                params.ck_delay = ck_delay;
 136
 137        /* Use platform specific override ODT value */
 138        if (tm->odt_config)
 139                params.g_odt_config = tm->odt_config;
 140
 141        status = ddr3_tip_tune_training_params(dev_num, &params);
 142        if (MV_OK != status) {
 143                printf("%s Training Sequence - FAILED\n", ddr_type);
 144                return status;
 145        }
 146
 147        return MV_OK;
 148}
 149