1
2
3
4
5
6#ifndef _DDR3_TRAINING_IP_BIST_H_
7#define _DDR3_TRAINING_IP_BIST_H_
8
9#include "ddr3_training_ip.h"
10
11enum hws_bist_operation {
12 BIST_STOP = 0,
13 BIST_START = 1
14};
15
16enum hws_stress_jump {
17 STRESS_NONE = 0,
18 STRESS_ENABLE = 1
19};
20
21enum hws_pattern_duration {
22 DURATION_SINGLE = 0,
23 DURATION_STOP_AT_FAIL = 1,
24 DURATION_ADDRESS = 2,
25 DURATION_CONT = 4
26};
27
28struct bist_result {
29 u32 bist_error_cnt;
30 u32 bist_fail_low;
31 u32 bist_fail_high;
32 u32 bist_last_fail_addr;
33};
34
35int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
36 struct bist_result *pst_bist_result);
37int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
38 enum hws_access_type access_type,
39 u32 if_num, enum hws_dir direction,
40 enum hws_stress_jump addr_stress_jump,
41 enum hws_pattern_duration duration,
42 enum hws_bist_operation oper_type,
43 u32 offset, u32 cs_num, u32 pattern_addr_length);
44int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
45 u32 cs_num);
46int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
47 u32 mode);
48int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num,
49 u32 direction, u32 mode);
50int ddr3_tip_print_regs(u32 dev_num);
51int ddr3_tip_reg_dump(u32 dev_num);
52int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
53 u32 burst_length);
54int mv_ddr_dm_to_dq_diff_get(u8 adll_byte_high, u8 adll_byte_low, u8 *vw_vector,
55 int *delta_h_adll, int *delta_l_adll);
56int mv_ddr_dm_vw_get(enum hws_pattern pattern, u32 cs, u8 *vw_vector);
57#endif
58
