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14#include <common.h>
15#include <fpga.h>
16#include <log.h>
17#include <virtex2.h>
18#include <spartan2.h>
19#include <spartan3.h>
20#include <zynqpl.h>
21
22
23static int xilinx_validate(xilinx_desc *desc, char *fn);
24
25
26
27int fpga_is_partial_data(int devnum, size_t img_len)
28{
29 const fpga_desc * const desc = fpga_get_desc(devnum);
30 xilinx_desc *desc_xilinx = desc->devdesc;
31
32
33 if (img_len >= desc_xilinx->size)
34 return 0;
35
36
37 return 1;
38}
39
40int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
41 bitstream_type bstype)
42{
43 unsigned int length;
44 unsigned int swapsize;
45 unsigned char *dataptr;
46 unsigned int i;
47 const fpga_desc *desc;
48 xilinx_desc *xdesc;
49
50 dataptr = (unsigned char *)fpgadata;
51
52 desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
53
54 xdesc = desc->devdesc;
55
56
57 length = (*dataptr << 8) + *(dataptr + 1);
58 dataptr += 2;
59 dataptr += length;
60
61
62 length = (*dataptr << 8) + *(dataptr + 1);
63 dataptr += 2;
64 if (*dataptr++ != 0x61) {
65 debug("%s: Design name id not recognized in bitstream\n",
66 __func__);
67 return FPGA_FAIL;
68 }
69
70 length = (*dataptr << 8) + *(dataptr + 1);
71 dataptr += 2;
72 printf(" design filename = \"%s\"\n", dataptr);
73 dataptr += length;
74
75
76 if (*dataptr++ != 0x62) {
77 printf("%s: Part number id not recognized in bitstream\n",
78 __func__);
79 return FPGA_FAIL;
80 }
81
82 length = (*dataptr << 8) + *(dataptr + 1);
83 dataptr += 2;
84
85 if (xdesc->name) {
86 i = (ulong)strstr((char *)dataptr, xdesc->name);
87 if (!i) {
88 printf("%s: Wrong bitstream ID for this device\n",
89 __func__);
90 printf("%s: Bitstream ID %s, current device ID %d/%s\n",
91 __func__, dataptr, devnum, xdesc->name);
92 return FPGA_FAIL;
93 }
94 } else {
95 printf("%s: Please fill correct device ID to xilinx_desc\n",
96 __func__);
97 }
98 printf(" part number = \"%s\"\n", dataptr);
99 dataptr += length;
100
101
102 if (*dataptr++ != 0x63) {
103 printf("%s: Date identifier not recognized in bitstream\n",
104 __func__);
105 return FPGA_FAIL;
106 }
107
108 length = (*dataptr << 8) + *(dataptr+1);
109 dataptr += 2;
110 printf(" date = \"%s\"\n", dataptr);
111 dataptr += length;
112
113
114 if (*dataptr++ != 0x64) {
115 printf("%s: Time identifier not recognized in bitstream\n",
116 __func__);
117 return FPGA_FAIL;
118 }
119
120 length = (*dataptr << 8) + *(dataptr+1);
121 dataptr += 2;
122 printf(" time = \"%s\"\n", dataptr);
123 dataptr += length;
124
125
126 if (*dataptr++ != 0x65) {
127 printf("%s: Data length id not recognized in bitstream\n",
128 __func__);
129 return FPGA_FAIL;
130 }
131 swapsize = ((unsigned int) *dataptr << 24) +
132 ((unsigned int) *(dataptr + 1) << 16) +
133 ((unsigned int) *(dataptr + 2) << 8) +
134 ((unsigned int) *(dataptr + 3));
135 dataptr += 4;
136 printf(" bytes in bitstream = %d\n", swapsize);
137
138 return fpga_load(devnum, dataptr, swapsize, bstype);
139}
140
141int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
142 bitstream_type bstype)
143{
144 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
145 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
146 return FPGA_FAIL;
147 }
148
149 if (!desc->operations || !desc->operations->load) {
150 printf("%s: Missing load operation\n", __func__);
151 return FPGA_FAIL;
152 }
153
154 return desc->operations->load(desc, buf, bsize, bstype);
155}
156
157#if defined(CONFIG_CMD_FPGA_LOADFS)
158int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
159 fpga_fs_info *fpga_fsinfo)
160{
161 if (!xilinx_validate(desc, (char *)__func__)) {
162 printf("%s: Invalid device descriptor\n", __func__);
163 return FPGA_FAIL;
164 }
165
166 if (!desc->operations || !desc->operations->loadfs) {
167 printf("%s: Missing loadfs operation\n", __func__);
168 return FPGA_FAIL;
169 }
170
171 return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
172}
173#endif
174
175#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
176int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
177 struct fpga_secure_info *fpga_sec_info)
178{
179 if (!xilinx_validate(desc, (char *)__func__)) {
180 printf("%s: Invalid device descriptor\n", __func__);
181 return FPGA_FAIL;
182 }
183
184 if (!desc->operations || !desc->operations->loads) {
185 printf("%s: Missing loads operation\n", __func__);
186 return FPGA_FAIL;
187 }
188
189 return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
190}
191#endif
192
193int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
194{
195 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
196 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
197 return FPGA_FAIL;
198 }
199
200 if (!desc->operations || !desc->operations->dump) {
201 printf("%s: Missing dump operation\n", __func__);
202 return FPGA_FAIL;
203 }
204
205 return desc->operations->dump(desc, buf, bsize);
206}
207
208int xilinx_info(xilinx_desc *desc)
209{
210 int ret_val = FPGA_FAIL;
211
212 if (xilinx_validate (desc, (char *)__FUNCTION__)) {
213 printf ("Family: \t");
214 switch (desc->family) {
215 case xilinx_spartan2:
216 printf ("Spartan-II\n");
217 break;
218 case xilinx_spartan3:
219 printf ("Spartan-III\n");
220 break;
221 case xilinx_virtex2:
222 printf ("Virtex-II\n");
223 break;
224 case xilinx_zynq:
225 printf("Zynq PL\n");
226 break;
227 case xilinx_zynqmp:
228 printf("ZynqMP PL\n");
229 break;
230 case xilinx_versal:
231 printf("Versal PL\n");
232 break;
233
234 default:
235 printf ("Unknown family type, %d\n", desc->family);
236 }
237
238 printf ("Interface type:\t");
239 switch (desc->iface) {
240 case slave_serial:
241 printf ("Slave Serial\n");
242 break;
243 case master_serial:
244 printf ("Master Serial\n");
245 break;
246 case slave_parallel:
247 printf ("Slave Parallel\n");
248 break;
249 case jtag_mode:
250 printf ("JTAG Mode\n");
251 break;
252 case slave_selectmap:
253 printf ("Slave SelectMap Mode\n");
254 break;
255 case master_selectmap:
256 printf ("Master SelectMap Mode\n");
257 break;
258 case devcfg:
259 printf("Device configuration interface (Zynq)\n");
260 break;
261 case csu_dma:
262 printf("csu_dma configuration interface (ZynqMP)\n");
263 break;
264 case cfi:
265 printf("CFI configuration interface (Versal)\n");
266 break;
267
268 default:
269 printf ("Unsupported interface type, %d\n", desc->iface);
270 }
271
272 printf("Device Size: \t%zd bytes\n"
273 "Cookie: \t0x%x (%d)\n",
274 desc->size, desc->cookie, desc->cookie);
275 if (desc->name)
276 printf("Device name: \t%s\n", desc->name);
277
278 if (desc->iface_fns)
279 printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
280 else
281 printf ("No Device Function Table.\n");
282
283 if (desc->operations && desc->operations->info)
284 desc->operations->info(desc);
285
286 ret_val = FPGA_SUCCESS;
287 } else {
288 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
289 }
290
291 return ret_val;
292}
293
294
295
296static int xilinx_validate(xilinx_desc *desc, char *fn)
297{
298 int ret_val = false;
299
300 if (desc) {
301 if ((desc->family > min_xilinx_type) &&
302 (desc->family < max_xilinx_type)) {
303 if ((desc->iface > min_xilinx_iface_type) &&
304 (desc->iface < max_xilinx_iface_type)) {
305 if (desc->size) {
306 ret_val = true;
307 } else
308 printf ("%s: NULL part size\n", fn);
309 } else
310 printf ("%s: Invalid Interface type, %d\n",
311 fn, desc->iface);
312 } else
313 printf ("%s: Invalid family type, %d\n", fn, desc->family);
314 } else
315 printf ("%s: NULL descriptor!\n", fn);
316
317 return ret_val;
318}
319
