1
2
3
4
5menuconfig I2C
6 bool "I2C support"
7 default y
8 help
9 Note:
10 This is a stand-in for an option to enable I2C support. In fact this
11 simply enables building of the I2C directory for U-Boot. The actual
12 I2C feature is enabled by DM_I2C (for driver model) and
13 the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack).
14
15 So at present there is no need to ever disable this option.
16
17 Eventually it will:
18
19 Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot.
20 I2C works with a clock and data line which can be driven by a
21 one or more masters or slaves. It is a fairly complex bus but is
22 widely used as it only needs two lines for communication. Speeds of
23 400kbps are typical but up to 3.4Mbps is supported by some
24 hardware. Enable this option to build the drivers in drivers/i2c as
25 part of a U-Boot build.
26
27if I2C
28
29config DM_I2C
30 bool "Enable Driver Model for I2C drivers"
31 depends on DM
32 help
33 Enable driver model for I2C. The I2C uclass interface: probe, read,
34 write and speed, is implemented with the bus drivers operations,
35 which provide methods for bus setting and data transfer. Each chip
36 device (bus child) info is kept as parent plat. The interface
37 is defined in include/i2c.h.
38
39config SPL_DM_I2C
40 bool "Enable Driver Model for I2C drivers in SPL"
41 depends on SPL_DM && DM_I2C
42 default y
43 help
44 Enable driver model for I2C. The I2C uclass interface: probe, read,
45 write and speed, is implemented with the bus drivers operations,
46 which provide methods for bus setting and data transfer. Each chip
47 device (bus child) info is kept as parent platdata. The interface
48 is defined in include/i2c.h.
49
50config SYS_I2C_LEGACY
51 bool "Enable legacy I2C subsystem and drivers"
52 depends on !DM_I2C
53 help
54 Enable the legacy I2C subsystem and drivers. While this is
55 deprecated in U-Boot itself, this can be useful in some situations
56 in SPL or TPL.
57
58config SPL_SYS_I2C_LEGACY
59 bool "Enable legacy I2C subsystem and drivers in SPL"
60 depends on SUPPORT_SPL && !SPL_DM_I2C
61 help
62 Enable the legacy I2C subsystem and drivers in SPL. This is useful
63 in some size constrained situations.
64
65config TPL_SYS_I2C_LEGACY
66 bool "Enable legacy I2C subsystem and drivers in TPL"
67 depends on SUPPORT_TPL && !SPL_DM_I2C
68 help
69 Enable the legacy I2C subsystem and drivers in TPL. This is useful
70 in some size constrained situations.
71
72config SYS_I2C_EARLY_INIT
73 bool "Enable legacy I2C subsystem early in boot"
74 depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC
75 help
76 Add the function prototype for i2c_early_init_f which is called in
77 board_early_init_f.
78
79config I2C_CROS_EC_TUNNEL
80 tristate "Chrome OS EC tunnel I2C bus"
81 depends on CROS_EC
82 help
83 This provides an I2C bus that will tunnel i2c commands through to
84 the other side of the Chrome OS EC to the I2C bus connected there.
85 This will work whatever the interface used to talk to the EC (SPI,
86 I2C or LPC). Some Chromebooks use this when the hardware design
87 does not allow direct access to the main PMIC from the AP.
88
89config I2C_CROS_EC_LDO
90 bool "Provide access to LDOs on the Chrome OS EC"
91 depends on CROS_EC
92 ---help---
93 On many Chromebooks the main PMIC is inaccessible to the AP. This is
94 often dealt with by using an I2C pass-through interface provided by
95 the EC. On some unfortunate models (e.g. Spring) the pass-through
96 is not available, and an LDO message is available instead. This
97 option enables a driver which provides very basic access to those
98 regulators, via the EC. We implement this as an I2C bus which
99 emulates just the TPS65090 messages we know about. This is done to
100 avoid duplicating the logic in the TPS65090 regulator driver for
101 enabling/disabling an LDO.
102
103config I2C_SET_DEFAULT_BUS_NUM
104 bool "Set default I2C bus number"
105 depends on DM_I2C
106 help
107 Set default number of I2C bus to be accessed. This option provides
108 behaviour similar to old (i.e. pre DM) I2C bus driver.
109
110config I2C_DEFAULT_BUS_NUMBER
111 hex "I2C default bus number"
112 depends on I2C_SET_DEFAULT_BUS_NUM
113 default 0x0
114 help
115 Number of default I2C bus to use
116
117config DM_I2C_GPIO
118 bool "Enable Driver Model for software emulated I2C bus driver"
119 depends on DM_I2C && DM_GPIO
120 help
121 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
122 configuration is given by the device tree. Kernel-style device tree
123 bindings are supported.
124 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
125
126config SPL_DM_I2C_GPIO
127 bool "Enable Driver Model for software emulated I2C bus driver in SPL"
128 depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO
129 default y
130 help
131 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
132 configuration is given by the device tree. Kernel-style device tree
133 bindings are supported.
134 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
135
136config SYS_I2C_AT91
137 bool "Atmel I2C driver"
138 depends on DM_I2C && ARCH_AT91
139 help
140 Add support for the Atmel I2C driver. A serious problem is that there
141 is no documented way to issue repeated START conditions for more than
142 two messages, as needed to support combined I2C messages. Use the
143 i2c-gpio driver unless your system can cope with this limitation.
144 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
145
146config SYS_I2C_IPROC
147 bool "Broadcom I2C driver"
148 depends on DM_I2C
149 help
150 Broadcom I2C driver.
151 Add support for Broadcom I2C driver.
152 Say yes here to to enable the Broadco I2C driver.
153
154config SYS_I2C_FSL
155 bool "Freescale I2C bus driver"
156 help
157 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
158 MPC85xx processors.
159
160if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
161config SYS_FSL_I2C_OFFSET
162 hex "Offset from the IMMR of the address of the first I2C controller"
163
164config SYS_FSL_HAS_I2C2_OFFSET
165 bool "Support a second I2C controller"
166
167config SYS_FSL_I2C2_OFFSET
168 hex "Offset from the IMMR of the address of the second I2C controller"
169 depends on SYS_FSL_HAS_I2C2_OFFSET
170
171config SYS_FSL_HAS_I2C3_OFFSET
172 bool "Support a third I2C controller"
173
174config SYS_FSL_I2C3_OFFSET
175 hex "Offset from the IMMR of the address of the third I2C controller"
176 depends on SYS_FSL_HAS_I2C3_OFFSET
177
178config SYS_FSL_HAS_I2C4_OFFSET
179 bool "Support a fourth I2C controller"
180
181config SYS_FSL_I2C4_OFFSET
182 hex "Offset from the IMMR of the address of the fourth I2C controller"
183 depends on SYS_FSL_HAS_I2C4_OFFSET
184endif
185
186config SYS_I2C_CADENCE
187 tristate "Cadence I2C Controller"
188 depends on DM_I2C
189 help
190 Say yes here to select Cadence I2C Host Controller. This controller is
191 e.g. used by Xilinx Zynq.
192
193config SYS_I2C_CA
194 tristate "Cortina-Access I2C Controller"
195 depends on DM_I2C && CORTINA_PLATFORM
196 help
197 Add support for the Cortina Access I2C host controller.
198 Say yes here to select Cortina-Access I2C Host Controller.
199
200config SYS_I2C_DAVINCI
201 bool "Davinci I2C Controller"
202 depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
203 help
204 Say yes here to add support for Davinci and Keystone I2C controller
205
206config SYS_I2C_DW
207 bool "Designware I2C Controller"
208 help
209 Say yes here to select the Designware I2C Host Controller. This
210 controller is used in various SoCs, e.g. the ST SPEAr, Altera
211 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
212
213config SYS_I2C_ASPEED
214 bool "Aspeed I2C Controller"
215 depends on DM_I2C && ARCH_ASPEED
216 help
217 Say yes here to select Aspeed I2C Host Controller. The driver
218 supports AST2500 and AST2400 controllers, but is very limited.
219 Only single master mode is supported and only byte-by-byte
220 synchronous reads and writes are supported, no Pool Buffers or DMA.
221
222config SYS_I2C_INTEL
223 bool "Intel I2C/SMBUS driver"
224 depends on DM_I2C
225 help
226 Add support for the Intel SMBUS driver. So far this driver is just
227 a stub which perhaps some basic init. There is no implementation of
228 the I2C API meaning that any I2C operations will immediately fail
229 for now.
230
231config SYS_I2C_IMX_LPI2C
232 bool "NXP i.MX LPI2C driver"
233 help
234 Add support for the NXP i.MX LPI2C driver.
235
236config SYS_I2C_LPC32XX
237 bool "LPC32XX I2C driver"
238 depends on ARCH_LPC32XX
239 help
240 Enable support for the LPC32xx I2C driver.
241
242config SYS_I2C_MESON
243 bool "Amlogic Meson I2C driver"
244 depends on DM_I2C && ARCH_MESON
245 help
246 Add support for the I2C controller available in Amlogic Meson
247 SoCs. The controller supports programmable bus speed including
248 standard (100kbits/s) and fast (400kbit/s) speed and allows the
249 software to define a flexible format of the bit streams. It has an
250 internal buffer holding up to 8 bytes for transfers and supports
251 both 7-bit and 10-bit addresses.
252
253config SYS_I2C_MICROCHIP
254 bool "Microchip I2C driver"
255 help
256 Add support for the Microchip I2C driver. This is operating on
257 standard mode up to 100 kbits/s and fast mode up to 400 kbits/s.
258
259config SYS_I2C_MXC
260 bool "NXP MXC I2C driver"
261 help
262 Add support for the NXP I2C driver. This supports up to four bus
263 channels and operating on standard mode up to 100 kbits/s and fast
264 mode up to 400 kbits/s.
265
266if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
267config SYS_I2C_MXC_I2C1
268 bool "NXP MXC I2C1"
269 help
270 Add support for NXP MXC I2C Controller 1.
271 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
272
273config SYS_I2C_MXC_I2C2
274 bool "NXP MXC I2C2"
275 help
276 Add support for NXP MXC I2C Controller 2.
277 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
278
279config SYS_I2C_MXC_I2C3
280 bool "NXP MXC I2C3"
281 help
282 Add support for NXP MXC I2C Controller 3.
283 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
284
285config SYS_I2C_MXC_I2C4
286 bool "NXP MXC I2C4"
287 help
288 Add support for NXP MXC I2C Controller 4.
289 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
290
291config SYS_I2C_MXC_I2C5
292 bool "NXP MXC I2C5"
293 help
294 Add support for NXP MXC I2C Controller 5.
295 Required for SoCs which have I2C MXC controller 5 eg LX2160A
296
297config SYS_I2C_MXC_I2C6
298 bool "NXP MXC I2C6"
299 help
300 Add support for NXP MXC I2C Controller 6.
301 Required for SoCs which have I2C MXC controller 6 eg LX2160A
302
303config SYS_I2C_MXC_I2C7
304 bool "NXP MXC I2C7"
305 help
306 Add support for NXP MXC I2C Controller 7.
307 Required for SoCs which have I2C MXC controller 7 eg LX2160A
308
309config SYS_I2C_MXC_I2C8
310 bool "NXP MXC I2C8"
311 help
312 Add support for NXP MXC I2C Controller 8.
313 Required for SoCs which have I2C MXC controller 8 eg LX2160A
314endif
315
316if SYS_I2C_MXC_I2C1
317config SYS_MXC_I2C1_SPEED
318 int "I2C Channel 1 speed"
319 default 40000000 if TARGET_LS2080A_EMU
320 default 100000
321 help
322 MXC I2C Channel 1 speed
323
324config SYS_MXC_I2C1_SLAVE
325 hex "I2C1 Slave"
326 default 0
327 help
328 MXC I2C1 Slave
329endif
330
331if SYS_I2C_MXC_I2C2
332config SYS_MXC_I2C2_SPEED
333 int "I2C Channel 2 speed"
334 default 40000000 if TARGET_LS2080A_EMU
335 default 100000
336 help
337 MXC I2C Channel 2 speed
338
339config SYS_MXC_I2C2_SLAVE
340 hex "I2C2 Slave"
341 default 0
342 help
343 MXC I2C2 Slave
344endif
345
346if SYS_I2C_MXC_I2C3
347config SYS_MXC_I2C3_SPEED
348 int "I2C Channel 3 speed"
349 default 100000
350 help
351 MXC I2C Channel 3 speed
352
353config SYS_MXC_I2C3_SLAVE
354 hex "I2C3 Slave"
355 default 0
356 help
357 MXC I2C3 Slave
358endif
359
360if SYS_I2C_MXC_I2C4
361config SYS_MXC_I2C4_SPEED
362 int "I2C Channel 4 speed"
363 default 100000
364 help
365 MXC I2C Channel 4 speed
366
367config SYS_MXC_I2C4_SLAVE
368 hex "I2C4 Slave"
369 default 0
370 help
371 MXC I2C4 Slave
372endif
373
374if SYS_I2C_MXC_I2C5
375config SYS_MXC_I2C5_SPEED
376 int "I2C Channel 5 speed"
377 default 100000
378 help
379 MXC I2C Channel 5 speed
380
381config SYS_MXC_I2C5_SLAVE
382 hex "I2C5 Slave"
383 default 0
384 help
385 MXC I2C5 Slave
386endif
387
388if SYS_I2C_MXC_I2C6
389config SYS_MXC_I2C6_SPEED
390 int "I2C Channel 6 speed"
391 default 100000
392 help
393 MXC I2C Channel 6 speed
394
395config SYS_MXC_I2C6_SLAVE
396 hex "I2C6 Slave"
397 default 0
398 help
399 MXC I2C6 Slave
400endif
401
402if SYS_I2C_MXC_I2C7
403config SYS_MXC_I2C7_SPEED
404 int "I2C Channel 7 speed"
405 default 100000
406 help
407 MXC I2C Channel 7 speed
408
409config SYS_MXC_I2C7_SLAVE
410 hex "I2C7 Slave"
411 default 0
412 help
413 MXC I2C7 Slave
414endif
415
416if SYS_I2C_MXC_I2C8
417config SYS_MXC_I2C8_SPEED
418 int "I2C Channel 8 speed"
419 default 100000
420 help
421 MXC I2C Channel 8 speed
422
423config SYS_MXC_I2C8_SLAVE
424 hex "I2C8 Slave"
425 default 0
426 help
427 MXC I2C8 Slave
428endif
429
430config SYS_I2C_NEXELL
431 bool "Nexell I2C driver"
432 depends on DM_I2C
433 help
434 Add support for the Nexell I2C driver. This is used with various
435 Nexell parts such as S5Pxx18 series SoCs. All chips
436 have several I2C ports and all are provided, controlled by the
437 device tree.
438
439config SYS_I2C_OCORES
440 bool "ocores I2C driver"
441 depends on DM_I2C
442 help
443 Add support for ocores I2C controller. For details see
444 https://opencores.org/projects/i2c
445
446config SYS_I2C_OMAP24XX
447 bool "TI OMAP2+ I2C driver"
448 depends on ARCH_OMAP2PLUS || ARCH_K3
449 help
450 Add support for the OMAP2+ I2C driver.
451
452config SYS_I2C_RCAR_I2C
453 bool "Renesas RCar I2C driver"
454 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
455 help
456 Support for Renesas RCar I2C controller.
457
458config SYS_I2C_RCAR_IIC
459 bool "Renesas RCar Gen3 IIC driver"
460 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
461 help
462 Support for Renesas RCar Gen3 IIC controller.
463
464config SYS_I2C_ROCKCHIP
465 bool "Rockchip I2C driver"
466 depends on DM_I2C
467 help
468 Add support for the Rockchip I2C driver. This is used with various
469 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
470 have several I2C ports and all are provided, controlled by the
471 device tree.
472
473config SYS_I2C_SANDBOX
474 bool "Sandbox I2C driver"
475 depends on SANDBOX && DM_I2C
476 help
477 Enable I2C support for sandbox. This is an emulation of a real I2C
478 bus. Devices can be attached to the bus using the device tree
479 which specifies the driver to use. See sandbox.dts as an example.
480
481config SYS_I2C_SH
482 bool "Legacy SuperH I2C interface"
483 depends on ARCH_RMOBILE && SYS_I2C_LEGACY
484 help
485 Enable the legacy SuperH I2C interface.
486
487if SYS_I2C_SH
488config SYS_I2C_SH_NUM_CONTROLLERS
489 int
490 default 5
491
492config SYS_I2C_SH_BASE0
493 hex
494 default 0xE6820000
495
496config SYS_I2C_SH_BASE1
497 hex
498 default 0xE6822000
499
500config SYS_I2C_SH_BASE2
501 hex
502 default 0xE6824000
503
504config SYS_I2C_SH_BASE3
505 hex
506 default 0xE6826000
507
508config SYS_I2C_SH_BASE4
509 hex
510 default 0xE6828000
511
512config SH_I2C_8BIT
513 bool
514 default y
515
516config SH_I2C_DATA_HIGH
517 int
518 default 4
519
520config SH_I2C_DATA_LOW
521 int
522 default 5
523
524config SH_I2C_CLOCK
525 int
526 default 104000000
527endif
528
529config SYS_I2C_SOFT
530 bool "Legacy software I2C interface"
531 help
532 Enable the legacy software defined I2C interface
533
534config SYS_I2C_SOFT_SPEED
535 int "Software I2C bus speed"
536 depends on SYS_I2C_SOFT
537 default 100000
538 help
539 Speed of the software I2C bus
540
541config SYS_I2C_SOFT_SLAVE
542 hex "Software I2C slave address"
543 depends on SYS_I2C_SOFT
544 default 0xfe
545 help
546 Slave address of the software I2C bus
547
548config SYS_I2C_OCTEON
549 bool "Octeon II/III/TX/TX2 I2C driver"
550 depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
551 default y
552 help
553 Add support for the Marvell Octeon I2C driver. This is used with
554 various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
555 chips have several I2C ports and all are provided, controlled by
556 the device tree.
557
558config SYS_I2C_S3C24X0
559 bool "Samsung I2C driver"
560 depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
561 help
562 Support for Samsung I2C controller as Samsung SoCs.
563
564config SYS_I2C_STM32F7
565 bool "STMicroelectronics STM32F7 I2C support"
566 depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
567 help
568 Enable this option to add support for STM32 I2C controller
569 introduced with STM32F7/H7 SoCs. This I2C controller supports :
570 _ Slave and master modes
571 _ Multimaster capability
572 _ Standard-mode (up to 100 kHz)
573 _ Fast-mode (up to 400 kHz)
574 _ Fast-mode Plus (up to 1 MHz)
575 _ 7-bit and 10-bit addressing mode
576 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
577 _ All 7-bit addresses acknowledge mode
578 _ General call
579 _ Programmable setup and hold times
580 _ Easy to use event management
581 _ Optional clock stretching
582 _ Software reset
583
584config SYS_I2C_SUN6I_P2WI
585 bool "Allwinner sun6i P2WI controller"
586 depends on ARCH_SUNXI
587 help
588 Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded
589 in the Allwinner A31 and A31s SOCs. This interface is used to connect
590 to specific devices like the X-Powers AXP221 PMIC.
591
592config SYS_I2C_SUN8I_RSB
593 bool "Allwinner sun8i Reduced Serial Bus controller"
594 depends on ARCH_SUNXI
595 help
596 Support for Allwinner's Reduced Serial Bus (RSB) controller. This
597 controller is responsible for communicating with various RSB based
598 devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs.
599
600config SYS_I2C_SYNQUACER
601 bool "Socionext SynQuacer I2C controller"
602 depends on ARCH_SYNQUACER && DM_I2C
603 help
604 Support for Socionext Synquacer I2C controller. This I2C controller
605 will be used for RTC and LS-connector on DeveloperBox.
606
607config SYS_I2C_TEGRA
608 bool "NVIDIA Tegra internal I2C controller"
609 depends on ARCH_TEGRA
610 help
611 Support for NVIDIA I2C controller available in Tegra SoCs.
612
613config SYS_I2C_UNIPHIER
614 bool "UniPhier I2C driver"
615 depends on ARCH_UNIPHIER && DM_I2C
616 default y
617 help
618 Support for UniPhier I2C controller driver. This I2C controller
619 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
620
621config SYS_I2C_UNIPHIER_F
622 bool "UniPhier FIFO-builtin I2C driver"
623 depends on ARCH_UNIPHIER && DM_I2C
624 default y
625 help
626 Support for UniPhier FIFO-builtin I2C controller driver.
627 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
628
629config SYS_I2C_VERSATILE
630 bool "Arm Ltd Versatile I2C bus driver"
631 depends on DM_I2C && TARGET_VEXPRESS64_JUNO
632 help
633 Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
634 controller is present in the development boards manufactured by Arm Ltd.
635
636config SYS_I2C_MV
637 bool "Marvell PXA (Armada 3720) I2C driver"
638 help
639 Support for PXA based I2C controller used on Armada 3720 SoC.
640 In Linux, this driver is called i2c-pxa.
641
642config SYS_I2C_MVTWSI
643 bool "Marvell I2C driver"
644 help
645 Support for Marvell I2C controllers as used on the orion5x and
646 kirkwood SoC families.
647
648config TEGRA186_BPMP_I2C
649 bool "Enable Tegra186 BPMP-based I2C driver"
650 depends on TEGRA186_BPMP
651 help
652 Support for Tegra I2C controllers managed by the BPMP (Boot and
653 Power Management Processor). On Tegra186, some I2C controllers are
654 directly controlled by the main CPU, whereas others are controlled
655 by the BPMP, and can only be accessed by the main CPU via IPC
656 requests to the BPMP. This driver covers the latter case.
657
658config SYS_I2C_SLAVE
659 hex "I2C Slave address channel (all buses)"
660 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
661 default 0xfe
662 help
663 I2C Slave address channel 0 for all buses in the legacy drivers.
664 Many boards/controllers/drivers don't support an I2C slave
665 interface so provide a default slave address for them for use in
666 common code. A real value for CONFIG_SYS_I2C_SLAVE should be
667 defined for any board which does support a slave interface and
668 this default used otherwise.
669
670config SYS_I2C_SPEED
671 int "I2C Slave channel 0 speed (all buses)"
672 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
673 default 100000
674 help
675 I2C Slave speed channel 0 for all buses in the legacy drivers.
676
677config SYS_I2C_BUS_MAX
678 int "Max I2C busses"
679 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
680 default 2 if TI816X
681 default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
682 default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
683 default 5 if OMAP54XX
684 help
685 Define the maximum number of available I2C buses.
686
687config SYS_I2C_XILINX_XIIC
688 bool "Xilinx AXI I2C driver"
689 depends on DM_I2C
690 help
691 Support for Xilinx AXI I2C controller.
692
693config SYS_I2C_IHS
694 bool "gdsys IHS I2C driver"
695 depends on DM_I2C
696 help
697 Support for gdsys IHS I2C driver on FPGA bus.
698
699source "drivers/i2c/muxes/Kconfig"
700
701endif
702
