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19#include <common.h>
20#include <dm.h>
21#include <i2c.h>
22#include <log.h>
23#include <asm/io.h>
24#include <linux/delay.h>
25#include "mv_i2c.h"
26
27
28struct mv_i2c_msg {
29 u8 condition;
30 u8 acknack;
31 u8 direction;
32 u8 data;
33};
34
35#ifdef CONFIG_ARMADA_3700
36
37struct mv_i2c {
38 u32 ibmr;
39 u32 idbr;
40 u32 icr;
41 u32 isr;
42 u32 isar;
43};
44#else
45struct mv_i2c {
46 u32 ibmr;
47 u32 pad0;
48 u32 idbr;
49 u32 pad1;
50 u32 icr;
51 u32 pad2;
52 u32 isr;
53 u32 pad3;
54 u32 isar;
55};
56#endif
57
58
59
60
61
62__weak void i2c_clk_enable(void)
63{
64}
65
66
67
68
69
70static void i2c_reset(struct mv_i2c *base)
71{
72 u32 icr_mode;
73
74
75 icr_mode = readl(&base->icr) & ICR_MODE_MASK;
76 writel(readl(&base->icr) & ~ICR_IUE, &base->icr);
77 writel(readl(&base->icr) | ICR_UR, &base->icr);
78 udelay(100);
79 writel(readl(&base->icr) & ~ICR_IUE, &base->icr);
80
81 i2c_clk_enable();
82
83 writel(0x0, &base->isar);
84
85 writel(I2C_ICR_INIT | icr_mode, &base->icr);
86 writel(I2C_ISR_INIT, &base->isr);
87 writel(readl(&base->icr) | ICR_IUE, &base->icr);
88 udelay(100);
89}
90
91
92
93
94
95
96
97static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
98 unsigned long cleared_mask)
99{
100 int timeout = 1000, isr;
101
102 do {
103 isr = readl(&base->isr);
104 udelay(10);
105 if (timeout-- < 0)
106 return 0;
107 } while (((isr & set_mask) != set_mask)
108 || ((isr & cleared_mask) != 0));
109
110 return 1;
111}
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
128{
129 int ret;
130
131 if (!msg)
132 goto transfer_error_msg_empty;
133
134 switch (msg->direction) {
135 case I2C_WRITE:
136
137 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
138 goto transfer_error_bus_busy;
139
140
141 writel(readl(&base->icr) & ~ICR_START, &base->icr);
142 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
143 writel(msg->data, &base->idbr);
144 if (msg->condition == I2C_COND_START)
145 writel(readl(&base->icr) | ICR_START, &base->icr);
146 if (msg->condition == I2C_COND_STOP)
147 writel(readl(&base->icr) | ICR_STOP, &base->icr);
148 if (msg->acknack == I2C_ACKNAK_SENDNAK)
149 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
150 if (msg->acknack == I2C_ACKNAK_SENDACK)
151 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
152 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
153 writel(readl(&base->icr) | ICR_TB, &base->icr);
154
155
156 if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
157 goto transfer_error_transmit_timeout;
158
159
160 writel(readl(&base->isr) | ISR_ITE, &base->isr);
161
162
163 if (msg->acknack == I2C_ACKNAK_WAITACK)
164 if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
165 goto transfer_error_ack_missing;
166 break;
167
168 case I2C_READ:
169
170
171 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
172 goto transfer_error_bus_busy;
173
174
175 writel(readl(&base->icr) & ~ICR_START, &base->icr);
176 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
177 if (msg->condition == I2C_COND_START)
178 writel(readl(&base->icr) | ICR_START, &base->icr);
179 if (msg->condition == I2C_COND_STOP)
180 writel(readl(&base->icr) | ICR_STOP, &base->icr);
181 if (msg->acknack == I2C_ACKNAK_SENDNAK)
182 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
183 if (msg->acknack == I2C_ACKNAK_SENDACK)
184 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
185 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
186 writel(readl(&base->icr) | ICR_TB, &base->icr);
187
188
189 if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
190 goto transfer_error_receive_timeout;
191
192 msg->data = readl(&base->idbr);
193
194
195 writel(readl(&base->isr) | ISR_IRF, &base->isr);
196 break;
197 default:
198 goto transfer_error_illegal_param;
199 }
200
201 return 0;
202
203transfer_error_msg_empty:
204 debug("i2c_transfer: error: 'msg' is empty\n");
205 ret = -1;
206 goto i2c_transfer_finish;
207
208transfer_error_transmit_timeout:
209 debug("i2c_transfer: error: transmit timeout\n");
210 ret = -2;
211 goto i2c_transfer_finish;
212
213transfer_error_ack_missing:
214 debug("i2c_transfer: error: ACK missing\n");
215 ret = -3;
216 goto i2c_transfer_finish;
217
218transfer_error_receive_timeout:
219 debug("i2c_transfer: error: receive timeout\n");
220 ret = -4;
221 goto i2c_transfer_finish;
222
223transfer_error_illegal_param:
224 debug("i2c_transfer: error: illegal parameters\n");
225 ret = -5;
226 goto i2c_transfer_finish;
227
228transfer_error_bus_busy:
229 debug("i2c_transfer: error: bus is busy\n");
230 ret = -6;
231 goto i2c_transfer_finish;
232
233i2c_transfer_finish:
234 debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
235 i2c_reset(base);
236 return ret;
237}
238
239static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
240 uchar *buffer, int len)
241{
242 struct mv_i2c_msg msg;
243
244 debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
245 "len=0x%02x)\n", chip, *addr, alen, len);
246
247 if (len == 0) {
248 printf("reading zero byte is invalid\n");
249 return -EINVAL;
250 }
251
252 i2c_reset(base);
253
254
255 debug("i2c_read: dummy chip address write\n");
256 msg.condition = I2C_COND_START;
257 msg.acknack = I2C_ACKNAK_WAITACK;
258 msg.direction = I2C_WRITE;
259 msg.data = (chip << 1);
260 msg.data &= 0xFE;
261 if (i2c_transfer(base, &msg))
262 return -1;
263
264
265
266
267
268 while (--alen >= 0) {
269 debug("i2c_read: send address byte %02x (alen=%d)\n",
270 *addr, alen);
271 msg.condition = I2C_COND_NORMAL;
272 msg.acknack = I2C_ACKNAK_WAITACK;
273 msg.direction = I2C_WRITE;
274 msg.data = addr[alen];
275 if (i2c_transfer(base, &msg))
276 return -1;
277 }
278
279
280 debug("i2c_read: start read sequence\n");
281 msg.condition = I2C_COND_START;
282 msg.acknack = I2C_ACKNAK_WAITACK;
283 msg.direction = I2C_WRITE;
284 msg.data = (chip << 1);
285 msg.data |= 0x01;
286 if (i2c_transfer(base, &msg))
287 return -1;
288
289
290 while (len--) {
291 if (len == 0) {
292 msg.condition = I2C_COND_STOP;
293 msg.acknack = I2C_ACKNAK_SENDNAK;
294 } else {
295 msg.condition = I2C_COND_NORMAL;
296 msg.acknack = I2C_ACKNAK_SENDACK;
297 }
298
299 msg.direction = I2C_READ;
300 msg.data = 0x00;
301 if (i2c_transfer(base, &msg))
302 return -1;
303
304 *buffer = msg.data;
305 debug("i2c_read: reading byte (%p)=0x%02x\n",
306 buffer, *buffer);
307 buffer++;
308 }
309
310 i2c_reset(base);
311
312 return 0;
313}
314
315static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
316 uchar *buffer, int len)
317{
318 struct mv_i2c_msg msg;
319
320 debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
321 "len=0x%02x)\n", chip, *addr, alen, len);
322
323 i2c_reset(base);
324
325
326 debug("i2c_write: chip address write\n");
327 msg.condition = I2C_COND_START;
328 msg.acknack = I2C_ACKNAK_WAITACK;
329 msg.direction = I2C_WRITE;
330 msg.data = (chip << 1);
331 msg.data &= 0xFE;
332 if (i2c_transfer(base, &msg))
333 return -1;
334
335
336
337
338
339 while (--alen >= 0) {
340 debug("i2c_read: send address byte %02x (alen=%d)\n",
341 *addr, alen);
342 msg.condition = I2C_COND_NORMAL;
343 msg.acknack = I2C_ACKNAK_WAITACK;
344 msg.direction = I2C_WRITE;
345 msg.data = addr[alen];
346 if (i2c_transfer(base, &msg))
347 return -1;
348 }
349
350
351 while (len--) {
352 debug("i2c_write: writing byte (%p)=0x%02x\n",
353 buffer, *buffer);
354
355 if (len == 0)
356 msg.condition = I2C_COND_STOP;
357 else
358 msg.condition = I2C_COND_NORMAL;
359
360 msg.acknack = I2C_ACKNAK_WAITACK;
361 msg.direction = I2C_WRITE;
362 msg.data = *(buffer++);
363
364 if (i2c_transfer(base, &msg))
365 return -1;
366 }
367
368 i2c_reset(base);
369
370 return 0;
371}
372
373#if !CONFIG_IS_ENABLED(DM_I2C)
374
375static struct mv_i2c *base_glob;
376
377static void i2c_board_init(struct mv_i2c *base)
378{
379#ifdef CONFIG_SYS_I2C_INIT_BOARD
380 u32 icr;
381
382
383
384
385
386
387
388
389 icr = readl(&base->icr);
390 writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
391
392 i2c_init_board();
393
394 writel(icr, &base->icr);
395#endif
396}
397
398#ifdef CONFIG_I2C_MULTI_BUS
399static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
400static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
401static unsigned int current_bus;
402
403int i2c_set_bus_num(unsigned int bus)
404{
405 if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
406 printf("Bad bus: %d\n", bus);
407 return -1;
408 }
409
410 base_glob = (struct mv_i2c *)i2c_regs[bus];
411 current_bus = bus;
412
413 if (!bus_initialized[current_bus]) {
414 i2c_board_init(base_glob);
415 bus_initialized[current_bus] = 1;
416 }
417
418 return 0;
419}
420
421unsigned int i2c_get_bus_num(void)
422{
423 return current_bus;
424}
425#endif
426
427
428void i2c_init(int speed, int slaveaddr)
429{
430 u32 val;
431
432#ifdef CONFIG_I2C_MULTI_BUS
433 current_bus = 0;
434 base_glob = (struct mv_i2c *)i2c_regs[current_bus];
435#else
436 base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
437#endif
438
439 if (speed > I2C_SPEED_STANDARD_RATE)
440 val = ICR_FM;
441 else
442 val = ICR_SM;
443 clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
444
445 i2c_board_init(base_glob);
446}
447
448static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
449{
450 struct mv_i2c_msg msg;
451
452 i2c_reset(base);
453
454 msg.condition = I2C_COND_START;
455 msg.acknack = I2C_ACKNAK_WAITACK;
456 msg.direction = I2C_WRITE;
457 msg.data = (chip << 1) + 1;
458 if (i2c_transfer(base, &msg))
459 return -1;
460
461 msg.condition = I2C_COND_STOP;
462 msg.acknack = I2C_ACKNAK_SENDNAK;
463 msg.direction = I2C_READ;
464 msg.data = 0x00;
465 if (i2c_transfer(base, &msg))
466 return -1;
467
468 return 0;
469}
470
471
472
473
474
475
476
477int i2c_probe(uchar chip)
478{
479 return __i2c_probe_chip(base_glob, chip);
480}
481
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493
494
495int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
496{
497 u8 addr_bytes[4];
498
499 addr_bytes[0] = (addr >> 0) & 0xFF;
500 addr_bytes[1] = (addr >> 8) & 0xFF;
501 addr_bytes[2] = (addr >> 16) & 0xFF;
502 addr_bytes[3] = (addr >> 24) & 0xFF;
503
504 return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len);
505}
506
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512
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514
515
516
517
518
519
520int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
521{
522 u8 addr_bytes[4];
523
524 addr_bytes[0] = (addr >> 0) & 0xFF;
525 addr_bytes[1] = (addr >> 8) & 0xFF;
526 addr_bytes[2] = (addr >> 16) & 0xFF;
527 addr_bytes[3] = (addr >> 24) & 0xFF;
528
529 return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len);
530}
531
532#else
533
534struct mv_i2c_priv {
535 struct mv_i2c *base;
536};
537
538static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
539{
540 struct mv_i2c_priv *i2c = dev_get_priv(bus);
541 struct i2c_msg *dmsg, *omsg, dummy;
542
543 memset(&dummy, 0, sizeof(struct i2c_msg));
544
545
546
547
548
549 if (nmsgs > 2 || nmsgs == 0) {
550 debug("%s: Only one or two messages are supported.", __func__);
551 return -1;
552 }
553
554 omsg = nmsgs == 1 ? &dummy : msg;
555 dmsg = nmsgs == 1 ? msg : msg + 1;
556
557 if (dmsg->flags & I2C_M_RD)
558 return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
559 omsg->len, dmsg->buf, dmsg->len);
560 else
561 return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
562 omsg->len, dmsg->buf, dmsg->len);
563}
564
565static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
566{
567 struct mv_i2c_priv *priv = dev_get_priv(bus);
568 u32 val;
569
570 if (speed > I2C_SPEED_STANDARD_RATE)
571 val = ICR_FM;
572 else
573 val = ICR_SM;
574 clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
575
576 return 0;
577}
578
579static int mv_i2c_probe(struct udevice *bus)
580{
581 struct mv_i2c_priv *priv = dev_get_priv(bus);
582
583 priv->base = dev_read_addr_ptr(bus);
584
585 return 0;
586}
587
588static const struct dm_i2c_ops mv_i2c_ops = {
589 .xfer = mv_i2c_xfer,
590 .set_bus_speed = mv_i2c_set_bus_speed,
591};
592
593static const struct udevice_id mv_i2c_ids[] = {
594 { .compatible = "marvell,armada-3700-i2c" },
595 { }
596};
597
598U_BOOT_DRIVER(i2c_mv) = {
599 .name = "i2c_mv",
600 .id = UCLASS_I2C,
601 .of_match = mv_i2c_ids,
602 .probe = mv_i2c_probe,
603 .priv_auto = sizeof(struct mv_i2c_priv),
604 .ops = &mv_i2c_ops,
605};
606#endif
607