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17#include <common.h>
18#include <log.h>
19#include <asm/arch/clock.h>
20#include <asm/arch/imx-regs.h>
21#include <asm/global_data.h>
22#include <dm/device_compat.h>
23#include <linux/delay.h>
24#include <linux/errno.h>
25#include <asm/mach-imx/mxc_i2c.h>
26#include <asm/mach-imx/sys_proto.h>
27#include <asm/io.h>
28#include <i2c.h>
29#include <watchdog.h>
30#include <dm.h>
31#include <dm/pinctrl.h>
32#include <fdtdec.h>
33
34DECLARE_GLOBAL_DATA_PTR;
35
36#define I2C_QUIRK_FLAG (1 << 0)
37
38#define IMX_I2C_REGSHIFT 2
39#define VF610_I2C_REGSHIFT 0
40
41#define I2C_EARLY_INIT_INDEX 0
42#ifdef CONFIG_SYS_I2C_IFDR_DIV
43#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
44#else
45#define I2C_IFDR_DIV_CONSERVATIVE 0x7e
46#endif
47
48
49#define IADR 0
50#define IFDR 1
51#define I2CR 2
52#define I2SR 3
53#define I2DR 4
54
55#define I2CR_IIEN (1 << 6)
56#define I2CR_MSTA (1 << 5)
57#define I2CR_MTX (1 << 4)
58#define I2CR_TX_NO_AK (1 << 3)
59#define I2CR_RSTA (1 << 2)
60
61#define I2SR_ICF (1 << 7)
62#define I2SR_IBB (1 << 5)
63#define I2SR_IAL (1 << 4)
64#define I2SR_IIF (1 << 1)
65#define I2SR_RX_NO_AK (1 << 0)
66
67#ifdef I2C_QUIRK_REG
68#define I2CR_IEN (0 << 7)
69#define I2CR_IDIS (1 << 7)
70#define I2SR_IIF_CLEAR (1 << 1)
71#else
72#define I2CR_IEN (1 << 7)
73#define I2CR_IDIS (0 << 7)
74#define I2SR_IIF_CLEAR (0 << 1)
75#endif
76
77#ifdef I2C_QUIRK_REG
78static u16 i2c_clk_div[60][2] = {
79 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
80 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
81 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
82 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
83 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
84 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
85 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
86 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
87 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
88 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
89 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
90 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
91 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
92 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
93 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
94};
95#else
96static u16 i2c_clk_div[50][2] = {
97 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
98 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
99 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
100 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
101 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
102 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
103 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
104 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
105 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
106 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
107 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
108 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
109 { 3072, 0x1E }, { 3840, 0x1F }
110};
111#endif
112
113
114
115
116static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
117{
118 unsigned int i2c_clk_rate;
119 unsigned int div;
120 u8 clk_div;
121
122#if defined(CONFIG_MX31)
123 struct clock_control_regs *sc_regs =
124 (struct clock_control_regs *)CCM_BASE;
125
126
127 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
128 &sc_regs->cgr0);
129#endif
130
131
132#if CONFIG_IS_ENABLED(CLK)
133 i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
134#else
135 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
136#endif
137
138 div = (i2c_clk_rate + rate - 1) / rate;
139 if (div < i2c_clk_div[0][0])
140 clk_div = 0;
141 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
142 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
143 else
144 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
145 ;
146
147
148 return clk_div;
149}
150
151
152
153
154static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
155{
156 ulong base = i2c_bus->base;
157 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
158 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
159 u8 idx = i2c_clk_div[clk_idx][1];
160 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
161
162 if (!base)
163 return -EINVAL;
164
165
166 writeb(idx, base + (IFDR << reg_shift));
167
168
169 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
170 writeb(0, base + (I2SR << reg_shift));
171 return 0;
172}
173
174#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
175#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
176#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
177
178static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
179{
180 unsigned sr;
181 ulong elapsed;
182 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
183 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
184 ulong base = i2c_bus->base;
185 ulong start_time = get_timer(0);
186 for (;;) {
187 sr = readb(base + (I2SR << reg_shift));
188 if (sr & I2SR_IAL) {
189 if (quirk)
190 writeb(sr | I2SR_IAL, base +
191 (I2SR << reg_shift));
192 else
193 writeb(sr & ~I2SR_IAL, base +
194 (I2SR << reg_shift));
195 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
196 __func__, sr, readb(base + (I2CR << reg_shift)),
197 state);
198 return -ERESTART;
199 }
200 if ((sr & (state >> 8)) == (unsigned char)state)
201 return sr;
202 WATCHDOG_RESET();
203 elapsed = get_timer(start_time);
204 if (elapsed > (CONFIG_SYS_HZ / 10))
205 break;
206 }
207 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
208 sr, readb(base + (I2CR << reg_shift)), state);
209 return -ETIMEDOUT;
210}
211
212static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
213{
214 int ret;
215 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
216 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
217 ulong base = i2c_bus->base;
218
219 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
220 writeb(byte, base + (I2DR << reg_shift));
221
222 ret = wait_for_sr_state(i2c_bus, ST_IIF);
223 if (ret < 0)
224 return ret;
225 if (ret & I2SR_RX_NO_AK)
226 return -EREMOTEIO;
227 return 0;
228}
229
230
231
232
233void __i2c_force_reset_slave(void)
234{
235}
236void i2c_force_reset_slave(void)
237 __attribute__((weak, alias("__i2c_force_reset_slave")));
238
239
240
241
242static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
243{
244 int ret;
245 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
246 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
247 ulong base = i2c_bus->base;
248 unsigned int temp = readb(base + (I2CR << reg_shift));
249
250 temp &= ~(I2CR_MSTA | I2CR_MTX);
251 writeb(temp, base + (I2CR << reg_shift));
252 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
253 if (ret < 0)
254 printf("%s:trigger stop failed\n", __func__);
255}
256
257
258
259
260
261static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
262 u32 addr, int alen)
263{
264 unsigned int temp;
265 int ret;
266 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
267 ulong base = i2c_bus->base;
268 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
269
270
271 i2c_force_reset_slave();
272
273
274 if (quirk)
275 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
276 else
277 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
278
279 if (ret) {
280 writeb(I2CR_IEN, base + (I2CR << reg_shift));
281
282 udelay(50);
283 }
284
285 if (readb(base + (IADR << reg_shift)) == (chip << 1))
286 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
287 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
288 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
289 if (ret < 0)
290 return ret;
291
292
293 temp = readb(base + (I2CR << reg_shift));
294 temp |= I2CR_MSTA;
295 writeb(temp, base + (I2CR << reg_shift));
296
297 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
298 if (ret < 0)
299 return ret;
300
301 temp |= I2CR_MTX | I2CR_TX_NO_AK;
302 writeb(temp, base + (I2CR << reg_shift));
303
304 if (alen >= 0) {
305
306 ret = tx_byte(i2c_bus, chip << 1);
307 if (ret < 0)
308 return ret;
309
310 while (alen--) {
311 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
312 if (ret < 0)
313 return ret;
314 }
315 }
316
317 return 0;
318}
319
320#if !defined(I2C2_BASE_ADDR)
321#define I2C2_BASE_ADDR 0
322#endif
323
324#if !defined(I2C3_BASE_ADDR)
325#define I2C3_BASE_ADDR 0
326#endif
327
328#if !defined(I2C4_BASE_ADDR)
329#define I2C4_BASE_ADDR 0
330#endif
331
332#if !defined(I2C5_BASE_ADDR)
333#define I2C5_BASE_ADDR 0
334#endif
335
336#if !defined(I2C6_BASE_ADDR)
337#define I2C6_BASE_ADDR 0
338#endif
339
340#if !defined(I2C7_BASE_ADDR)
341#define I2C7_BASE_ADDR 0
342#endif
343
344#if !defined(I2C8_BASE_ADDR)
345#define I2C8_BASE_ADDR 0
346#endif
347
348static struct mxc_i2c_bus mxc_i2c_buses[] = {
349#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
350 defined(CONFIG_FSL_LAYERSCAPE)
351 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
352 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
353 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
354 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
355 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
356 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
357 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
358 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
359#else
360 { 0, I2C1_BASE_ADDR, 0 },
361 { 1, I2C2_BASE_ADDR, 0 },
362 { 2, I2C3_BASE_ADDR, 0 },
363 { 3, I2C4_BASE_ADDR, 0 },
364 { 4, I2C5_BASE_ADDR, 0 },
365 { 5, I2C6_BASE_ADDR, 0 },
366 { 6, I2C7_BASE_ADDR, 0 },
367 { 7, I2C8_BASE_ADDR, 0 },
368#endif
369};
370
371#if !CONFIG_IS_ENABLED(DM_I2C)
372int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
373{
374 if (i2c_bus && i2c_bus->idle_bus_fn)
375 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
376 return 0;
377}
378#else
379
380
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388
389
390int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
391{
392 struct udevice *bus = i2c_bus->bus;
393 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
394 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
395 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
396 int sda, scl, idle_sclks;
397 int i, ret = 0;
398 ulong elapsed, start_time;
399
400 if (pinctrl_select_state(bus, "gpio")) {
401 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
402
403
404
405
406
407
408
409 return 0;
410 }
411
412 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
413 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
414 scl = dm_gpio_get_value(scl_gpio);
415 sda = dm_gpio_get_value(sda_gpio);
416
417 if ((sda & scl) == 1)
418 goto exit;
419
420
421
422
423
424
425
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427
428
429
430 idle_sclks = 8 + 1;
431
432 if (i2c->max_transaction_bytes > 0)
433 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
434
435 for (i = 0; i < idle_sclks; i++) {
436 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
437 dm_gpio_set_value(scl_gpio, 0);
438 udelay(50);
439 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
440 udelay(50);
441 }
442 start_time = get_timer(0);
443 for (;;) {
444 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
445 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
446 scl = dm_gpio_get_value(scl_gpio);
447 sda = dm_gpio_get_value(sda_gpio);
448 if ((sda & scl) == 1)
449 break;
450 WATCHDOG_RESET();
451 elapsed = get_timer(start_time);
452 if (elapsed > (CONFIG_SYS_HZ / 5)) {
453 ret = -EBUSY;
454 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
455 break;
456 }
457 }
458
459exit:
460 pinctrl_select_state(bus, "default");
461 return ret;
462}
463#endif
464
465
466
467void i2c_early_init_f(void)
468{
469 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
470 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
471 & I2C_QUIRK_FLAG ? true : false;
472 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
473
474
475 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
476
477 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
478 writeb(0, base + (I2SR << reg_shift));
479
480 writeb(I2CR_IEN, base + (I2CR << reg_shift));
481}
482
483static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
484 u32 addr, int alen)
485{
486 int retry;
487 int ret;
488 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
489 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
490
491 if (!i2c_bus->base)
492 return -EINVAL;
493
494 for (retry = 0; retry < 3; retry++) {
495 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
496 if (ret >= 0)
497 return 0;
498 i2c_imx_stop(i2c_bus);
499 if (ret == -EREMOTEIO)
500 return ret;
501
502 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
503 retry);
504 if (ret != -ERESTART)
505
506 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
507 udelay(100);
508 if (i2c_idle_bus(i2c_bus) < 0)
509 break;
510 }
511 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
512 return ret;
513}
514
515
516static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
517 int len)
518{
519 int i, ret = 0;
520
521 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
522 debug("write_data: ");
523
524 for (i = 0; i < len; ++i)
525 debug(" 0x%02x", buf[i]);
526 debug("\n");
527
528 for (i = 0; i < len; i++) {
529 ret = tx_byte(i2c_bus, buf[i]);
530 if (ret < 0) {
531 debug("i2c_write_data(): rc=%d\n", ret);
532 break;
533 }
534 }
535
536 return ret;
537}
538
539
540
541
542
543
544static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
545 int len, bool last)
546{
547 int ret;
548 unsigned int temp;
549 int i;
550 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
551 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
552 ulong base = i2c_bus->base;
553
554 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
555
556
557 temp = readb(base + (I2CR << reg_shift));
558 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
559 if (len == 1)
560 temp |= I2CR_TX_NO_AK;
561 writeb(temp, base + (I2CR << reg_shift));
562 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
563
564 readb(base + (I2DR << reg_shift));
565
566
567 for (i = 0; i < len; i++) {
568 ret = wait_for_sr_state(i2c_bus, ST_IIF);
569 if (ret < 0) {
570 debug("i2c_read_data(): ret=%d\n", ret);
571 i2c_imx_stop(i2c_bus);
572 return ret;
573 }
574
575 if (i == (len - 1)) {
576
577
578
579
580
581 if (last) {
582 i2c_imx_stop(i2c_bus);
583 } else {
584
585 temp = readb(base + (I2CR << reg_shift));
586 temp |= I2CR_MTX | I2CR_TX_NO_AK;
587 writeb(temp, base + (I2CR << reg_shift));
588 }
589 } else if (i == (len - 2)) {
590
591
592
593
594
595 temp = readb(base + (I2CR << reg_shift));
596 temp |= I2CR_TX_NO_AK;
597 writeb(temp, base + (I2CR << reg_shift));
598 }
599
600 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
601 buf[i] = readb(base + (I2DR << reg_shift));
602 }
603
604
605 for (ret = 0; ret < len; ++ret)
606 debug(" 0x%02x", buf[ret]);
607 debug("\n");
608
609
610 if (last)
611 i2c_imx_stop(i2c_bus);
612 return 0;
613}
614
615int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
616{
617 return 1;
618}
619
620int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
621 __attribute__((weak, alias("__enable_i2c_clk")));
622
623#if !CONFIG_IS_ENABLED(DM_I2C)
624
625
626
627
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631
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644
645
646static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
647 int alen, u8 *buf, int len)
648{
649 int ret = 0;
650 u32 temp;
651 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
652 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
653 ulong base = i2c_bus->base;
654
655 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
656 if (ret < 0)
657 return ret;
658
659 if (alen >= 0) {
660 temp = readb(base + (I2CR << reg_shift));
661 temp |= I2CR_RSTA;
662 writeb(temp, base + (I2CR << reg_shift));
663 }
664
665 ret = tx_byte(i2c_bus, (chip << 1) | 1);
666 if (ret < 0) {
667 i2c_imx_stop(i2c_bus);
668 return ret;
669 }
670
671 ret = i2c_read_data(i2c_bus, chip, buf, len, true);
672
673 i2c_imx_stop(i2c_bus);
674 return ret;
675}
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
695 int alen, const u8 *buf, int len)
696{
697 int ret = 0;
698
699 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
700 if (ret < 0)
701 return ret;
702
703 ret = i2c_write_data(i2c_bus, chip, buf, len);
704
705 i2c_imx_stop(i2c_bus);
706
707 return ret;
708}
709
710struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
711{
712 return &mxc_i2c_buses[adap->hwadapnr];
713}
714
715static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
716 uint addr, int alen, uint8_t *buffer,
717 int len)
718{
719 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
720}
721
722static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
723 uint addr, int alen, uint8_t *buffer,
724 int len)
725{
726 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
727}
728
729
730
731
732static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
733{
734 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
735}
736
737void bus_i2c_init(int index, int speed, int unused,
738 int (*idle_bus_fn)(void *p), void *idle_bus_data)
739{
740 int ret;
741
742 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
743 debug("Error i2c index\n");
744 return;
745 }
746
747 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
748 if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
749 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
750 (ulong)mxc_i2c_buses[index].base);
751 return;
752 }
753 }
754
755
756
757
758
759
760
761 if (idle_bus_fn)
762 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
763 if (idle_bus_data)
764 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
765
766 ret = enable_i2c_clk(1, index);
767 if (ret < 0) {
768 debug("I2C-%d clk fail to enable.\n", index);
769 return;
770 }
771
772 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
773}
774
775
776
777
778static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
779{
780 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
781}
782
783
784
785
786static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
787{
788 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
789}
790
791
792
793
794#ifdef CONFIG_SYS_I2C_MXC_I2C1
795U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
796 mxc_i2c_read, mxc_i2c_write,
797 mxc_i2c_set_bus_speed,
798 CONFIG_SYS_MXC_I2C1_SPEED,
799 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
800#endif
801
802#ifdef CONFIG_SYS_I2C_MXC_I2C2
803U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
804 mxc_i2c_read, mxc_i2c_write,
805 mxc_i2c_set_bus_speed,
806 CONFIG_SYS_MXC_I2C2_SPEED,
807 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
808#endif
809
810#ifdef CONFIG_SYS_I2C_MXC_I2C3
811U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
812 mxc_i2c_read, mxc_i2c_write,
813 mxc_i2c_set_bus_speed,
814 CONFIG_SYS_MXC_I2C3_SPEED,
815 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
816#endif
817
818#ifdef CONFIG_SYS_I2C_MXC_I2C4
819U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
820 mxc_i2c_read, mxc_i2c_write,
821 mxc_i2c_set_bus_speed,
822 CONFIG_SYS_MXC_I2C4_SPEED,
823 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
824#endif
825
826#ifdef CONFIG_SYS_I2C_MXC_I2C5
827U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
828 mxc_i2c_read, mxc_i2c_write,
829 mxc_i2c_set_bus_speed,
830 CONFIG_SYS_MXC_I2C5_SPEED,
831 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
832#endif
833
834#ifdef CONFIG_SYS_I2C_MXC_I2C6
835U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
836 mxc_i2c_read, mxc_i2c_write,
837 mxc_i2c_set_bus_speed,
838 CONFIG_SYS_MXC_I2C6_SPEED,
839 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
840#endif
841
842#ifdef CONFIG_SYS_I2C_MXC_I2C7
843U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
844 mxc_i2c_read, mxc_i2c_write,
845 mxc_i2c_set_bus_speed,
846 CONFIG_SYS_MXC_I2C7_SPEED,
847 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
848#endif
849
850#ifdef CONFIG_SYS_I2C_MXC_I2C8
851U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
852 mxc_i2c_read, mxc_i2c_write,
853 mxc_i2c_set_bus_speed,
854 CONFIG_SYS_MXC_I2C8_SPEED,
855 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
856#endif
857
858#else
859
860static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
861{
862 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
863
864 return bus_i2c_set_bus_speed(i2c_bus, speed);
865}
866
867static int mxc_i2c_probe(struct udevice *bus)
868{
869 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
870 const void *fdt = gd->fdt_blob;
871 int node = dev_of_offset(bus);
872 fdt_addr_t addr;
873 int ret, ret2;
874
875 i2c_bus->driver_data = dev_get_driver_data(bus);
876
877 addr = dev_read_addr(bus);
878 if (addr == FDT_ADDR_T_NONE)
879 return -EINVAL;
880
881 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
882 if (i2c_fused((ulong)addr)) {
883 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
884 (ulong)addr);
885 return -ENODEV;
886 }
887 }
888
889 i2c_bus->base = addr;
890 i2c_bus->index = dev_seq(bus);
891 i2c_bus->bus = bus;
892
893
894#if CONFIG_IS_ENABLED(CLK)
895 ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
896 if (ret) {
897 printf("Failed to get i2c clk\n");
898 return ret;
899 }
900 ret = clk_enable(&i2c_bus->per_clk);
901 if (ret) {
902 printf("Failed to enable i2c clk\n");
903 return ret;
904 }
905#else
906 ret = enable_i2c_clk(1, dev_seq(bus));
907 if (ret < 0)
908 return ret;
909#endif
910
911
912
913
914
915 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
916 if (ret < 0) {
917 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
918 dev_seq(bus), i2c_bus->base);
919 } else {
920 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
921 "scl-gpios", 0, &i2c_bus->scl_gpio,
922 GPIOD_IS_OUT);
923 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
924 "sda-gpios", 0, &i2c_bus->sda_gpio,
925 GPIOD_IS_OUT);
926 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
927 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
928 ret || ret2) {
929 dev_err(bus,
930 "i2c bus %d at 0x%2lx, fail to request scl/sda gpio\n",
931 dev_seq(bus), i2c_bus->base);
932 return -EINVAL;
933 }
934 }
935
936
937
938
939
940
941 debug("i2c : controller bus %d at %lu , speed %d: ",
942 dev_seq(bus), i2c_bus->base,
943 i2c_bus->speed);
944
945 return 0;
946}
947
948
949static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
950 u32 chip_flags)
951{
952 int ret;
953 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
954
955 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
956 if (ret < 0) {
957 debug("%s failed, ret = %d\n", __func__, ret);
958 return ret;
959 }
960
961 i2c_imx_stop(i2c_bus);
962
963 return 0;
964}
965
966static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
967{
968 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
969 int ret = 0;
970 ulong base = i2c_bus->base;
971 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
972 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
973 int read_mode;
974
975
976
977
978
979 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
980 if (ret < 0) {
981 debug("i2c_init_transfer error: %d\n", ret);
982 return ret;
983 }
984
985 read_mode = -1;
986 for (; nmsgs > 0; nmsgs--, msg++) {
987 const int msg_is_read = !!(msg->flags & I2C_M_RD);
988
989 debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
990 msg->len, msg_is_read ? 'R' : 'W');
991
992 if (msg_is_read != read_mode) {
993
994 if (read_mode != -1) {
995 debug("i2c_xfer: [RSTART]\n");
996 ret = readb(base + (I2CR << reg_shift));
997 ret |= I2CR_RSTA;
998 writeb(ret, base + (I2CR << reg_shift));
999 }
1000 debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1001 msg_is_read ? 'R' : 'W');
1002 ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1003 if (ret < 0) {
1004 debug("i2c_xfer: [STOP]\n");
1005 i2c_imx_stop(i2c_bus);
1006 break;
1007 }
1008 read_mode = msg_is_read;
1009 }
1010
1011 if (msg->flags & I2C_M_RD)
1012 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1013 msg->len, nmsgs == 1 ||
1014 (msg->flags & I2C_M_STOP));
1015 else
1016 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1017 msg->len);
1018
1019 if (ret < 0)
1020 break;
1021 }
1022
1023 if (ret)
1024 debug("i2c_write: error sending\n");
1025
1026 i2c_imx_stop(i2c_bus);
1027
1028 return ret;
1029}
1030
1031static const struct dm_i2c_ops mxc_i2c_ops = {
1032 .xfer = mxc_i2c_xfer,
1033 .probe_chip = mxc_i2c_probe_chip,
1034 .set_bus_speed = mxc_i2c_set_bus_speed,
1035};
1036
1037static const struct udevice_id mxc_i2c_ids[] = {
1038 { .compatible = "fsl,imx21-i2c", },
1039 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1040 {}
1041};
1042
1043U_BOOT_DRIVER(i2c_mxc) = {
1044 .name = "i2c_mxc",
1045 .id = UCLASS_I2C,
1046 .of_match = mxc_i2c_ids,
1047 .probe = mxc_i2c_probe,
1048 .priv_auto = sizeof(struct mxc_i2c_bus),
1049 .ops = &mxc_i2c_ops,
1050 .flags = DM_FLAG_PRE_RELOC,
1051};
1052#endif
1053