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9#include <common.h>
10#include <malloc.h>
11#include <mmc.h>
12#include <asm/global_data.h>
13#include <asm/io.h>
14#include <asm/unaligned.h>
15#include <errno.h>
16#include <dm/device_compat.h>
17#include <linux/bitops.h>
18#include <linux/delay.h>
19#include <mach/jz4780.h>
20#include <wait_bit.h>
21
22
23#define MSC_STRPCL 0x000
24#define MSC_STAT 0x004
25#define MSC_CLKRT 0x008
26#define MSC_CMDAT 0x00c
27#define MSC_RESTO 0x010
28#define MSC_RDTO 0x014
29#define MSC_BLKLEN 0x018
30#define MSC_NOB 0x01c
31#define MSC_SNOB 0x020
32#define MSC_IMASK 0x024
33#define MSC_IREG 0x028
34#define MSC_CMD 0x02c
35#define MSC_ARG 0x030
36#define MSC_RES 0x034
37#define MSC_RXFIFO 0x038
38#define MSC_TXFIFO 0x03c
39#define MSC_LPM 0x040
40#define MSC_DMAC 0x044
41#define MSC_DMANDA 0x048
42#define MSC_DMADA 0x04c
43#define MSC_DMALEN 0x050
44#define MSC_DMACMD 0x054
45#define MSC_CTRL2 0x058
46#define MSC_RTCNT 0x05c
47#define MSC_DBG 0x0fc
48
49
50#define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
51#define MSC_STRPCL_EXIT_TRANSFER BIT(6)
52#define MSC_STRPCL_START_READWAIT BIT(5)
53#define MSC_STRPCL_STOP_READWAIT BIT(4)
54#define MSC_STRPCL_RESET BIT(3)
55#define MSC_STRPCL_START_OP BIT(2)
56#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
57#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
58
59
60#define MSC_STAT_AUTO_CMD_DONE BIT(31)
61#define MSC_STAT_IS_RESETTING BIT(15)
62#define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
63#define MSC_STAT_PRG_DONE BIT(13)
64#define MSC_STAT_DATA_TRAN_DONE BIT(12)
65#define MSC_STAT_END_CMD_RES BIT(11)
66#define MSC_STAT_DATA_FIFO_AFULL BIT(10)
67#define MSC_STAT_IS_READWAIT BIT(9)
68#define MSC_STAT_CLK_EN BIT(8)
69#define MSC_STAT_DATA_FIFO_FULL BIT(7)
70#define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
71#define MSC_STAT_CRC_RES_ERR BIT(5)
72#define MSC_STAT_CRC_READ_ERROR BIT(4)
73#define MSC_STAT_CRC_WRITE_ERROR BIT(2)
74#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
75#define MSC_STAT_TIME_OUT_RES BIT(1)
76#define MSC_STAT_TIME_OUT_READ BIT(0)
77
78
79#define MSC_CLKRT_CLK_RATE_MASK 0x7
80
81
82#define MSC_CMDAT_IO_ABORT BIT(11)
83#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
84#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
85#define MSC_CMDAT_DMA_EN BIT(8)
86#define MSC_CMDAT_INIT BIT(7)
87#define MSC_CMDAT_BUSY BIT(6)
88#define MSC_CMDAT_STREAM_BLOCK BIT(5)
89#define MSC_CMDAT_WRITE BIT(4)
90#define MSC_CMDAT_DATA_EN BIT(3)
91#define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
92#define MSC_CMDAT_RESPONSE_NONE (0x0 << 0)
93#define MSC_CMDAT_RESPONSE_R1 (0x1 << 0)
94#define MSC_CMDAT_RESPONSE_R2 (0x2 << 0)
95#define MSC_CMDAT_RESPONSE_R3 (0x3 << 0)
96#define MSC_CMDAT_RESPONSE_R4 (0x4 << 0)
97#define MSC_CMDAT_RESPONSE_R5 (0x5 << 0)
98#define MSC_CMDAT_RESPONSE_R6 (0x6 << 0)
99
100
101#define MSC_IMASK_TIME_OUT_RES BIT(9)
102#define MSC_IMASK_TIME_OUT_READ BIT(8)
103#define MSC_IMASK_SDIO BIT(7)
104#define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
105#define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
106#define MSC_IMASK_END_CMD_RES BIT(2)
107#define MSC_IMASK_PRG_DONE BIT(1)
108#define MSC_IMASK_DATA_TRAN_DONE BIT(0)
109
110
111#define MSC_IREG_TIME_OUT_RES BIT(9)
112#define MSC_IREG_TIME_OUT_READ BIT(8)
113#define MSC_IREG_SDIO BIT(7)
114#define MSC_IREG_TXFIFO_WR_REQ BIT(6)
115#define MSC_IREG_RXFIFO_RD_REQ BIT(5)
116#define MSC_IREG_END_CMD_RES BIT(2)
117#define MSC_IREG_PRG_DONE BIT(1)
118#define MSC_IREG_DATA_TRAN_DONE BIT(0)
119
120struct jz_mmc_plat {
121 struct mmc_config cfg;
122 struct mmc mmc;
123};
124
125struct jz_mmc_priv {
126 void __iomem *regs;
127 u32 flags;
128
129#define JZ_MMC_BUS_WIDTH_MASK 0x3
130#define JZ_MMC_BUS_WIDTH_1 0x0
131#define JZ_MMC_BUS_WIDTH_4 0x2
132#define JZ_MMC_BUS_WIDTH_8 0x3
133#define JZ_MMC_SENT_INIT BIT(2)
134};
135
136static int jz_mmc_clock_rate(void)
137{
138 return 24000000;
139}
140
141#if CONFIG_IS_ENABLED(MMC_WRITE)
142static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
143{
144 int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
145 const void *buf = data->src;
146
147 while (sz--) {
148 u32 val = get_unaligned_le32(buf);
149
150 wait_for_bit_le32(priv->regs + MSC_IREG,
151 MSC_IREG_TXFIFO_WR_REQ,
152 true, 10000, false);
153 writel(val, priv->regs + MSC_TXFIFO);
154 buf += 4;
155 }
156}
157#else
158static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
159{}
160#endif
161
162static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
163{
164 int sz = data->blocks * data->blocksize;
165 void *buf = data->dest;
166 u32 stat, val;
167
168 do {
169 stat = readl(priv->regs + MSC_STAT);
170
171 if (stat & MSC_STAT_TIME_OUT_READ)
172 return -ETIMEDOUT;
173 if (stat & MSC_STAT_CRC_READ_ERROR)
174 return -EINVAL;
175 if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
176 udelay(10);
177 continue;
178 }
179 do {
180 val = readl(priv->regs + MSC_RXFIFO);
181 if (sz == 1)
182 *(u8 *)buf = (u8)val;
183 else if (sz == 2)
184 put_unaligned_le16(val, buf);
185 else if (sz >= 4)
186 put_unaligned_le32(val, buf);
187 buf += 4;
188 sz -= 4;
189 stat = readl(priv->regs + MSC_STAT);
190 } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
191 } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
192 return 0;
193}
194
195static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
196 struct mmc_cmd *cmd, struct mmc_data *data)
197{
198 u32 stat, mask, cmdat = 0;
199 int i, ret;
200
201
202 writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
203 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
204 MSC_STAT_CLK_EN, false, 10000, false);
205 if (ret)
206 return ret;
207
208 writel(0, priv->regs + MSC_DMAC);
209
210
211 writel(cmd->cmdidx, priv->regs + MSC_CMD);
212 writel(cmd->cmdarg, priv->regs + MSC_ARG);
213
214 if (data) {
215
216 cmdat |= MSC_CMDAT_DATA_EN;
217 if (data->flags & MMC_DATA_WRITE)
218 cmdat |= MSC_CMDAT_WRITE;
219
220 writel(data->blocks, priv->regs + MSC_NOB);
221 writel(data->blocksize, priv->regs + MSC_BLKLEN);
222 } else {
223 writel(0, priv->regs + MSC_NOB);
224 writel(0, priv->regs + MSC_BLKLEN);
225 }
226
227
228 switch (cmd->resp_type) {
229 case MMC_RSP_NONE:
230 break;
231 case MMC_RSP_R1:
232 case MMC_RSP_R1b:
233 cmdat |= MSC_CMDAT_RESPONSE_R1;
234 break;
235 case MMC_RSP_R2:
236 cmdat |= MSC_CMDAT_RESPONSE_R2;
237 break;
238 case MMC_RSP_R3:
239 cmdat |= MSC_CMDAT_RESPONSE_R3;
240 break;
241 default:
242 break;
243 }
244
245 if (cmd->resp_type & MMC_RSP_BUSY)
246 cmdat |= MSC_CMDAT_BUSY;
247
248
249 if (!(priv->flags & JZ_MMC_SENT_INIT)) {
250 cmdat |= MSC_CMDAT_INIT;
251 priv->flags |= JZ_MMC_SENT_INIT;
252 }
253
254 cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
255
256
257 writel(cmdat, priv->regs + MSC_CMDAT);
258
259
260 mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
261 if (data) {
262 mask &= ~MSC_IMASK_DATA_TRAN_DONE;
263 if (data->flags & MMC_DATA_WRITE) {
264 mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
265 } else {
266 mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
267 MSC_IMASK_TIME_OUT_READ);
268 }
269 }
270 writel(mask, priv->regs + MSC_IMASK);
271
272
273 writel(0xffffffff, priv->regs + MSC_IREG);
274
275
276 writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
277 priv->regs + MSC_STRPCL);
278
279
280 for (i = 0; i < 100; i++) {
281 stat = readl(priv->regs + MSC_IREG);
282 stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
283 if (stat)
284 break;
285 mdelay(1);
286 }
287 writel(stat, priv->regs + MSC_IREG);
288 if (stat & MSC_IREG_TIME_OUT_RES)
289 return -ETIMEDOUT;
290
291 if (cmd->resp_type & MMC_RSP_PRESENT) {
292
293 if (cmd->resp_type & MMC_RSP_136) {
294 u16 a, b, c, i;
295
296 a = readw(priv->regs + MSC_RES);
297 for (i = 0; i < 4; i++) {
298 b = readw(priv->regs + MSC_RES);
299 c = readw(priv->regs + MSC_RES);
300 cmd->response[i] =
301 (a << 24) | (b << 8) | (c >> 8);
302 a = c;
303 }
304 } else {
305 cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
306 cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
307 cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
308 }
309 }
310 if (data) {
311 if (data->flags & MMC_DATA_WRITE)
312 jz_mmc_write_data(priv, data);
313 else if (data->flags & MMC_DATA_READ) {
314 ret = jz_mmc_read_data(priv, data);
315 if (ret)
316 return ret;
317 }
318 }
319
320 return 0;
321}
322
323static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
324{
325 u32 real_rate = jz_mmc_clock_rate();
326 u8 clk_div = 0;
327
328
329 while ((real_rate > mmc->clock) && (clk_div < 7)) {
330 real_rate >>= 1;
331 clk_div++;
332 }
333 writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
334
335
336 priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
337 if (mmc->bus_width == 8)
338 priv->flags |= JZ_MMC_BUS_WIDTH_8;
339 else if (mmc->bus_width == 4)
340 priv->flags |= JZ_MMC_BUS_WIDTH_4;
341 else
342 priv->flags |= JZ_MMC_BUS_WIDTH_1;
343
344 return 0;
345}
346
347static int jz_mmc_core_init(struct mmc *mmc)
348{
349 struct jz_mmc_priv *priv = mmc->priv;
350 int ret;
351
352
353 writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
354 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
355 MSC_STAT_IS_RESETTING, false, 10000, false);
356 if (ret)
357 return ret;
358
359
360 writel(0xffff, priv->regs + MSC_RESTO);
361 writel(0xffffffff, priv->regs + MSC_RDTO);
362
363
364 writel(0x1, priv->regs + MSC_LPM);
365
366 return 0;
367}
368
369#if !CONFIG_IS_ENABLED(DM_MMC)
370
371static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
372 struct mmc_data *data)
373{
374 struct jz_mmc_priv *priv = mmc->priv;
375
376 return jz_mmc_send_cmd(mmc, priv, cmd, data);
377}
378
379static int jz_mmc_legacy_set_ios(struct mmc *mmc)
380{
381 struct jz_mmc_priv *priv = mmc->priv;
382
383 return jz_mmc_set_ios(mmc, priv);
384};
385
386static const struct mmc_ops jz_msc_ops = {
387 .send_cmd = jz_mmc_legacy_send_cmd,
388 .set_ios = jz_mmc_legacy_set_ios,
389 .init = jz_mmc_core_init,
390};
391
392static struct jz_mmc_priv jz_mmc_priv_static;
393static struct jz_mmc_plat jz_mmc_plat_static = {
394 .cfg = {
395 .name = "MSC",
396 .ops = &jz_msc_ops,
397
398 .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
399 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
400 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
401 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
402
403 .f_min = 375000,
404 .f_max = 48000000,
405 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
406 },
407};
408
409int jz_mmc_init(void __iomem *base)
410{
411 struct mmc *mmc;
412
413 jz_mmc_priv_static.regs = base;
414
415 mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
416
417 return mmc ? 0 : -ENODEV;
418}
419
420#else
421
422#include <dm.h>
423DECLARE_GLOBAL_DATA_PTR;
424
425static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
426 struct mmc_data *data)
427{
428 struct jz_mmc_priv *priv = dev_get_priv(dev);
429 struct mmc *mmc = mmc_get_mmc_dev(dev);
430
431 return jz_mmc_send_cmd(mmc, priv, cmd, data);
432}
433
434static int jz_mmc_dm_set_ios(struct udevice *dev)
435{
436 struct jz_mmc_priv *priv = dev_get_priv(dev);
437 struct mmc *mmc = mmc_get_mmc_dev(dev);
438
439 return jz_mmc_set_ios(mmc, priv);
440};
441
442static const struct dm_mmc_ops jz_msc_ops = {
443 .send_cmd = jz_mmc_dm_send_cmd,
444 .set_ios = jz_mmc_dm_set_ios,
445};
446
447static int jz_mmc_of_to_plat(struct udevice *dev)
448{
449 struct jz_mmc_priv *priv = dev_get_priv(dev);
450 struct jz_mmc_plat *plat = dev_get_plat(dev);
451 struct mmc_config *cfg;
452 int ret;
453
454 priv->regs = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
455 cfg = &plat->cfg;
456
457 cfg->name = "MSC";
458 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
459
460 ret = mmc_of_parse(dev, cfg);
461 if (ret < 0) {
462 dev_err(dev, "failed to parse host caps\n");
463 return ret;
464 }
465
466 cfg->f_min = 400000;
467 cfg->f_max = 52000000;
468
469 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
470 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
471
472 return 0;
473}
474
475static int jz_mmc_bind(struct udevice *dev)
476{
477 struct jz_mmc_plat *plat = dev_get_plat(dev);
478
479 return mmc_bind(dev, &plat->mmc, &plat->cfg);
480}
481
482static int jz_mmc_probe(struct udevice *dev)
483{
484 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
485 struct jz_mmc_priv *priv = dev_get_priv(dev);
486 struct jz_mmc_plat *plat = dev_get_plat(dev);
487
488 plat->mmc.priv = priv;
489 upriv->mmc = &plat->mmc;
490 return jz_mmc_core_init(&plat->mmc);
491}
492
493static const struct udevice_id jz_mmc_ids[] = {
494 { .compatible = "ingenic,jz4780-mmc" },
495 { }
496};
497
498U_BOOT_DRIVER(jz_mmc_drv) = {
499 .name = "jz_mmc",
500 .id = UCLASS_MMC,
501 .of_match = jz_mmc_ids,
502 .of_to_plat = jz_mmc_of_to_plat,
503 .bind = jz_mmc_bind,
504 .probe = jz_mmc_probe,
505 .priv_auto = sizeof(struct jz_mmc_priv),
506 .plat_auto = sizeof(struct jz_mmc_plat),
507 .ops = &jz_msc_ops,
508};
509#endif
510
