LXR uboot/drivers/mmc/pxa_mmc

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   4 *
   5 * Modified to add driver model (DM) support
   6 * Copyright (C) 2019 Marcel Ziswiler <marcel@ziswiler.com>
   7 *
   8 * Loosely based on the old code and Linux's PXA MMC driver
   9 */
  10
  11#include <common.h>
  12#include <asm/arch/hardware.h>
  13#include <asm/arch/regs-mmc.h>
  14#include <linux/delay.h>
  15#include <linux/errno.h>
  16#include <asm/io.h>
  17#include <dm.h>
  18#include <dm/platform_data/pxa_mmc_gen.h>
  19#include <malloc.h>
  20#include <mmc.h>
  21
  22/* PXAMMC Generic default config for various CPUs */
  23#if defined(CONFIG_CPU_PXA25X)
  24#define PXAMMC_FIFO_SIZE        1
  25#define PXAMMC_MIN_SPEED        312500
  26#define PXAMMC_MAX_SPEED        20000000
  27#define PXAMMC_HOST_CAPS        (0)
  28#elif defined(CONFIG_CPU_PXA27X)
  29#define PXAMMC_CRC_SKIP
  30#define PXAMMC_FIFO_SIZE        32
  31#define PXAMMC_MIN_SPEED        304000
  32#define PXAMMC_MAX_SPEED        19500000
  33#define PXAMMC_HOST_CAPS        (MMC_MODE_4BIT)
  34#elif defined(CONFIG_CPU_MONAHANS)
  35#define PXAMMC_FIFO_SIZE        32
  36#define PXAMMC_MIN_SPEED        304000
  37#define PXAMMC_MAX_SPEED        26000000
  38#define PXAMMC_HOST_CAPS        (MMC_MODE_4BIT | MMC_MODE_HS)
  39#else
  40#error "This CPU isn't supported by PXA MMC!"
  41#endif
  42
  43#define MMC_STAT_ERRORS                                                 \
  44        (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN |       \
  45        MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE |          \
  46        MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)
  47
  48/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
  49#define PXA_MMC_TIMEOUT 100
  50
  51struct pxa_mmc_priv {
  52        struct pxa_mmc_regs *regs;
  53};
  54
  55/* Wait for bit to be set */
  56static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
  57{
  58        struct pxa_mmc_priv *priv = mmc->priv;
  59        struct pxa_mmc_regs *regs = priv->regs;
  60        unsigned int timeout = PXA_MMC_TIMEOUT;
  61
  62        /* Wait for bit to be set */
  63        while (--timeout) {
  64                if (readl(&regs->stat) & mask)
  65                        break;
  66                udelay(10);
  67        }
  68
  69        if (!timeout)
  70                return -ETIMEDOUT;
  71
  72        return 0;
  73}
  74
  75static int pxa_mmc_stop_clock(struct mmc *mmc)
  76{
  77        struct pxa_mmc_priv *priv = mmc->priv;
  78        struct pxa_mmc_regs *regs = priv->regs;
  79        unsigned int timeout = PXA_MMC_TIMEOUT;
  80
  81        /* If the clock aren't running, exit */
  82        if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
  83                return 0;
  84
  85        /* Tell the controller to turn off the clock */
  86        writel(MMC_STRPCL_STOP_CLK, &regs->strpcl);
  87
  88        /* Wait until the clock are off */
  89        while (--timeout) {
  90                if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
  91                        break;
  92                udelay(10);
  93        }
  94
  95        /* The clock refused to stop, scream and die a painful death */
  96        if (!timeout)
  97                return -ETIMEDOUT;
  98
  99        /* The clock stopped correctly */
 100        return 0;
 101}
 102
 103static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 104                             uint32_t cmdat)
 105{
 106        struct pxa_mmc_priv *priv = mmc->priv;
 107        struct pxa_mmc_regs *regs = priv->regs;
 108        int ret;
 109
 110        /* The card can send a "busy" response */
 111        if (cmd->resp_type & MMC_RSP_BUSY)
 112                cmdat |= MMC_CMDAT_BUSY;
 113
 114        /* Inform the controller about response type */
 115        switch (cmd->resp_type) {
 116        case MMC_RSP_R1:
 117        case MMC_RSP_R1b:
 118                cmdat |= MMC_CMDAT_R1;
 119                break;
 120        case MMC_RSP_R2:
 121                cmdat |= MMC_CMDAT_R2;
 122                break;
 123        case MMC_RSP_R3:
 124                cmdat |= MMC_CMDAT_R3;
 125                break;
 126        default:
 127                break;
 128        }
 129
 130        /* Load command and it's arguments into the controller */
 131        writel(cmd->cmdidx, &regs->cmd);
 132        writel(cmd->cmdarg >> 16, &regs->argh);
 133        writel(cmd->cmdarg & 0xffff, &regs->argl);
 134        writel(cmdat, &regs->cmdat);
 135
 136        /* Start the controller clock and wait until they are started */
 137        writel(MMC_STRPCL_START_CLK, &regs->strpcl);
 138
 139        ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
 140        if (ret)
 141                return ret;
 142
 143        /* Correct and happy end */
 144        return 0;
 145}
 146
 147static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
 148{
 149        struct pxa_mmc_priv *priv = mmc->priv;
 150        struct pxa_mmc_regs *regs = priv->regs;
 151        u32 a, b, c;
 152        int i;
 153        int stat;
 154
 155        /* Read the controller status */
 156        stat = readl(&regs->stat);
 157
 158        /*
 159         * Linux says:
 160         * Did I mention this is Sick. We always need to
 161         * discard the upper 8 bits of the first 16-bit word.
 162         */
 163        a = readl(&regs->res) & 0xffff;
 164        for (i = 0; i < 4; i++) {
 165                b = readl(&regs->res) & 0xffff;
 166                c = readl(&regs->res) & 0xffff;
 167                cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
 168                a = c;
 169        }
 170
 171        /* The command response didn't arrive */
 172        if (stat & MMC_STAT_TIME_OUT_RESPONSE) {
 173                return -ETIMEDOUT;
 174        } else if (stat & MMC_STAT_RES_CRC_ERROR &&
 175                   cmd->resp_type & MMC_RSP_CRC) {
 176#ifdef PXAMMC_CRC_SKIP
 177                if (cmd->resp_type & MMC_RSP_136 &&
 178                    cmd->response[0] & (1 << 31))
 179                        printf("Ignoring CRC, this may be dangerous!\n");
 180                else
 181#endif
 182                return -EILSEQ;
 183        }
 184
 185        /* The command response was successfully read */
 186        return 0;
 187}
 188
 189static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
 190{
 191        struct pxa_mmc_priv *priv = mmc->priv;
 192        struct pxa_mmc_regs *regs = priv->regs;
 193        u32 len;
 194        u32 *buf = (uint32_t *)data->dest;
 195        int size;
 196        int ret;
 197
 198        len = data->blocks * data->blocksize;
 199
 200        while (len) {
 201                /* The controller has data ready */
 202                if (readl(&regs->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
 203                        size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
 204                        len -= size;
 205                        size /= 4;
 206
 207                        /* Read data into the buffer */
 208                        while (size--)
 209                                *buf++ = readl(&regs->rxfifo);
 210                }
 211
 212                if (readl(&regs->stat) & MMC_STAT_ERRORS)
 213                        return -EIO;
 214        }
 215
 216        /* Wait for the transmission-done interrupt */
 217        ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
 218        if (ret)
 219                return ret;
 220
 221        return 0;
 222}
 223
 224static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
 225{
 226        struct pxa_mmc_priv *priv = mmc->priv;
 227        struct pxa_mmc_regs *regs = priv->regs;
 228        u32 len;
 229        u32 *buf = (uint32_t *)data->src;
 230        int size;
 231        int ret;
 232
 233        len = data->blocks * data->blocksize;
 234
 235        while (len) {
 236                /* The controller is ready to receive data */
 237                if (readl(&regs->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
 238                        size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
 239                        len -= size;
 240                        size /= 4;
 241
 242                        while (size--)
 243                                writel(*buf++, &regs->txfifo);
 244
 245                        if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
 246                                writel(MMC_PRTBUF_BUF_PART_FULL, &regs->prtbuf);
 247                }
 248
 249                if (readl(&regs->stat) & MMC_STAT_ERRORS)
 250                        return -EIO;
 251        }
 252
 253        /* Wait for the transmission-done interrupt */
 254        ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
 255        if (ret)
 256                return ret;
 257
 258        /* Wait until the data are really written to the card */
 259        ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
 260        if (ret)
 261                return ret;
 262
 263        return 0;
 264}
 265
 266static int pxa_mmc_send_cmd_common(struct pxa_mmc_priv *priv, struct mmc *mmc,
 267                                   struct mmc_cmd *cmd, struct mmc_data *data)
 268{
 269        struct pxa_mmc_regs *regs = priv->regs;
 270        u32 cmdat = 0;
 271        int ret;
 272
 273        /* Stop the controller */
 274        ret = pxa_mmc_stop_clock(mmc);
 275        if (ret)
 276                return ret;
 277
 278        /* If we're doing data transfer, configure the controller accordingly */
 279        if (data) {
 280                writel(data->blocks, &regs->nob);
 281                writel(data->blocksize, &regs->blklen);
 282                /* This delay can be optimized, but stick with max value */
 283                writel(0xffff, &regs->rdto);
 284                cmdat |= MMC_CMDAT_DATA_EN;
 285                if (data->flags & MMC_DATA_WRITE)
 286                        cmdat |= MMC_CMDAT_WRITE;
 287        }
 288
 289        /* Run in 4bit mode if the card can do it */
 290        if (mmc->bus_width == 4)
 291                cmdat |= MMC_CMDAT_SD_4DAT;
 292
 293        /* Execute the command */
 294        ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
 295        if (ret)
 296                return ret;
 297
 298        /* Wait until the command completes */
 299        ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
 300        if (ret)
 301                return ret;
 302
 303        /* Read back the result */
 304        ret = pxa_mmc_cmd_done(mmc, cmd);
 305        if (ret)
 306                return ret;
 307
 308        /* In case there was a data transfer scheduled, do it */
 309        if (data) {
 310                if (data->flags & MMC_DATA_WRITE)
 311                        pxa_mmc_do_write_xfer(mmc, data);
 312                else
 313                        pxa_mmc_do_read_xfer(mmc, data);
 314        }
 315
 316        return 0;
 317}
 318
 319static int pxa_mmc_set_ios_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
 320{
 321        struct pxa_mmc_regs *regs = priv->regs;
 322        u32 tmp;
 323        u32 pxa_mmc_clock;
 324
 325        if (!mmc->clock) {
 326                pxa_mmc_stop_clock(mmc);
 327                return 0;
 328        }
 329
 330        /* PXA3xx can do 26MHz with special settings. */
 331        if (mmc->clock == 26000000) {
 332                writel(0x7, &regs->clkrt);
 333                return 0;
 334        }
 335
 336        /* Set clock to the card the usual way. */
 337        pxa_mmc_clock = 0;
 338        tmp = mmc->cfg->f_max / mmc->clock;
 339        tmp += tmp % 2;
 340
 341        while (tmp > 1) {
 342                pxa_mmc_clock++;
 343                tmp >>= 1;
 344        }
 345
 346        writel(pxa_mmc_clock, &regs->clkrt);
 347
 348        return 0;
 349}
 350
 351static int pxa_mmc_init_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
 352{
 353        struct pxa_mmc_regs *regs = priv->regs;
 354
 355        /* Make sure the clock are stopped */
 356        pxa_mmc_stop_clock(mmc);
 357
 358        /* Turn off SPI mode */
 359        writel(0, &regs->spi);
 360
 361        /* Set up maximum timeout to wait for command response */
 362        writel(MMC_RES_TO_MAX_MASK, &regs->resto);
 363
 364        /* Mask all interrupts */
 365        writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
 366               &regs->i_mask);
 367
 368        return 0;
 369}
 370
 371#if !CONFIG_IS_ENABLED(DM_MMC)
 372static int pxa_mmc_init(struct mmc *mmc)
 373{
 374        struct pxa_mmc_priv *priv = mmc->priv;
 375
 376        return pxa_mmc_init_common(priv, mmc);
 377}
 378
 379static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
 380                           struct mmc_data *data)
 381{
 382        struct pxa_mmc_priv *priv = mmc->priv;
 383
 384        return pxa_mmc_send_cmd_common(priv, mmc, cmd, data);
 385}
 386
 387static int pxa_mmc_set_ios(struct mmc *mmc)
 388{
 389        struct pxa_mmc_priv *priv = mmc->priv;
 390
 391        return pxa_mmc_set_ios_common(priv, mmc);
 392}
 393
 394static const struct mmc_ops pxa_mmc_ops = {
 395        .send_cmd       = pxa_mmc_request,
 396        .set_ios        = pxa_mmc_set_ios,
 397        .init           = pxa_mmc_init,
 398};
 399
 400static struct mmc_config pxa_mmc_cfg = {
 401        .name           = "PXA MMC",
 402        .ops            = &pxa_mmc_ops,
 403        .voltages       = MMC_VDD_32_33 | MMC_VDD_33_34,
 404        .f_max          = PXAMMC_MAX_SPEED,
 405        .f_min          = PXAMMC_MIN_SPEED,
 406        .host_caps      = PXAMMC_HOST_CAPS,
 407        .b_max          = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 408};
 409
 410int pxa_mmc_register(int card_index)
 411{
 412        struct mmc *mmc;
 413        struct pxa_mmc_priv *priv;
 414        u32 reg;
 415        int ret = -ENOMEM;
 416
 417        priv = malloc(sizeof(struct pxa_mmc_priv));
 418        if (!priv)
 419                goto err0;
 420
 421        memset(priv, 0, sizeof(*priv));
 422
 423        switch (card_index) {
 424        case 0:
 425                priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
 426                break;
 427        case 1:
 428                priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
 429                break;
 430        default:
 431                ret = -EINVAL;
 432                printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
 433                       card_index);
 434                goto err1;
 435        }
 436
 437#ifndef CONFIG_CPU_MONAHANS     /* PXA2xx */
 438        reg = readl(CKEN);
 439        reg |= CKEN12_MMC;
 440        writel(reg, CKEN);
 441#else                           /* PXA3xx */
 442        reg = readl(CKENA);
 443        reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
 444        writel(reg, CKENA);
 445#endif
 446
 447        mmc = mmc_create(&pxa_mmc_cfg, priv);
 448        if (!mmc)
 449                goto err1;
 450
 451        return 0;
 452
 453err1:
 454        free(priv);
 455err0:
 456        return ret;
 457}
 458#else /* !CONFIG_IS_ENABLED(DM_MMC) */
 459static int pxa_mmc_probe(struct udevice *dev)
 460{
 461        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 462        struct pxa_mmc_plat *plat = dev_get_plat(dev);
 463        struct mmc_config *cfg = &plat->cfg;
 464        struct mmc *mmc = &plat->mmc;
 465        struct pxa_mmc_priv *priv = dev_get_priv(dev);
 466        u32 reg;
 467
 468        upriv->mmc = mmc;
 469
 470        cfg->b_max      = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 471        cfg->f_max      = PXAMMC_MAX_SPEED;
 472        cfg->f_min      = PXAMMC_MIN_SPEED;
 473        cfg->host_caps  = PXAMMC_HOST_CAPS;
 474        cfg->name       = dev->name;
 475        cfg->voltages   = MMC_VDD_32_33 | MMC_VDD_33_34;
 476
 477        mmc->priv = priv;
 478
 479        priv->regs = plat->base;
 480
 481#ifndef CONFIG_CPU_MONAHANS     /* PXA2xx */
 482        reg = readl(CKEN);
 483        reg |= CKEN12_MMC;
 484        writel(reg, CKEN);
 485#else                           /* PXA3xx */
 486        reg = readl(CKENA);
 487        reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
 488        writel(reg, CKENA);
 489#endif
 490
 491        return pxa_mmc_init_common(priv, mmc);
 492}
 493
 494static int pxa_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 495                            struct mmc_data *data)
 496{
 497        struct pxa_mmc_plat *plat = dev_get_plat(dev);
 498        struct pxa_mmc_priv *priv = dev_get_priv(dev);
 499
 500        return pxa_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
 501}
 502
 503static int pxa_mmc_set_ios(struct udevice *dev)
 504{
 505        struct pxa_mmc_plat *plat = dev_get_plat(dev);
 506        struct pxa_mmc_priv *priv = dev_get_priv(dev);
 507
 508        return pxa_mmc_set_ios_common(priv, &plat->mmc);
 509}
 510
 511static const struct dm_mmc_ops pxa_mmc_ops = {
 512        .get_cd                 = NULL,
 513        .send_cmd               = pxa_mmc_send_cmd,
 514        .set_ios                = pxa_mmc_set_ios,
 515};
 516
 517#if CONFIG_IS_ENABLED(BLK)
 518static int pxa_mmc_bind(struct udevice *dev)
 519{
 520        struct pxa_mmc_plat *plat = dev_get_plat(dev);
 521
 522        return mmc_bind(dev, &plat->mmc, &plat->cfg);
 523}
 524#endif
 525
 526U_BOOT_DRIVER(pxa_mmc) = {
 527#if CONFIG_IS_ENABLED(BLK)
 528        .bind   = pxa_mmc_bind,
 529#endif
 530        .id     = UCLASS_MMC,
 531        .name   = "pxa_mmc",
 532        .ops    = &pxa_mmc_ops,
 533        .priv_auto      = sizeof(struct pxa_mmc_priv),
 534        .probe  = pxa_mmc_probe,
 535};
 536#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
 537