LXR uboot/drivers/mmc/renesas-sdhi.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4 */
   5
   6#include <common.h>
   7#include <bouncebuf.h>
   8#include <clk.h>
   9#include <fdtdec.h>
  10#include <log.h>
  11#include <malloc.h>
  12#include <mmc.h>
  13#include <dm.h>
  14#include <asm/global_data.h>
  15#include <dm/device_compat.h>
  16#include <linux/bitops.h>
  17#include <linux/compat.h>
  18#include <linux/delay.h>
  19#include <linux/dma-direction.h>
  20#include <linux/io.h>
  21#include <linux/sizes.h>
  22#include <power/regulator.h>
  23#include <asm/unaligned.h>
  24#include "tmio-common.h"
  25
  26#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  27    CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  28    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  29
  30/* SCC registers */
  31#define RENESAS_SDHI_SCC_DTCNTL                 0x800
  32#define RENESAS_SDHI_SCC_DTCNTL_TAPEN           BIT(0)
  33#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT    16
  34#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK     0xff
  35#define RENESAS_SDHI_SCC_TAPSET                 0x804
  36#define RENESAS_SDHI_SCC_DT2FF                  0x808
  37#define RENESAS_SDHI_SCC_CKSEL                  0x80c
  38#define RENESAS_SDHI_SCC_CKSEL_DTSEL            BIT(0)
  39#define RENESAS_SDHI_SCC_RVSCNTL                0x810
  40#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN          BIT(0)
  41#define RENESAS_SDHI_SCC_RVSREQ                 0x814
  42#define RENESAS_SDHI_SCC_RVSREQ_RVSERR          BIT(2)
  43#define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP        BIT(1)
  44#define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN      BIT(0)
  45#define RENESAS_SDHI_SCC_SMPCMP                 0x818
  46#define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR         (BIT(24) | BIT(8))
  47#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP       BIT(24)
  48#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN     BIT(8)
  49#define RENESAS_SDHI_SCC_TMPPORT2               0x81c
  50#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN       BIT(31)
  51#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL     BIT(4)
  52#define RENESAS_SDHI_SCC_TMPPORT3               0x828
  53#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0      3
  54#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1      2
  55#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2      1
  56#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3      0
  57#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK   0x3
  58#define RENESAS_SDHI_SCC_TMPPORT4               0x82c
  59#define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  60#define RENESAS_SDHI_SCC_TMPPORT5               0x830
  61#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R  BIT(8)
  62#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W  (0 << 8)
  63#define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK  0x3F
  64#define RENESAS_SDHI_SCC_TMPPORT6               0x834
  65#define RENESAS_SDHI_SCC_TMPPORT7               0x838
  66#define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE        0xa5000000
  67#define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK        0x1f
  68#define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE            BIT(7)
  69
  70#define RENESAS_SDHI_MAX_TAP 3
  71
  72#define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
  73
  74static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
  75        { 0,  0,  0,  0,  0,  1,  1,  2,  3,  4,  5,  5,  6,  6,  7, 11,
  76         15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
  77        { 3,  3,  4,  4,  5,  6,  6,  7,  8,  8,  9,  9, 10, 11, 12, 15,
  78         16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
  79};
  80
  81static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
  82        { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  1,  1,  2,  3,  4,  9,
  83         15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
  84        { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  1,
  85          2,  9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
  86};
  87
  88static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
  89        { 0,  0,  0,  0,  2,  3,  4,  4,  5,  6,  7,  7,  8,  9,  9, 10,
  90         11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
  91        { 1,  2,  2,  3,  4,  4,  5,  6,  6,  7,  8,  9,  9, 10, 11, 12,
  92         13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
  93};
  94
  95static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
  96        { 0,  1,  2,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 15,
  97         16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
  98        { 0,  1,  2,  2,  2,  3,  4,  5,  6,  7,  9, 10, 11, 12, 13, 15,
  99         16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
 100};
 101
 102static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
 103        { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
 104          0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },
 105        { 0,  0,  1,  2,  3,  4,  4,  4,  4,  5,  5,  6,  7,  8, 10, 11,
 106         12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
 107};
 108
 109static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
 110{
 111        /* On R-Car Gen3, MMC0 is at 0xee140000 */
 112        return (uintptr_t)(priv->regbase) == 0xee140000;
 113}
 114
 115static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
 116{
 117        /* read mode */
 118        tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
 119                       (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
 120                       RENESAS_SDHI_SCC_TMPPORT5);
 121
 122        /* access start and stop */
 123        tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
 124                       RENESAS_SDHI_SCC_TMPPORT4);
 125        tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
 126
 127        return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
 128}
 129
 130static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
 131{
 132        /* write mode */
 133        tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
 134                       (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
 135                       RENESAS_SDHI_SCC_TMPPORT5);
 136        tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
 137
 138        /* access start and stop */
 139        tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
 140                       RENESAS_SDHI_SCC_TMPPORT4);
 141        tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
 142}
 143
 144static bool renesas_sdhi_check_scc_error(struct udevice *dev)
 145{
 146        struct tmio_sd_priv *priv = dev_get_priv(dev);
 147        struct mmc *mmc = mmc_get_mmc_dev(dev);
 148        unsigned long new_tap = priv->tap_set;
 149        unsigned long error_tap = priv->tap_set;
 150        u32 reg, smpcmp;
 151
 152        if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 153            (mmc->selected_mode != UHS_SDR104) &&
 154            (mmc->selected_mode != MMC_HS_200) &&
 155            (mmc->selected_mode != MMC_HS_400) &&
 156            (priv->nrtaps != 4))
 157                return false;
 158
 159        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 160        /* Handle automatic tuning correction */
 161        if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
 162                reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 163                if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
 164                        tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 165                        return true;
 166                }
 167
 168                return false;
 169        }
 170
 171        /* Handle manual tuning correction */
 172        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 173        if (!reg)       /* No error */
 174                return false;
 175
 176        tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 177
 178        if (mmc->selected_mode == MMC_HS_400) {
 179                /*
 180                 * Correction Error Status contains CMD and DAT signal status.
 181                 * In HS400, DAT signal based on DS signal, not CLK.
 182                 * Therefore, use only CMD status.
 183                 */
 184                smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
 185                         RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
 186
 187                switch (smpcmp) {
 188                case 0:
 189                        return false;   /* No error in CMD signal */
 190                case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
 191                        new_tap = (priv->tap_set +
 192                                   priv->tap_num + 1) % priv->tap_num;
 193                        error_tap = (priv->tap_set +
 194                                     priv->tap_num - 1) % priv->tap_num;
 195                        break;
 196                case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
 197                        new_tap = (priv->tap_set +
 198                                   priv->tap_num - 1) % priv->tap_num;
 199                        error_tap = (priv->tap_set +
 200                                     priv->tap_num + 1) % priv->tap_num;
 201                        break;
 202                default:
 203                        return true;    /* Need re-tune */
 204                }
 205
 206                if (priv->hs400_bad_tap & BIT(new_tap)) {
 207                        /*
 208                         * New tap is bad tap (cannot change).
 209                         * Compare with HS200 tuning result.
 210                         * In HS200 tuning, when smpcmp[error_tap]
 211                         * is OK, retune is executed.
 212                         */
 213                        if (priv->smpcmp & BIT(error_tap))
 214                                return true;    /* Need retune */
 215
 216                        return false;   /* cannot change */
 217                }
 218
 219                priv->tap_set = new_tap;
 220        } else {
 221                if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
 222                        return true;    /* Need re-tune */
 223                else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
 224                        priv->tap_set = (priv->tap_set +
 225                                         priv->tap_num + 1) % priv->tap_num;
 226                else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
 227                        priv->tap_set = (priv->tap_set +
 228                                         priv->tap_num - 1) % priv->tap_num;
 229                else
 230                        return false;
 231        }
 232
 233        /* Set TAP position */
 234        tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
 235                       RENESAS_SDHI_SCC_TAPSET);
 236
 237        return false;
 238}
 239
 240static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
 241{
 242        u32 calib_code;
 243
 244        if (!priv->adjust_hs400_enable)
 245                return;
 246
 247        if (!priv->needs_adjust_hs400)
 248                return;
 249
 250        if (!priv->adjust_hs400_calib_table)
 251                return;
 252
 253        /*
 254         * Enabled Manual adjust HS400 mode
 255         *
 256         * 1) Disabled Write Protect
 257         *    W(addr=0x00, WP_DISABLE_CODE)
 258         *
 259         * 2) Read Calibration code
 260         *    read_value = R(addr=0x26)
 261         * 3) Refer to calibration table
 262         *    Calibration code = table[read_value]
 263         * 4) Enabled Manual Calibration
 264         *    W(addr=0x22, manual mode | Calibration code)
 265         * 5) Set Offset value to TMPPORT3 Reg
 266         */
 267        sd_scc_tmpport_write32(priv, 0x00,
 268                               RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 269        calib_code = sd_scc_tmpport_read32(priv, 0x26);
 270        calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 271        sd_scc_tmpport_write32(priv, 0x22,
 272                               RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
 273                               priv->adjust_hs400_calib_table[calib_code]);
 274        tmio_sd_writel(priv, priv->adjust_hs400_offset,
 275                       RENESAS_SDHI_SCC_TMPPORT3);
 276
 277        /* Clear flag */
 278        priv->needs_adjust_hs400 = false;
 279}
 280
 281static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
 282{
 283
 284        /* Disabled Manual adjust HS400 mode
 285         *
 286         * 1) Disabled Write Protect
 287         *    W(addr=0x00, WP_DISABLE_CODE)
 288         * 2) Disabled Manual Calibration
 289         *    W(addr=0x22, 0)
 290         * 3) Clear offset value to TMPPORT3 Reg
 291         */
 292        sd_scc_tmpport_write32(priv, 0x00,
 293                               RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 294        sd_scc_tmpport_write32(priv, 0x22, 0);
 295        tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
 296}
 297
 298static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
 299{
 300        u32 reg;
 301
 302        /* Initialize SCC */
 303        tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
 304
 305        reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 306        reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 307        tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 308
 309        /* Set sampling clock selection range */
 310        tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 311                             RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 312                             RENESAS_SDHI_SCC_DTCNTL);
 313
 314        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 315        reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 316        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 317
 318        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 319        reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 320        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 321
 322        tmio_sd_writel(priv, 0x300 /* scc_tappos */,
 323                           RENESAS_SDHI_SCC_DT2FF);
 324
 325        reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 326        reg |= TMIO_SD_CLKCTL_SCLKEN;
 327        tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 328
 329        /* Read TAPNUM */
 330        return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
 331                RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 332                RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 333}
 334
 335static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
 336{
 337        u32 reg;
 338
 339        /* Reset SCC */
 340        reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 341        reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 342        tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 343
 344        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 345        reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
 346        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 347
 348        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 349        reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 350                 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 351        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 352
 353        /* Disable HS400 mode adjustment */
 354        renesas_sdhi_adjust_hs400_mode_disable(priv);
 355
 356        reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 357        reg |= TMIO_SD_CLKCTL_SCLKEN;
 358        tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 359
 360        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 361        reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 362        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 363
 364        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 365        reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 366        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 367}
 368
 369static int renesas_sdhi_hs400(struct udevice *dev)
 370{
 371        struct tmio_sd_priv *priv = dev_get_priv(dev);
 372        struct mmc *mmc = mmc_get_mmc_dev(dev);
 373        bool hs400 = (mmc->selected_mode == MMC_HS_400);
 374        int ret, taps = hs400 ? priv->nrtaps : 8;
 375        unsigned long new_tap;
 376        u32 reg;
 377
 378        if (taps == 4)  /* HS400 on 4tap SoC needs different clock */
 379                ret = clk_set_rate(&priv->clk, 400000000);
 380        else
 381                ret = clk_set_rate(&priv->clk, 200000000);
 382        if (ret < 0)
 383                return ret;
 384
 385        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 386        reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 387        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 388
 389        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 390        if (hs400) {
 391                reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 392                       RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
 393        } else {
 394                reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 395                       RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 396        }
 397
 398        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 399
 400        /* Disable HS400 mode adjustment */
 401        if (!hs400)
 402                renesas_sdhi_adjust_hs400_mode_disable(priv);
 403
 404        tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 405                             RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 406                             RENESAS_SDHI_SCC_DTCNTL);
 407
 408        /* Avoid bad TAP */
 409        if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
 410                new_tap = (priv->tap_set +
 411                           priv->tap_num + 1) % priv->tap_num;
 412
 413                if (priv->hs400_bad_tap & BIT(new_tap))
 414                        new_tap = (priv->tap_set +
 415                                   priv->tap_num - 1) % priv->tap_num;
 416
 417                if (priv->hs400_bad_tap & BIT(new_tap)) {
 418                        new_tap = priv->tap_set;
 419                        debug("Three consecutive bad tap is prohibited\n");
 420                }
 421
 422                priv->tap_set = new_tap;
 423                tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 424        }
 425
 426        if (taps == 4) {
 427                tmio_sd_writel(priv, priv->tap_set >> 1,
 428                               RENESAS_SDHI_SCC_TAPSET);
 429                tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
 430                               RENESAS_SDHI_SCC_DT2FF);
 431        } else {
 432                tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 433                tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
 434        }
 435
 436        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 437        reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 438        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 439
 440        /* Execute adjust hs400 offset after setting to HS400 mode */
 441        if (hs400)
 442                priv->needs_adjust_hs400 = true;
 443
 444        return 0;
 445}
 446
 447static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 448                                       unsigned long tap)
 449{
 450        /* Set sampling clock position */
 451        tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 452}
 453
 454static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 455{
 456        /* Get comparison of sampling data */
 457        return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 458}
 459
 460static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 461                                     unsigned int taps)
 462{
 463        unsigned long tap_cnt;  /* counter of tuning success */
 464        unsigned long tap_start;/* start position of tuning success */
 465        unsigned long tap_end;  /* end position of tuning success */
 466        unsigned long ntap;     /* temporary counter of tuning success */
 467        unsigned long match_cnt;/* counter of matching data */
 468        unsigned long i;
 469        bool select = false;
 470        u32 reg;
 471
 472        priv->needs_adjust_hs400 = false;
 473
 474        /* Clear SCC_RVSREQ */
 475        tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 476
 477        /* Merge the results */
 478        for (i = 0; i < priv->tap_num * 2; i++) {
 479                if (!(taps & BIT(i))) {
 480                        taps &= ~BIT(i % priv->tap_num);
 481                        taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
 482                }
 483                if (!(priv->smpcmp & BIT(i))) {
 484                        priv->smpcmp &= ~BIT(i % priv->tap_num);
 485                        priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
 486                }
 487        }
 488
 489        /*
 490         * Find the longest consecutive run of successful probes.  If that
 491         * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 492         * center index as the tap.
 493         */
 494        tap_cnt = 0;
 495        ntap = 0;
 496        tap_start = 0;
 497        tap_end = 0;
 498        for (i = 0; i < priv->tap_num * 2; i++) {
 499                if (taps & BIT(i))
 500                        ntap++;
 501                else {
 502                        if (ntap > tap_cnt) {
 503                                tap_start = i - ntap;
 504                                tap_end = i - 1;
 505                                tap_cnt = ntap;
 506                        }
 507                        ntap = 0;
 508                }
 509        }
 510
 511        if (ntap > tap_cnt) {
 512                tap_start = i - ntap;
 513                tap_end = i - 1;
 514                tap_cnt = ntap;
 515        }
 516
 517        /*
 518         * If all of the TAP is OK, the sampling clock position is selected by
 519         * identifying the change point of data.
 520         */
 521        if (tap_cnt == priv->tap_num * 2) {
 522                match_cnt = 0;
 523                ntap = 0;
 524                tap_start = 0;
 525                tap_end = 0;
 526                for (i = 0; i < priv->tap_num * 2; i++) {
 527                        if (priv->smpcmp & BIT(i))
 528                                ntap++;
 529                        else {
 530                                if (ntap > match_cnt) {
 531                                        tap_start = i - ntap;
 532                                        tap_end = i - 1;
 533                                        match_cnt = ntap;
 534                                }
 535                                ntap = 0;
 536                        }
 537                }
 538                if (ntap > match_cnt) {
 539                        tap_start = i - ntap;
 540                        tap_end = i - 1;
 541                        match_cnt = ntap;
 542                }
 543                if (match_cnt)
 544                        select = true;
 545        } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 546                select = true;
 547
 548        if (select)
 549                priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
 550        else
 551                return -EIO;
 552
 553        /* Set SCC */
 554        tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 555
 556        /* Enable auto re-tuning */
 557        reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 558        reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 559        tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 560
 561        return 0;
 562}
 563
 564int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 565{
 566        struct tmio_sd_priv *priv = dev_get_priv(dev);
 567        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 568        struct mmc *mmc = upriv->mmc;
 569        unsigned int tap_num;
 570        unsigned int taps = 0;
 571        int i, ret = 0;
 572        u32 caps;
 573
 574        /* Only supported on Renesas RCar */
 575        if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 576                return -EINVAL;
 577
 578        /* clock tuning is not needed for upto 52MHz */
 579        if (!((mmc->selected_mode == MMC_HS_200) ||
 580              (mmc->selected_mode == MMC_HS_400) ||
 581              (mmc->selected_mode == UHS_SDR104) ||
 582              (mmc->selected_mode == UHS_SDR50)))
 583                return 0;
 584
 585        tap_num = renesas_sdhi_init_tuning(priv);
 586        if (!tap_num)
 587                /* Tuning is not supported */
 588                goto out;
 589
 590        priv->tap_num = tap_num;
 591
 592        if (priv->tap_num * 2 >= sizeof(taps) * 8) {
 593                dev_err(dev,
 594                        "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 595                goto out;
 596        }
 597
 598        priv->smpcmp = 0;
 599
 600        /* Issue CMD19 twice for each tap */
 601        for (i = 0; i < 2 * priv->tap_num; i++) {
 602                renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
 603
 604                /* Force PIO for the tuning */
 605                caps = priv->caps;
 606                priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 607
 608                ret = mmc_send_tuning(mmc, opcode, NULL);
 609
 610                priv->caps = caps;
 611
 612                if (ret == 0)
 613                        taps |= BIT(i);
 614
 615                ret = renesas_sdhi_compare_scc_data(priv);
 616                if (ret == 0)
 617                        priv->smpcmp |= BIT(i);
 618
 619                mdelay(1);
 620        }
 621
 622        ret = renesas_sdhi_select_tuning(priv, taps);
 623
 624out:
 625        if (ret < 0) {
 626                dev_warn(dev, "Tuning procedure failed\n");
 627                renesas_sdhi_reset_tuning(priv);
 628        }
 629
 630        return ret;
 631}
 632#else
 633static int renesas_sdhi_hs400(struct udevice *dev)
 634{
 635        return 0;
 636}
 637#endif
 638
 639static int renesas_sdhi_set_ios(struct udevice *dev)
 640{
 641        struct tmio_sd_priv *priv = dev_get_priv(dev);
 642        u32 tmp;
 643        int ret;
 644
 645        /* Stop the clock before changing its rate to avoid a glitch signal */
 646        tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 647        tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
 648        tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
 649
 650        ret = renesas_sdhi_hs400(dev);
 651        if (ret)
 652                return ret;
 653
 654        ret = tmio_sd_set_ios(dev);
 655
 656        mdelay(10);
 657
 658#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 659    CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 660    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 661        struct mmc *mmc = mmc_get_mmc_dev(dev);
 662        if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 663            (mmc->selected_mode != UHS_SDR104) &&
 664            (mmc->selected_mode != MMC_HS_200) &&
 665            (mmc->selected_mode != MMC_HS_400)) {
 666                renesas_sdhi_reset_tuning(priv);
 667        }
 668#endif
 669
 670        return ret;
 671}
 672
 673#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 674static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
 675                                  int timeout_us)
 676{
 677        int ret = -ETIMEDOUT;
 678        bool dat0_high;
 679        bool target_dat0_high = !!state;
 680        struct tmio_sd_priv *priv = dev_get_priv(dev);
 681
 682        timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 683        while (timeout_us--) {
 684                dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
 685                if (dat0_high == target_dat0_high) {
 686                        ret = 0;
 687                        break;
 688                }
 689                udelay(10);
 690        }
 691
 692        return ret;
 693}
 694#endif
 695
 696#define RENESAS_SDHI_DMA_ALIGNMENT      128
 697
 698static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
 699                                         size_t len, size_t len_aligned)
 700{
 701        /* Check if start is aligned */
 702        if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
 703                debug("Unaligned buffer address %lx\n", ubuf);
 704                return 0;
 705        }
 706
 707        /* Check if length is aligned */
 708        if (len != len_aligned) {
 709                debug("Unaligned buffer length %zu\n", len);
 710                return 0;
 711        }
 712
 713#ifdef CONFIG_PHYS_64BIT
 714        /* Check if below 32bit boundary */
 715        if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
 716                debug("Buffer above 32bit boundary %lx-%lx\n",
 717                        ubuf, ubuf + len_aligned);
 718                return 0;
 719        }
 720#endif
 721
 722        /* Aligned */
 723        return 1;
 724}
 725
 726static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
 727{
 728        uintptr_t ubuf = (uintptr_t)state->user_buffer;
 729
 730        return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
 731                                             state->len_aligned);
 732}
 733
 734static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 735                                 struct mmc_data *data)
 736{
 737        struct bounce_buffer bbstate;
 738        unsigned int bbflags;
 739        bool bbok = false;
 740        size_t len;
 741        void *buf;
 742        int ret;
 743
 744        if (data) {
 745                if (data->flags & MMC_DATA_READ) {
 746                        buf = data->dest;
 747                        bbflags = GEN_BB_WRITE;
 748                } else {
 749                        buf = (void *)data->src;
 750                        bbflags = GEN_BB_READ;
 751                }
 752                len = data->blocks * data->blocksize;
 753
 754                ret = bounce_buffer_start_extalign(&bbstate, buf, len, bbflags,
 755                                                   RENESAS_SDHI_DMA_ALIGNMENT,
 756                                                   renesas_sdhi_addr_aligned);
 757                /*
 758                 * If the amount of data to transfer is too large, we can get
 759                 * -ENOMEM when starting the bounce buffer. If that happens,
 760                 *  fall back to PIO as it was before, otherwise use the BB.
 761                 */
 762                if (!ret) {
 763                        bbok = true;
 764                        if (data->flags & MMC_DATA_READ)
 765                                data->dest = bbstate.bounce_buffer;
 766                        else
 767                                data->src = bbstate.bounce_buffer;
 768                }
 769        }
 770
 771        ret = tmio_sd_send_cmd(dev, cmd, data);
 772
 773        if (data && bbok) {
 774                buf = bbstate.user_buffer;
 775
 776                bounce_buffer_stop(&bbstate);
 777
 778                if (data->flags & MMC_DATA_READ)
 779                        data->dest = buf;
 780                else
 781                        data->src = buf;
 782        }
 783
 784        if (ret)
 785                return ret;
 786
 787#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 788    CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 789    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 790        struct tmio_sd_priv *priv = dev_get_priv(dev);
 791
 792        renesas_sdhi_check_scc_error(dev);
 793
 794        if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
 795                renesas_sdhi_adjust_hs400_mode_enable(priv);
 796#endif
 797
 798        return 0;
 799}
 800
 801int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
 802{
 803        struct tmio_sd_priv *priv = dev_get_priv(dev);
 804        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 805        struct mmc *mmc = upriv->mmc;
 806        size_t len = blkcnt * mmc->read_bl_len;
 807        size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
 808
 809        if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
 810                if (priv->quirks & TMIO_SD_CAP_16BIT)
 811                        return U16_MAX;
 812                else
 813                        return U32_MAX;
 814        } else {
 815                return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
 816        }
 817}
 818
 819static const struct dm_mmc_ops renesas_sdhi_ops = {
 820        .send_cmd = renesas_sdhi_send_cmd,
 821        .set_ios = renesas_sdhi_set_ios,
 822        .get_cd = tmio_sd_get_cd,
 823#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 824    CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 825    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 826        .execute_tuning = renesas_sdhi_execute_tuning,
 827#endif
 828#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 829        .wait_dat0 = renesas_sdhi_wait_dat0,
 830#endif
 831        .get_b_max = renesas_sdhi_get_b_max,
 832};
 833
 834#define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 835#define RENESAS_GEN3_QUIRKS                             \
 836        TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 837
 838static const struct udevice_id renesas_sdhi_match[] = {
 839        { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 840        { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 841        { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 842        { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 843        { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 844        { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 845        { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 846        { .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS },
 847        { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 848        { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 849        { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 850        { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 851        { /* sentinel */ }
 852};
 853
 854static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 855{
 856        return clk_get_rate(&priv->clk);
 857}
 858
 859static void renesas_sdhi_filter_caps(struct udevice *dev)
 860{
 861        struct tmio_sd_priv *priv = dev_get_priv(dev);
 862
 863        if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
 864                return;
 865
 866        if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL)
 867                priv->idma_bus_width = TMIO_SD_DMA_MODE_BUS_WIDTH;
 868
 869#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 870    CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 871    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 872        struct tmio_sd_plat *plat = dev_get_plat(dev);
 873
 874        /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
 875        if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 876            (rmobile_get_cpu_rev_integer() <= 1)) ||
 877            ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 878            (rmobile_get_cpu_rev_integer() == 1) &&
 879            (rmobile_get_cpu_rev_fraction() < 2)))
 880                plat->cfg.host_caps &= ~MMC_MODE_HS400;
 881
 882        /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
 883        if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 884            (rmobile_get_cpu_rev_integer() >= 2)) ||
 885            ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 886            (rmobile_get_cpu_rev_integer() == 1) &&
 887            (rmobile_get_cpu_rev_fraction() == 2)) ||
 888            (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
 889                priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
 890
 891        /* H3 ES3.0 can use HS400 with manual adjustment */
 892        if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 893            (rmobile_get_cpu_rev_integer() >= 3)) {
 894                priv->adjust_hs400_enable = true;
 895                priv->adjust_hs400_offset = 0;
 896                priv->adjust_hs400_calib_table =
 897                        r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
 898        }
 899
 900        /* M3W ES1.2 can use HS400 with manual adjustment */
 901        if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 902            (rmobile_get_cpu_rev_integer() == 1) &&
 903            (rmobile_get_cpu_rev_fraction() == 2)) {
 904                priv->adjust_hs400_enable = true;
 905                priv->adjust_hs400_offset = 3;
 906                priv->adjust_hs400_calib_table =
 907                        r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
 908        }
 909
 910        /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
 911        if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 912            (rmobile_get_cpu_rev_integer() == 1) &&
 913            (rmobile_get_cpu_rev_fraction() > 2)) {
 914                priv->adjust_hs400_enable = true;
 915                priv->adjust_hs400_offset = 0;
 916                priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
 917                priv->adjust_hs400_calib_table =
 918                        r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
 919        }
 920
 921        /* M3N can use HS400 with manual adjustment */
 922        if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
 923                priv->adjust_hs400_enable = true;
 924                priv->adjust_hs400_offset = 3;
 925                priv->adjust_hs400_calib_table =
 926                        r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
 927        }
 928
 929        /* E3 can use HS400 with manual adjustment */
 930        if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
 931                priv->adjust_hs400_enable = true;
 932                priv->adjust_hs400_offset = 3;
 933                priv->adjust_hs400_calib_table =
 934                        r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
 935        }
 936
 937        /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
 938        if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 939            (rmobile_get_cpu_rev_integer() <= 2)) ||
 940            ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 941            (rmobile_get_cpu_rev_integer() == 1) &&
 942            (rmobile_get_cpu_rev_fraction() <= 2)))
 943                priv->nrtaps = 4;
 944        else
 945                priv->nrtaps = 8;
 946#endif
 947        /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
 948        if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 949            (rmobile_get_cpu_rev_integer() <= 1)) ||
 950            ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 951            (rmobile_get_cpu_rev_integer() == 1) &&
 952            (rmobile_get_cpu_rev_fraction() == 0)))
 953                priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
 954        else
 955                priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
 956}
 957
 958static int renesas_sdhi_probe(struct udevice *dev)
 959{
 960        struct tmio_sd_priv *priv = dev_get_priv(dev);
 961        u32 quirks = dev_get_driver_data(dev);
 962        struct fdt_resource reg_res;
 963        DECLARE_GLOBAL_DATA_PTR;
 964        int ret;
 965
 966        priv->clk_get_rate = renesas_sdhi_clk_get_rate;
 967
 968        if (quirks == RENESAS_GEN2_QUIRKS) {
 969                ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 970                                       "reg", 0, &reg_res);
 971                if (ret < 0) {
 972                        dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 973                                ret);
 974                        return ret;
 975                }
 976
 977                if (fdt_resource_size(&reg_res) == 0x100)
 978                        quirks |= TMIO_SD_CAP_16BIT;
 979        }
 980
 981        ret = clk_get_by_index(dev, 0, &priv->clk);
 982        if (ret < 0) {
 983                dev_err(dev, "failed to get host clock\n");
 984                return ret;
 985        }
 986
 987        /* set to max rate */
 988        ret = clk_set_rate(&priv->clk, 200000000);
 989        if (ret < 0) {
 990                dev_err(dev, "failed to set rate for host clock\n");
 991                clk_free(&priv->clk);
 992                return ret;
 993        }
 994
 995        ret = clk_enable(&priv->clk);
 996        if (ret) {
 997                dev_err(dev, "failed to enable host clock\n");
 998                return ret;
 999        }
1000

1001        priv->quirks = quirks;
1002        ret = tmio_sd_probe(dev, quirks);
1003
1004        renesas_sdhi_filter_caps(dev);
1005
1006#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
1007    CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
1008    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1009        if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
1010                renesas_sdhi_reset_tuning(priv);
1011#endif
1012        return ret;
1013}
1014
1015U_BOOT_DRIVER(renesas_sdhi) = {
1016        .name = "renesas-sdhi",
1017        .id = UCLASS_MMC,
1018        .of_match = renesas_sdhi_match,
1019        .bind = tmio_sd_bind,
1020        .probe = renesas_sdhi_probe,
1021        .priv_auto      = sizeof(struct tmio_sd_priv),
1022        .plat_auto      = sizeof(struct tmio_sd_plat),
1023        .ops = &renesas_sdhi_ops,
1024};
1025