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29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31#include <common.h>
32#include <log.h>
33#include <malloc.h>
34#include <watchdog.h>
35#include <dm/devres.h>
36#include <linux/bitops.h>
37#include <linux/bug.h>
38#include <linux/delay.h>
39#include <linux/err.h>
40#include <linux/compat.h>
41#include <linux/mtd/mtd.h>
42#include <linux/mtd/rawnand.h>
43#include <linux/mtd/nand_ecc.h>
44#include <linux/mtd/nand_bch.h>
45#ifdef CONFIG_MTD_PARTITIONS
46#include <linux/mtd/partitions.h>
47#endif
48#include <asm/io.h>
49#include <linux/errno.h>
50
51
52#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
53static struct nand_ecclayout nand_oob_8 = {
54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
60 .length = 2} }
61};
62
63static struct nand_ecclayout nand_oob_16 = {
64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
66 .oobfree = {
67 {.offset = 8,
68 . length = 8} }
69};
70
71static struct nand_ecclayout nand_oob_64 = {
72 .eccbytes = 24,
73 .eccpos = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
77 .oobfree = {
78 {.offset = 2,
79 .length = 38} }
80};
81
82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
93 .length = 78} }
94};
95#endif
96
97static int nand_get_device(struct mtd_info *mtd, int new_state);
98
99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
102
103
104
105
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd_to_nand(mtd);
112 int ret = 0;
113
114
115 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
116 pr_debug("%s: unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120
121 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
122 pr_debug("%s: length not block aligned\n", __func__);
123 ret = -EINVAL;
124 }
125
126 return ret;
127}
128
129
130
131
132
133
134
135static void nand_release_device(struct mtd_info *mtd)
136{
137 struct nand_chip *chip = mtd_to_nand(mtd);
138
139
140 chip->select_chip(mtd, -1);
141}
142
143
144
145
146
147
148
149uint8_t nand_read_byte(struct mtd_info *mtd)
150{
151 struct nand_chip *chip = mtd_to_nand(mtd);
152 return readb(chip->IO_ADDR_R);
153}
154
155
156
157
158
159
160
161
162static uint8_t nand_read_byte16(struct mtd_info *mtd)
163{
164 struct nand_chip *chip = mtd_to_nand(mtd);
165 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
166}
167
168
169
170
171
172
173
174static u16 nand_read_word(struct mtd_info *mtd)
175{
176 struct nand_chip *chip = mtd_to_nand(mtd);
177 return readw(chip->IO_ADDR_R);
178}
179
180
181
182
183
184
185
186
187static void nand_select_chip(struct mtd_info *mtd, int chipnr)
188{
189 struct nand_chip *chip = mtd_to_nand(mtd);
190
191 switch (chipnr) {
192 case -1:
193 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
194 break;
195 case 0:
196 break;
197
198 default:
199 BUG();
200 }
201}
202
203
204
205
206
207
208
209
210static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
211{
212 struct nand_chip *chip = mtd_to_nand(mtd);
213
214 chip->write_buf(mtd, &byte, 1);
215}
216
217
218
219
220
221
222
223
224static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
225{
226 struct nand_chip *chip = mtd_to_nand(mtd);
227 uint16_t word = byte;
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245 chip->write_buf(mtd, (uint8_t *)&word, 2);
246}
247
248static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
249{
250 int i;
251
252 for (i = 0; i < len; i++)
253 writeb(buf[i], addr);
254}
255static void ioread8_rep(void *addr, uint8_t *buf, int len)
256{
257 int i;
258
259 for (i = 0; i < len; i++)
260 buf[i] = readb(addr);
261}
262
263static void ioread16_rep(void *addr, void *buf, int len)
264{
265 int i;
266 u16 *p = (u16 *) buf;
267
268 for (i = 0; i < len; i++)
269 p[i] = readw(addr);
270}
271
272static void iowrite16_rep(void *addr, void *buf, int len)
273{
274 int i;
275 u16 *p = (u16 *) buf;
276
277 for (i = 0; i < len; i++)
278 writew(p[i], addr);
279}
280
281
282
283
284
285
286
287
288
289void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
290{
291 struct nand_chip *chip = mtd_to_nand(mtd);
292
293 iowrite8_rep(chip->IO_ADDR_W, buf, len);
294}
295
296
297
298
299
300
301
302
303
304void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
305{
306 struct nand_chip *chip = mtd_to_nand(mtd);
307
308 ioread8_rep(chip->IO_ADDR_R, buf, len);
309}
310
311
312
313
314
315
316
317
318
319void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
320{
321 struct nand_chip *chip = mtd_to_nand(mtd);
322 u16 *p = (u16 *) buf;
323
324 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
325}
326
327
328
329
330
331
332
333
334
335void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
336{
337 struct nand_chip *chip = mtd_to_nand(mtd);
338 u16 *p = (u16 *) buf;
339
340 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
341}
342
343
344
345
346
347
348
349
350static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
351{
352 int page, res = 0, i = 0;
353 struct nand_chip *chip = mtd_to_nand(mtd);
354 u16 bad;
355
356 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
357 ofs += mtd->erasesize - mtd->writesize;
358
359 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
360
361 do {
362 if (chip->options & NAND_BUSWIDTH_16) {
363 chip->cmdfunc(mtd, NAND_CMD_READOOB,
364 chip->badblockpos & 0xFE, page);
365 bad = cpu_to_le16(chip->read_word(mtd));
366 if (chip->badblockpos & 0x1)
367 bad >>= 8;
368 else
369 bad &= 0xFF;
370 } else {
371 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
372 page);
373 bad = chip->read_byte(mtd);
374 }
375
376 if (likely(chip->badblockbits == 8))
377 res = bad != 0xFF;
378 else
379 res = hweight8(bad) < chip->badblockbits;
380 ofs += mtd->writesize;
381 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
382 i++;
383 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
384
385 return res;
386}
387
388
389
390
391
392
393
394
395
396
397static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
398{
399 struct nand_chip *chip = mtd_to_nand(mtd);
400 struct mtd_oob_ops ops;
401 uint8_t buf[2] = { 0, 0 };
402 int ret = 0, res, i = 0;
403
404 memset(&ops, 0, sizeof(ops));
405 ops.oobbuf = buf;
406 ops.ooboffs = chip->badblockpos;
407 if (chip->options & NAND_BUSWIDTH_16) {
408 ops.ooboffs &= ~0x01;
409 ops.len = ops.ooblen = 2;
410 } else {
411 ops.len = ops.ooblen = 1;
412 }
413 ops.mode = MTD_OPS_PLACE_OOB;
414
415
416 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
417 ofs += mtd->erasesize - mtd->writesize;
418 do {
419 res = nand_do_write_oob(mtd, ofs, &ops);
420 if (!ret)
421 ret = res;
422
423 i++;
424 ofs += mtd->writesize;
425 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
426
427 return ret;
428}
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
448{
449 struct nand_chip *chip = mtd_to_nand(mtd);
450 int res, ret = 0;
451
452 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
453 struct erase_info einfo;
454
455
456 memset(&einfo, 0, sizeof(einfo));
457 einfo.mtd = mtd;
458 einfo.addr = ofs;
459 einfo.len = 1ULL << chip->phys_erase_shift;
460 nand_erase_nand(mtd, &einfo, 0);
461
462
463 nand_get_device(mtd, FL_WRITING);
464 ret = chip->block_markbad(mtd, ofs);
465 nand_release_device(mtd);
466 }
467
468
469 if (chip->bbt) {
470 res = nand_markbad_bbt(mtd, ofs);
471 if (!ret)
472 ret = res;
473 }
474
475 if (!ret)
476 mtd->ecc_stats.badblocks++;
477
478 return ret;
479}
480
481
482
483
484
485
486
487
488static int nand_check_wp(struct mtd_info *mtd)
489{
490 struct nand_chip *chip = mtd_to_nand(mtd);
491 u8 status;
492 int ret;
493
494
495 if (chip->options & NAND_BROKEN_XD)
496 return 0;
497
498
499 ret = nand_status_op(chip, &status);
500 if (ret)
501 return ret;
502
503 return status & NAND_STATUS_WP ? 0 : 1;
504}
505
506
507
508
509
510
511
512
513static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
514{
515 struct nand_chip *chip = mtd_to_nand(mtd);
516
517 if (!chip->bbt)
518 return 0;
519
520 return nand_isreserved_bbt(mtd, ofs);
521}
522
523
524
525
526
527
528
529
530
531
532static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
533{
534 struct nand_chip *chip = mtd_to_nand(mtd);
535
536 if (!(chip->options & NAND_SKIP_BBTSCAN) &&
537 !(chip->options & NAND_BBT_SCANNED)) {
538 chip->options |= NAND_BBT_SCANNED;
539 chip->scan_bbt(mtd);
540 }
541
542 if (!chip->bbt)
543 return chip->block_bad(mtd, ofs);
544
545
546 return nand_isbad_bbt(mtd, ofs, allowbbt);
547}
548
549
550
551
552
553
554
555void nand_wait_ready(struct mtd_info *mtd)
556{
557 struct nand_chip *chip = mtd_to_nand(mtd);
558 u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
559 u32 time_start;
560
561 time_start = get_timer(0);
562
563 while (get_timer(time_start) < timeo) {
564 if (chip->dev_ready)
565 if (chip->dev_ready(mtd))
566 break;
567 }
568
569 if (!chip->dev_ready(mtd))
570 pr_warn("timeout while waiting for chip to become ready\n");
571}
572EXPORT_SYMBOL_GPL(nand_wait_ready);
573
574
575
576
577
578
579
580
581static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
582{
583 register struct nand_chip *chip = mtd_to_nand(mtd);
584 u32 time_start;
585 int ret;
586
587 timeo = (CONFIG_SYS_HZ * timeo) / 1000;
588 time_start = get_timer(0);
589 while (get_timer(time_start) < timeo) {
590 u8 status;
591
592 ret = nand_read_data_op(chip, &status, sizeof(status), true);
593 if (ret)
594 return;
595
596 if (status & NAND_STATUS_READY)
597 break;
598 WATCHDOG_RESET();
599 }
600};
601
602
603
604
605
606
607
608
609
610
611
612static void nand_command(struct mtd_info *mtd, unsigned int command,
613 int column, int page_addr)
614{
615 register struct nand_chip *chip = mtd_to_nand(mtd);
616 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
617
618
619 if (command == NAND_CMD_SEQIN) {
620 int readcmd;
621
622 if (column >= mtd->writesize) {
623
624 column -= mtd->writesize;
625 readcmd = NAND_CMD_READOOB;
626 } else if (column < 256) {
627
628 readcmd = NAND_CMD_READ0;
629 } else {
630 column -= 256;
631 readcmd = NAND_CMD_READ1;
632 }
633 chip->cmd_ctrl(mtd, readcmd, ctrl);
634 ctrl &= ~NAND_CTRL_CHANGE;
635 }
636 chip->cmd_ctrl(mtd, command, ctrl);
637
638
639 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
640
641 if (column != -1) {
642
643 if (chip->options & NAND_BUSWIDTH_16 &&
644 !nand_opcode_8bits(command))
645 column >>= 1;
646 chip->cmd_ctrl(mtd, column, ctrl);
647 ctrl &= ~NAND_CTRL_CHANGE;
648 }
649 if (page_addr != -1) {
650 chip->cmd_ctrl(mtd, page_addr, ctrl);
651 ctrl &= ~NAND_CTRL_CHANGE;
652 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
653 if (chip->options & NAND_ROW_ADDR_3)
654 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
655 }
656 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
657
658
659
660
661
662 switch (command) {
663
664 case NAND_CMD_PAGEPROG:
665 case NAND_CMD_ERASE1:
666 case NAND_CMD_ERASE2:
667 case NAND_CMD_SEQIN:
668 case NAND_CMD_STATUS:
669 case NAND_CMD_READID:
670 case NAND_CMD_SET_FEATURES:
671 return;
672
673 case NAND_CMD_RESET:
674 if (chip->dev_ready)
675 break;
676 udelay(chip->chip_delay);
677 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
678 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
679 chip->cmd_ctrl(mtd,
680 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
681
682 nand_wait_status_ready(mtd, 250);
683 return;
684
685
686 default:
687
688
689
690
691 if (!chip->dev_ready) {
692 udelay(chip->chip_delay);
693 return;
694 }
695 }
696
697
698
699
700 ndelay(100);
701
702 nand_wait_ready(mtd);
703}
704
705
706
707
708
709
710
711
712
713
714
715
716static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
717 int column, int page_addr)
718{
719 register struct nand_chip *chip = mtd_to_nand(mtd);
720
721
722 if (command == NAND_CMD_READOOB) {
723 column += mtd->writesize;
724 command = NAND_CMD_READ0;
725 }
726
727
728 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
729
730 if (column != -1 || page_addr != -1) {
731 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
732
733
734 if (column != -1) {
735
736 if (chip->options & NAND_BUSWIDTH_16 &&
737 !nand_opcode_8bits(command))
738 column >>= 1;
739 chip->cmd_ctrl(mtd, column, ctrl);
740 ctrl &= ~NAND_CTRL_CHANGE;
741 chip->cmd_ctrl(mtd, column >> 8, ctrl);
742 }
743 if (page_addr != -1) {
744 chip->cmd_ctrl(mtd, page_addr, ctrl);
745 chip->cmd_ctrl(mtd, page_addr >> 8,
746 NAND_NCE | NAND_ALE);
747 if (chip->options & NAND_ROW_ADDR_3)
748 chip->cmd_ctrl(mtd, page_addr >> 16,
749 NAND_NCE | NAND_ALE);
750 }
751 }
752 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
753
754
755
756
757
758 switch (command) {
759
760 case NAND_CMD_CACHEDPROG:
761 case NAND_CMD_PAGEPROG:
762 case NAND_CMD_ERASE1:
763 case NAND_CMD_ERASE2:
764 case NAND_CMD_SEQIN:
765 case NAND_CMD_RNDIN:
766 case NAND_CMD_STATUS:
767 case NAND_CMD_READID:
768 case NAND_CMD_SET_FEATURES:
769 return;
770
771 case NAND_CMD_RESET:
772 if (chip->dev_ready)
773 break;
774 udelay(chip->chip_delay);
775 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
776 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
777 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
778 NAND_NCE | NAND_CTRL_CHANGE);
779
780 nand_wait_status_ready(mtd, 250);
781 return;
782
783 case NAND_CMD_RNDOUT:
784
785 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
786 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
787 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
788 NAND_NCE | NAND_CTRL_CHANGE);
789 return;
790
791 case NAND_CMD_READ0:
792 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
793 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
794 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
795 NAND_NCE | NAND_CTRL_CHANGE);
796
797
798 default:
799
800
801
802
803 if (!chip->dev_ready) {
804 udelay(chip->chip_delay);
805 return;
806 }
807 }
808
809
810
811
812
813 ndelay(100);
814
815 nand_wait_ready(mtd);
816}
817
818
819
820
821
822
823
824
825
826static void panic_nand_get_device(struct nand_chip *chip,
827 struct mtd_info *mtd, int new_state)
828{
829
830 chip->controller->active = chip;
831 chip->state = new_state;
832}
833
834
835
836
837
838
839
840
841static int
842nand_get_device(struct mtd_info *mtd, int new_state)
843{
844 struct nand_chip *chip = mtd_to_nand(mtd);
845 chip->state = new_state;
846 return 0;
847}
848
849
850
851
852
853
854
855
856
857
858
859static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
860 unsigned long timeo)
861{
862 int i;
863 for (i = 0; i < timeo; i++) {
864 if (chip->dev_ready) {
865 if (chip->dev_ready(mtd))
866 break;
867 } else {
868 int ret;
869 u8 status;
870
871 ret = nand_read_data_op(chip, &status, sizeof(status),
872 true);
873 if (ret)
874 return;
875
876 if (status & NAND_STATUS_READY)
877 break;
878 }
879 mdelay(1);
880 }
881}
882
883
884
885
886
887
888
889
890static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
891{
892 unsigned long timeo = 400;
893 u8 status;
894 int ret;
895
896 led_trigger_event(nand_led_trigger, LED_FULL);
897
898
899
900
901
902 ndelay(100);
903
904 ret = nand_status_op(chip, NULL);
905 if (ret)
906 return ret;
907
908 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
909 u32 time_start;
910
911 time_start = get_timer(0);
912 while (get_timer(time_start) < timer) {
913 if (chip->dev_ready) {
914 if (chip->dev_ready(mtd))
915 break;
916 } else {
917 ret = nand_read_data_op(chip, &status,
918 sizeof(status), true);
919 if (ret)
920 return ret;
921
922 if (status & NAND_STATUS_READY)
923 break;
924 }
925 }
926 led_trigger_event(nand_led_trigger, LED_OFF);
927
928 ret = nand_read_data_op(chip, &status, sizeof(status), true);
929 if (ret)
930 return ret;
931
932
933 WARN_ON(!(status & NAND_STATUS_READY));
934 return status;
935}
936
937
938
939
940
941
942
943
944
945
946static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
947{
948 struct mtd_info *mtd = nand_to_mtd(chip);
949 const struct nand_data_interface *conf;
950 int ret;
951
952 if (!chip->setup_data_interface)
953 return 0;
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969 conf = nand_get_default_data_interface();
970 ret = chip->setup_data_interface(mtd, chipnr, conf);
971 if (ret)
972 pr_err("Failed to configure data interface to SDR timing mode 0\n");
973
974 return ret;
975}
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
991{
992 struct mtd_info *mtd = nand_to_mtd(chip);
993 int ret;
994
995 if (!chip->setup_data_interface || !chip->data_interface)
996 return 0;
997
998
999
1000
1001
1002 if (chip->onfi_version) {
1003 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
1004 chip->onfi_timing_mode_default,
1005 };
1006
1007 ret = chip->onfi_set_features(mtd, chip,
1008 ONFI_FEATURE_ADDR_TIMING_MODE,
1009 tmode_param);
1010 if (ret)
1011 goto err;
1012 }
1013
1014 ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
1015err:
1016 return ret;
1017}
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033static int nand_init_data_interface(struct nand_chip *chip)
1034{
1035 struct mtd_info *mtd = nand_to_mtd(chip);
1036 int modes, mode, ret;
1037
1038 if (!chip->setup_data_interface)
1039 return 0;
1040
1041
1042
1043
1044
1045
1046 modes = onfi_get_async_timing_mode(chip);
1047 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1048 if (!chip->onfi_timing_mode_default)
1049 return 0;
1050
1051 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1052 }
1053
1054 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1055 GFP_KERNEL);
1056 if (!chip->data_interface)
1057 return -ENOMEM;
1058
1059 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1060 ret = onfi_init_data_interface(chip, chip->data_interface,
1061 NAND_SDR_IFACE, mode);
1062 if (ret)
1063 continue;
1064
1065
1066 ret = chip->setup_data_interface(mtd,
1067 NAND_DATA_IFACE_CHECK_ONLY,
1068 chip->data_interface);
1069 if (!ret) {
1070 chip->onfi_timing_mode_default = mode;
1071 break;
1072 }
1073 }
1074
1075 return 0;
1076}
1077
1078static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
1079{
1080 kfree(chip->data_interface);
1081}
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1097 unsigned int offset_in_page, void *buf, unsigned int len)
1098{
1099 struct mtd_info *mtd = nand_to_mtd(chip);
1100
1101 if (len && !buf)
1102 return -EINVAL;
1103
1104 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1105 return -EINVAL;
1106
1107 chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page);
1108 if (len)
1109 chip->read_buf(mtd, buf, len);
1110
1111 return 0;
1112}
1113EXPORT_SYMBOL_GPL(nand_read_page_op);
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
1128 unsigned int len)
1129{
1130 struct mtd_info *mtd = nand_to_mtd(chip);
1131 unsigned int i;
1132 u8 *p = buf;
1133
1134 if (len && !buf)
1135 return -EINVAL;
1136
1137 chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1);
1138 for (i = 0; i < len; i++)
1139 p[i] = chip->read_byte(mtd);
1140
1141 return 0;
1142}
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157int nand_change_read_column_op(struct nand_chip *chip,
1158 unsigned int offset_in_page, void *buf,
1159 unsigned int len, bool force_8bit)
1160{
1161 struct mtd_info *mtd = nand_to_mtd(chip);
1162
1163 if (len && !buf)
1164 return -EINVAL;
1165
1166 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1167 return -EINVAL;
1168
1169 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1);
1170 if (len)
1171 chip->read_buf(mtd, buf, len);
1172
1173 return 0;
1174}
1175EXPORT_SYMBOL_GPL(nand_change_read_column_op);
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1191 unsigned int offset_in_oob, void *buf, unsigned int len)
1192{
1193 struct mtd_info *mtd = nand_to_mtd(chip);
1194
1195 if (len && !buf)
1196 return -EINVAL;
1197
1198 if (offset_in_oob + len > mtd->oobsize)
1199 return -EINVAL;
1200
1201 chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page);
1202 if (len)
1203 chip->read_buf(mtd, buf, len);
1204
1205 return 0;
1206}
1207EXPORT_SYMBOL_GPL(nand_read_oob_op);
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1223 unsigned int offset_in_page, const void *buf,
1224 unsigned int len)
1225{
1226 struct mtd_info *mtd = nand_to_mtd(chip);
1227
1228 if (len && !buf)
1229 return -EINVAL;
1230
1231 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1232 return -EINVAL;
1233
1234 chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
1235
1236 if (buf)
1237 chip->write_buf(mtd, buf, len);
1238
1239 return 0;
1240}
1241EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252int nand_prog_page_end_op(struct nand_chip *chip)
1253{
1254 struct mtd_info *mtd = nand_to_mtd(chip);
1255 int status;
1256
1257 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1258
1259 status = chip->waitfunc(mtd, chip);
1260 if (status & NAND_STATUS_FAIL)
1261 return -EIO;
1262
1263 return 0;
1264}
1265EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1281 unsigned int offset_in_page, const void *buf,
1282 unsigned int len)
1283{
1284 struct mtd_info *mtd = nand_to_mtd(chip);
1285 int status;
1286
1287 if (!len || !buf)
1288 return -EINVAL;
1289
1290 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1291 return -EINVAL;
1292
1293 chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
1294 chip->write_buf(mtd, buf, len);
1295 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1296
1297 status = chip->waitfunc(mtd, chip);
1298 if (status & NAND_STATUS_FAIL)
1299 return -EIO;
1300
1301 return 0;
1302}
1303EXPORT_SYMBOL_GPL(nand_prog_page_op);
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318int nand_change_write_column_op(struct nand_chip *chip,
1319 unsigned int offset_in_page,
1320 const void *buf, unsigned int len,
1321 bool force_8bit)
1322{
1323 struct mtd_info *mtd = nand_to_mtd(chip);
1324
1325 if (len && !buf)
1326 return -EINVAL;
1327
1328 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1329 return -EINVAL;
1330
1331 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1);
1332 if (len)
1333 chip->write_buf(mtd, buf, len);
1334
1335 return 0;
1336}
1337EXPORT_SYMBOL_GPL(nand_change_write_column_op);
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1353 unsigned int len)
1354{
1355 struct mtd_info *mtd = nand_to_mtd(chip);
1356 unsigned int i;
1357 u8 *id = buf;
1358
1359 if (len && !buf)
1360 return -EINVAL;
1361
1362 chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1);
1363
1364 for (i = 0; i < len; i++)
1365 id[i] = chip->read_byte(mtd);
1366
1367 return 0;
1368}
1369EXPORT_SYMBOL_GPL(nand_readid_op);
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382int nand_status_op(struct nand_chip *chip, u8 *status)
1383{
1384 struct mtd_info *mtd = nand_to_mtd(chip);
1385
1386 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1387 if (status)
1388 *status = chip->read_byte(mtd);
1389
1390 return 0;
1391}
1392EXPORT_SYMBOL_GPL(nand_status_op);
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405int nand_exit_status_op(struct nand_chip *chip)
1406{
1407 struct mtd_info *mtd = nand_to_mtd(chip);
1408
1409 chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1);
1410
1411 return 0;
1412}
1413EXPORT_SYMBOL_GPL(nand_exit_status_op);
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
1427{
1428 struct mtd_info *mtd = nand_to_mtd(chip);
1429 unsigned int page = eraseblock <<
1430 (chip->phys_erase_shift - chip->page_shift);
1431 int status;
1432
1433 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1434 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1435
1436 status = chip->waitfunc(mtd, chip);
1437 if (status < 0)
1438 return status;
1439
1440 if (status & NAND_STATUS_FAIL)
1441 return -EIO;
1442
1443 return 0;
1444}
1445EXPORT_SYMBOL_GPL(nand_erase_op);
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459static int nand_set_features_op(struct nand_chip *chip, u8 feature,
1460 const void *data)
1461{
1462 struct mtd_info *mtd = nand_to_mtd(chip);
1463 const u8 *params = data;
1464 int i, status;
1465
1466 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1);
1467 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1468 chip->write_byte(mtd, params[i]);
1469
1470 status = chip->waitfunc(mtd, chip);
1471 if (status & NAND_STATUS_FAIL)
1472 return -EIO;
1473
1474 return 0;
1475}
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489static int nand_get_features_op(struct nand_chip *chip, u8 feature,
1490 void *data)
1491{
1492 struct mtd_info *mtd = nand_to_mtd(chip);
1493 u8 *params = data;
1494 int i;
1495
1496 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1);
1497 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1498 params[i] = chip->read_byte(mtd);
1499
1500 return 0;
1501}
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513int nand_reset_op(struct nand_chip *chip)
1514{
1515 struct mtd_info *mtd = nand_to_mtd(chip);
1516
1517 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1518
1519 return 0;
1520}
1521EXPORT_SYMBOL_GPL(nand_reset_op);
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1537 bool force_8bit)
1538{
1539 struct mtd_info *mtd = nand_to_mtd(chip);
1540
1541 if (!len || !buf)
1542 return -EINVAL;
1543
1544 if (force_8bit) {
1545 u8 *p = buf;
1546 unsigned int i;
1547
1548 for (i = 0; i < len; i++)
1549 p[i] = chip->read_byte(mtd);
1550 } else {
1551 chip->read_buf(mtd, buf, len);
1552 }
1553
1554 return 0;
1555}
1556EXPORT_SYMBOL_GPL(nand_read_data_op);
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571int nand_write_data_op(struct nand_chip *chip, const void *buf,
1572 unsigned int len, bool force_8bit)
1573{
1574 struct mtd_info *mtd = nand_to_mtd(chip);
1575
1576 if (!len || !buf)
1577 return -EINVAL;
1578
1579 if (force_8bit) {
1580 const u8 *p = buf;
1581 unsigned int i;
1582
1583 for (i = 0; i < len; i++)
1584 chip->write_byte(mtd, p[i]);
1585 } else {
1586 chip->write_buf(mtd, buf, len);
1587 }
1588
1589 return 0;
1590}
1591EXPORT_SYMBOL_GPL(nand_write_data_op);
1592
1593
1594
1595
1596
1597
1598
1599
1600int nand_reset(struct nand_chip *chip, int chipnr)
1601{
1602 struct mtd_info *mtd = nand_to_mtd(chip);
1603 int ret;
1604
1605 ret = nand_reset_data_interface(chip, chipnr);
1606 if (ret)
1607 return ret;
1608
1609
1610
1611
1612
1613 chip->select_chip(mtd, chipnr);
1614 ret = nand_reset_op(chip);
1615 chip->select_chip(mtd, -1);
1616 if (ret)
1617 return ret;
1618
1619 chip->select_chip(mtd, chipnr);
1620 ret = nand_setup_data_interface(chip, chipnr);
1621 chip->select_chip(mtd, -1);
1622 if (ret)
1623 return ret;
1624
1625 return 0;
1626}
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1648{
1649 const unsigned char *bitmap = buf;
1650 int bitflips = 0;
1651 int weight;
1652
1653 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1654 len--, bitmap++) {
1655 weight = hweight8(*bitmap);
1656 bitflips += BITS_PER_BYTE - weight;
1657 if (unlikely(bitflips > bitflips_threshold))
1658 return -EBADMSG;
1659 }
1660
1661 for (; len >= 4; len -= 4, bitmap += 4) {
1662 weight = hweight32(*((u32 *)bitmap));
1663 bitflips += 32 - weight;
1664 if (unlikely(bitflips > bitflips_threshold))
1665 return -EBADMSG;
1666 }
1667
1668 for (; len > 0; len--, bitmap++) {
1669 weight = hweight8(*bitmap);
1670 bitflips += BITS_PER_BYTE - weight;
1671 if (unlikely(bitflips > bitflips_threshold))
1672 return -EBADMSG;
1673 }
1674
1675 return bitflips;
1676}
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717int nand_check_erased_ecc_chunk(void *data, int datalen,
1718 void *ecc, int ecclen,
1719 void *extraoob, int extraooblen,
1720 int bitflips_threshold)
1721{
1722 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1723
1724 data_bitflips = nand_check_erased_buf(data, datalen,
1725 bitflips_threshold);
1726 if (data_bitflips < 0)
1727 return data_bitflips;
1728
1729 bitflips_threshold -= data_bitflips;
1730
1731 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1732 if (ecc_bitflips < 0)
1733 return ecc_bitflips;
1734
1735 bitflips_threshold -= ecc_bitflips;
1736
1737 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1738 bitflips_threshold);
1739 if (extraoob_bitflips < 0)
1740 return extraoob_bitflips;
1741
1742 if (data_bitflips)
1743 memset(data, 0xff, datalen);
1744
1745 if (ecc_bitflips)
1746 memset(ecc, 0xff, ecclen);
1747
1748 if (extraoob_bitflips)
1749 memset(extraoob, 0xff, extraooblen);
1750
1751 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1752}
1753EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1766 uint8_t *buf, int oob_required, int page)
1767{
1768 int ret;
1769
1770 ret = nand_read_data_op(chip, buf, mtd->writesize, false);
1771 if (ret)
1772 return ret;
1773
1774 if (oob_required) {
1775 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
1776 false);
1777 if (ret)
1778 return ret;
1779 }
1780
1781 return 0;
1782}
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1795 struct nand_chip *chip, uint8_t *buf,
1796 int oob_required, int page)
1797{
1798 int eccsize = chip->ecc.size;
1799 int eccbytes = chip->ecc.bytes;
1800 uint8_t *oob = chip->oob_poi;
1801 int steps, size, ret;
1802
1803 for (steps = chip->ecc.steps; steps > 0; steps--) {
1804 ret = nand_read_data_op(chip, buf, eccsize, false);
1805 if (ret)
1806 return ret;
1807
1808 buf += eccsize;
1809
1810 if (chip->ecc.prepad) {
1811 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
1812 false);
1813 if (ret)
1814 return ret;
1815
1816 oob += chip->ecc.prepad;
1817 }
1818
1819 ret = nand_read_data_op(chip, oob, eccbytes, false);
1820 if (ret)
1821 return ret;
1822
1823 oob += eccbytes;
1824
1825 if (chip->ecc.postpad) {
1826 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
1827 false);
1828 if (ret)
1829 return ret;
1830
1831 oob += chip->ecc.postpad;
1832 }
1833 }
1834
1835 size = mtd->oobsize - (oob - chip->oob_poi);
1836 if (size) {
1837 ret = nand_read_data_op(chip, oob, size, false);
1838 if (ret)
1839 return ret;
1840 }
1841
1842 return 0;
1843}
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1854 uint8_t *buf, int oob_required, int page)
1855{
1856 int i, eccsize = chip->ecc.size;
1857 int eccbytes = chip->ecc.bytes;
1858 int eccsteps = chip->ecc.steps;
1859 uint8_t *p = buf;
1860 uint8_t *ecc_calc = chip->buffers->ecccalc;
1861 uint8_t *ecc_code = chip->buffers->ecccode;
1862 uint32_t *eccpos = chip->ecc.layout->eccpos;
1863 unsigned int max_bitflips = 0;
1864
1865 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1866
1867 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1868 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1869
1870 for (i = 0; i < chip->ecc.total; i++)
1871 ecc_code[i] = chip->oob_poi[eccpos[i]];
1872
1873 eccsteps = chip->ecc.steps;
1874 p = buf;
1875
1876 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1877 int stat;
1878
1879 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1880 if (stat < 0) {
1881 mtd->ecc_stats.failed++;
1882 } else {
1883 mtd->ecc_stats.corrected += stat;
1884 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1885 }
1886 }
1887 return max_bitflips;
1888}
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1900 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1901 int page)
1902{
1903 int start_step, end_step, num_steps;
1904 uint32_t *eccpos = chip->ecc.layout->eccpos;
1905 uint8_t *p;
1906 int data_col_addr, i, gaps = 0;
1907 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1908 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1909 int index;
1910 unsigned int max_bitflips = 0;
1911 int ret;
1912
1913
1914 start_step = data_offs / chip->ecc.size;
1915 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1916 num_steps = end_step - start_step + 1;
1917 index = start_step * chip->ecc.bytes;
1918
1919
1920 datafrag_len = num_steps * chip->ecc.size;
1921 eccfrag_len = num_steps * chip->ecc.bytes;
1922
1923 data_col_addr = start_step * chip->ecc.size;
1924
1925 if (data_col_addr != 0)
1926 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1927
1928 p = bufpoi + data_col_addr;
1929 ret = nand_read_data_op(chip, p, datafrag_len, false);
1930 if (ret)
1931 return ret;
1932
1933
1934 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1935 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1936
1937
1938
1939
1940
1941 for (i = 0; i < eccfrag_len - 1; i++) {
1942 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1943 gaps = 1;
1944 break;
1945 }
1946 }
1947 if (gaps) {
1948 ret = nand_change_read_column_op(chip, mtd->writesize,
1949 chip->oob_poi, mtd->oobsize,
1950 false);
1951 if (ret)
1952 return ret;
1953 } else {
1954
1955
1956
1957
1958 aligned_pos = eccpos[index] & ~(busw - 1);
1959 aligned_len = eccfrag_len;
1960 if (eccpos[index] & (busw - 1))
1961 aligned_len++;
1962 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1963 aligned_len++;
1964
1965 ret = nand_change_read_column_op(chip,
1966 mtd->writesize + aligned_pos,
1967 &chip->oob_poi[aligned_pos],
1968 aligned_len, false);
1969 if (ret)
1970 return ret;
1971 }
1972
1973 for (i = 0; i < eccfrag_len; i++)
1974 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1975
1976 p = bufpoi + data_col_addr;
1977 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1978 int stat;
1979
1980 stat = chip->ecc.correct(mtd, p,
1981 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1982 if (stat == -EBADMSG &&
1983 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1984
1985 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1986 &chip->buffers->ecccode[i],
1987 chip->ecc.bytes,
1988 NULL, 0,
1989 chip->ecc.strength);
1990 }
1991
1992 if (stat < 0) {
1993 mtd->ecc_stats.failed++;
1994 } else {
1995 mtd->ecc_stats.corrected += stat;
1996 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1997 }
1998 }
1999 return max_bitflips;
2000}
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2013 uint8_t *buf, int oob_required, int page)
2014{
2015 int i, eccsize = chip->ecc.size;
2016 int eccbytes = chip->ecc.bytes;
2017 int eccsteps = chip->ecc.steps;
2018 uint8_t *p = buf;
2019 uint8_t *ecc_calc = chip->buffers->ecccalc;
2020 uint8_t *ecc_code = chip->buffers->ecccode;
2021 uint32_t *eccpos = chip->ecc.layout->eccpos;
2022 unsigned int max_bitflips = 0;
2023 int ret;
2024
2025 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2026 chip->ecc.hwctl(mtd, NAND_ECC_READ);
2027
2028 ret = nand_read_data_op(chip, p, eccsize, false);
2029 if (ret)
2030 return ret;
2031
2032 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2033 }
2034
2035 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
2036 if (ret)
2037 return ret;
2038
2039 for (i = 0; i < chip->ecc.total; i++)
2040 ecc_code[i] = chip->oob_poi[eccpos[i]];
2041
2042 eccsteps = chip->ecc.steps;
2043 p = buf;
2044
2045 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2046 int stat;
2047
2048 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
2049 if (stat == -EBADMSG &&
2050 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2051
2052 stat = nand_check_erased_ecc_chunk(p, eccsize,
2053 &ecc_code[i], eccbytes,
2054 NULL, 0,
2055 chip->ecc.strength);
2056 }
2057
2058 if (stat < 0) {
2059 mtd->ecc_stats.failed++;
2060 } else {
2061 mtd->ecc_stats.corrected += stat;
2062 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2063 }
2064 }
2065 return max_bitflips;
2066}
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
2083 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
2084{
2085 int i, eccsize = chip->ecc.size;
2086 int eccbytes = chip->ecc.bytes;
2087 int eccsteps = chip->ecc.steps;
2088 uint8_t *p = buf;
2089 uint8_t *ecc_code = chip->buffers->ecccode;
2090 uint32_t *eccpos = chip->ecc.layout->eccpos;
2091 uint8_t *ecc_calc = chip->buffers->ecccalc;
2092 unsigned int max_bitflips = 0;
2093 int ret;
2094
2095
2096 ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
2097 if (ret)
2098 return ret;
2099
2100 ret = nand_read_page_op(chip, page, 0, NULL, 0);
2101 if (ret)
2102 return ret;
2103
2104 for (i = 0; i < chip->ecc.total; i++)
2105 ecc_code[i] = chip->oob_poi[eccpos[i]];
2106
2107 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2108 int stat;
2109
2110 chip->ecc.hwctl(mtd, NAND_ECC_READ);
2111
2112 ret = nand_read_data_op(chip, p, eccsize, false);
2113 if (ret)
2114 return ret;
2115
2116 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2117
2118 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
2119 if (stat == -EBADMSG &&
2120 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2121
2122 stat = nand_check_erased_ecc_chunk(p, eccsize,
2123 &ecc_code[i], eccbytes,
2124 NULL, 0,
2125 chip->ecc.strength);
2126 }
2127
2128 if (stat < 0) {
2129 mtd->ecc_stats.failed++;
2130 } else {
2131 mtd->ecc_stats.corrected += stat;
2132 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2133 }
2134 }
2135 return max_bitflips;
2136}
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2150 uint8_t *buf, int oob_required, int page)
2151{
2152 int ret, i, eccsize = chip->ecc.size;
2153 int eccbytes = chip->ecc.bytes;
2154 int eccsteps = chip->ecc.steps;
2155 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
2156 uint8_t *p = buf;
2157 uint8_t *oob = chip->oob_poi;
2158 unsigned int max_bitflips = 0;
2159
2160 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2161 int stat;
2162
2163 chip->ecc.hwctl(mtd, NAND_ECC_READ);
2164
2165 ret = nand_read_data_op(chip, p, eccsize, false);
2166 if (ret)
2167 return ret;
2168
2169 if (chip->ecc.prepad) {
2170 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
2171 false);
2172 if (ret)
2173 return ret;
2174
2175 oob += chip->ecc.prepad;
2176 }
2177
2178 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
2179
2180 ret = nand_read_data_op(chip, oob, eccbytes, false);
2181 if (ret)
2182 return ret;
2183
2184 stat = chip->ecc.correct(mtd, p, oob, NULL);
2185
2186 oob += eccbytes;
2187
2188 if (chip->ecc.postpad) {
2189 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
2190 false);
2191 if (ret)
2192 return ret;
2193
2194 oob += chip->ecc.postpad;
2195 }
2196
2197 if (stat == -EBADMSG &&
2198 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2199
2200 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
2201 oob - eccpadbytes,
2202 eccpadbytes,
2203 NULL, 0,
2204 chip->ecc.strength);
2205 }
2206
2207 if (stat < 0) {
2208 mtd->ecc_stats.failed++;
2209 } else {
2210 mtd->ecc_stats.corrected += stat;
2211 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2212 }
2213 }
2214
2215
2216 i = mtd->oobsize - (oob - chip->oob_poi);
2217 if (i) {
2218 ret = nand_read_data_op(chip, oob, i, false);
2219 if (ret)
2220 return ret;
2221 }
2222
2223 return max_bitflips;
2224}
2225
2226
2227
2228
2229
2230
2231
2232
2233static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
2234 struct mtd_oob_ops *ops, size_t len)
2235{
2236 switch (ops->mode) {
2237
2238 case MTD_OPS_PLACE_OOB:
2239 case MTD_OPS_RAW:
2240 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
2241 return oob + len;
2242
2243 case MTD_OPS_AUTO_OOB: {
2244 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2245 uint32_t boffs = 0, roffs = ops->ooboffs;
2246 size_t bytes = 0;
2247
2248 for (; free->length && len; free++, len -= bytes) {
2249
2250 if (unlikely(roffs)) {
2251 if (roffs >= free->length) {
2252 roffs -= free->length;
2253 continue;
2254 }
2255 boffs = free->offset + roffs;
2256 bytes = min_t(size_t, len,
2257 (free->length - roffs));
2258 roffs = 0;
2259 } else {
2260 bytes = min_t(size_t, len, free->length);
2261 boffs = free->offset;
2262 }
2263 memcpy(oob, chip->oob_poi + boffs, bytes);
2264 oob += bytes;
2265 }
2266 return oob;
2267 }
2268 default:
2269 BUG();
2270 }
2271 return NULL;
2272}
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
2284{
2285 struct nand_chip *chip = mtd_to_nand(mtd);
2286
2287 pr_debug("setting READ RETRY mode %d\n", retry_mode);
2288
2289 if (retry_mode >= chip->read_retries)
2290 return -EINVAL;
2291
2292 if (!chip->setup_read_retry)
2293 return -EOPNOTSUPP;
2294
2295 return chip->setup_read_retry(mtd, retry_mode);
2296}
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
2307 struct mtd_oob_ops *ops)
2308{
2309 int chipnr, page, realpage, col, bytes, aligned, oob_required;
2310 struct nand_chip *chip = mtd_to_nand(mtd);
2311 int ret = 0;
2312 uint32_t readlen = ops->len;
2313 uint32_t oobreadlen = ops->ooblen;
2314 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
2315
2316 uint8_t *bufpoi, *oob, *buf;
2317 int use_bufpoi;
2318 unsigned int max_bitflips = 0;
2319 int retry_mode = 0;
2320 bool ecc_fail = false;
2321
2322 chipnr = (int)(from >> chip->chip_shift);
2323 chip->select_chip(mtd, chipnr);
2324
2325 realpage = (int)(from >> chip->page_shift);
2326 page = realpage & chip->pagemask;
2327
2328 col = (int)(from & (mtd->writesize - 1));
2329
2330 buf = ops->datbuf;
2331 oob = ops->oobbuf;
2332 oob_required = oob ? 1 : 0;
2333
2334 while (1) {
2335 unsigned int ecc_failures = mtd->ecc_stats.failed;
2336
2337 WATCHDOG_RESET();
2338 bytes = min(mtd->writesize - col, readlen);
2339 aligned = (bytes == mtd->writesize);
2340
2341 if (!aligned)
2342 use_bufpoi = 1;
2343 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2344 use_bufpoi = !IS_ALIGNED((unsigned long)buf,
2345 chip->buf_align);
2346 else
2347 use_bufpoi = 0;
2348
2349
2350 if (realpage != chip->pagebuf || oob) {
2351 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
2352
2353 if (use_bufpoi && aligned)
2354 pr_debug("%s: using read bounce buffer for buf@%p\n",
2355 __func__, buf);
2356
2357read_retry:
2358 if (nand_standard_page_accessors(&chip->ecc)) {
2359 ret = nand_read_page_op(chip, page, 0, NULL, 0);
2360 if (ret)
2361 break;
2362 }
2363
2364
2365
2366
2367
2368 if (unlikely(ops->mode == MTD_OPS_RAW))
2369 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
2370 oob_required,
2371 page);
2372 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
2373 !oob)
2374 ret = chip->ecc.read_subpage(mtd, chip,
2375 col, bytes, bufpoi,
2376 page);
2377 else
2378 ret = chip->ecc.read_page(mtd, chip, bufpoi,
2379 oob_required, page);
2380 if (ret < 0) {
2381 if (use_bufpoi)
2382
2383 chip->pagebuf = -1;
2384 break;
2385 }
2386
2387 max_bitflips = max_t(unsigned int, max_bitflips, ret);
2388
2389
2390 if (use_bufpoi) {
2391 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
2392 !(mtd->ecc_stats.failed - ecc_failures) &&
2393 (ops->mode != MTD_OPS_RAW)) {
2394 chip->pagebuf = realpage;
2395 chip->pagebuf_bitflips = ret;
2396 } else {
2397
2398 chip->pagebuf = -1;
2399 }
2400 memcpy(buf, chip->buffers->databuf + col, bytes);
2401 }
2402
2403 if (unlikely(oob)) {
2404 int toread = min(oobreadlen, max_oobsize);
2405
2406 if (toread) {
2407 oob = nand_transfer_oob(chip,
2408 oob, ops, toread);
2409 oobreadlen -= toread;
2410 }
2411 }
2412
2413 if (chip->options & NAND_NEED_READRDY) {
2414
2415 if (!chip->dev_ready)
2416 udelay(chip->chip_delay);
2417 else
2418 nand_wait_ready(mtd);
2419 }
2420
2421 if (mtd->ecc_stats.failed - ecc_failures) {
2422 if (retry_mode + 1 < chip->read_retries) {
2423 retry_mode++;
2424 ret = nand_setup_read_retry(mtd,
2425 retry_mode);
2426 if (ret < 0)
2427 break;
2428
2429
2430 mtd->ecc_stats.failed = ecc_failures;
2431 goto read_retry;
2432 } else {
2433
2434 ecc_fail = true;
2435 }
2436 }
2437
2438 buf += bytes;
2439 } else {
2440 memcpy(buf, chip->buffers->databuf + col, bytes);
2441 buf += bytes;
2442 max_bitflips = max_t(unsigned int, max_bitflips,
2443 chip->pagebuf_bitflips);
2444 }
2445
2446 readlen -= bytes;
2447
2448
2449 if (retry_mode) {
2450 ret = nand_setup_read_retry(mtd, 0);
2451 if (ret < 0)
2452 break;
2453 retry_mode = 0;
2454 }
2455
2456 if (!readlen)
2457 break;
2458
2459
2460 col = 0;
2461
2462 realpage++;
2463
2464 page = realpage & chip->pagemask;
2465
2466 if (!page) {
2467 chipnr++;
2468 chip->select_chip(mtd, -1);
2469 chip->select_chip(mtd, chipnr);
2470 }
2471 }
2472 chip->select_chip(mtd, -1);
2473
2474 ops->retlen = ops->len - (size_t) readlen;
2475 if (oob)
2476 ops->oobretlen = ops->ooblen - oobreadlen;
2477
2478 if (ret < 0)
2479 return ret;
2480
2481 if (ecc_fail)
2482 return -EBADMSG;
2483
2484 return max_bitflips;
2485}
2486
2487
2488
2489
2490
2491
2492
2493static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
2494 int page)
2495{
2496 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
2497}
2498
2499
2500
2501
2502
2503
2504
2505
2506static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2507 int page)
2508{
2509 int length = mtd->oobsize;
2510 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2511 int eccsize = chip->ecc.size;
2512 uint8_t *bufpoi = chip->oob_poi;
2513 int i, toread, sndrnd = 0, pos, ret;
2514
2515 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
2516 if (ret)
2517 return ret;
2518
2519 for (i = 0; i < chip->ecc.steps; i++) {
2520 if (sndrnd) {
2521 int ret;
2522
2523 pos = eccsize + i * (eccsize + chunk);
2524 if (mtd->writesize > 512)
2525 ret = nand_change_read_column_op(chip, pos,
2526 NULL, 0,
2527 false);
2528 else
2529 ret = nand_read_page_op(chip, page, pos, NULL,
2530 0);
2531
2532 if (ret)
2533 return ret;
2534 } else
2535 sndrnd = 1;
2536 toread = min_t(int, length, chunk);
2537
2538 ret = nand_read_data_op(chip, bufpoi, toread, false);
2539 if (ret)
2540 return ret;
2541
2542 bufpoi += toread;
2543 length -= toread;
2544 }
2545 if (length > 0) {
2546 ret = nand_read_data_op(chip, bufpoi, length, false);
2547 if (ret)
2548 return ret;
2549 }
2550
2551 return 0;
2552}
2553
2554
2555
2556
2557
2558
2559
2560static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
2561 int page)
2562{
2563 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
2564 mtd->oobsize);
2565}
2566
2567
2568
2569
2570
2571
2572
2573
2574static int nand_write_oob_syndrome(struct mtd_info *mtd,
2575 struct nand_chip *chip, int page)
2576{
2577 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2578 int eccsize = chip->ecc.size, length = mtd->oobsize;
2579 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
2580 const uint8_t *bufpoi = chip->oob_poi;
2581
2582
2583
2584
2585
2586
2587 if (!chip->ecc.prepad && !chip->ecc.postpad) {
2588 pos = steps * (eccsize + chunk);
2589 steps = 0;
2590 } else
2591 pos = eccsize;
2592
2593 ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
2594 if (ret)
2595 return ret;
2596
2597 for (i = 0; i < steps; i++) {
2598 if (sndcmd) {
2599 if (mtd->writesize <= 512) {
2600 uint32_t fill = 0xFFFFFFFF;
2601
2602 len = eccsize;
2603 while (len > 0) {
2604 int num = min_t(int, len, 4);
2605
2606 ret = nand_write_data_op(chip, &fill,
2607 num, false);
2608 if (ret)
2609 return ret;
2610
2611 len -= num;
2612 }
2613 } else {
2614 pos = eccsize + i * (eccsize + chunk);
2615 ret = nand_change_write_column_op(chip, pos,
2616 NULL, 0,
2617 false);
2618 if (ret)
2619 return ret;
2620 }
2621 } else
2622 sndcmd = 1;
2623 len = min_t(int, length, chunk);
2624
2625 ret = nand_write_data_op(chip, bufpoi, len, false);
2626 if (ret)
2627 return ret;
2628
2629 bufpoi += len;
2630 length -= len;
2631 }
2632 if (length > 0) {
2633 ret = nand_write_data_op(chip, bufpoi, length, false);
2634 if (ret)
2635 return ret;
2636 }
2637
2638 return nand_prog_page_end_op(chip);
2639}
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2650 struct mtd_oob_ops *ops)
2651{
2652 int page, realpage, chipnr;
2653 struct nand_chip *chip = mtd_to_nand(mtd);
2654 struct mtd_ecc_stats stats;
2655 int readlen = ops->ooblen;
2656 int len;
2657 uint8_t *buf = ops->oobbuf;
2658 int ret = 0;
2659
2660 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2661 __func__, (unsigned long long)from, readlen);
2662
2663 stats = mtd->ecc_stats;
2664
2665 len = mtd_oobavail(mtd, ops);
2666
2667 if (unlikely(ops->ooboffs >= len)) {
2668 pr_debug("%s: attempt to start read outside oob\n",
2669 __func__);
2670 return -EINVAL;
2671 }
2672
2673
2674 if (unlikely(from >= mtd->size ||
2675 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2676 (from >> chip->page_shift)) * len)) {
2677 pr_debug("%s: attempt to read beyond end of device\n",
2678 __func__);
2679 return -EINVAL;
2680 }
2681
2682 chipnr = (int)(from >> chip->chip_shift);
2683 chip->select_chip(mtd, chipnr);
2684
2685
2686 realpage = (int)(from >> chip->page_shift);
2687 page = realpage & chip->pagemask;
2688
2689 while (1) {
2690 WATCHDOG_RESET();
2691
2692 if (ops->mode == MTD_OPS_RAW)
2693 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2694 else
2695 ret = chip->ecc.read_oob(mtd, chip, page);
2696
2697 if (ret < 0)
2698 break;
2699
2700 len = min(len, readlen);
2701 buf = nand_transfer_oob(chip, buf, ops, len);
2702
2703 if (chip->options & NAND_NEED_READRDY) {
2704
2705 if (!chip->dev_ready)
2706 udelay(chip->chip_delay);
2707 else
2708 nand_wait_ready(mtd);
2709 }
2710
2711 readlen -= len;
2712 if (!readlen)
2713 break;
2714
2715
2716 realpage++;
2717
2718 page = realpage & chip->pagemask;
2719
2720 if (!page) {
2721 chipnr++;
2722 chip->select_chip(mtd, -1);
2723 chip->select_chip(mtd, chipnr);
2724 }
2725 }
2726 chip->select_chip(mtd, -1);
2727
2728 ops->oobretlen = ops->ooblen - readlen;
2729
2730 if (ret < 0)
2731 return ret;
2732
2733 if (mtd->ecc_stats.failed - stats.failed)
2734 return -EBADMSG;
2735
2736 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2737}
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2748 struct mtd_oob_ops *ops)
2749{
2750 int ret = -ENOTSUPP;
2751
2752 ops->retlen = 0;
2753
2754
2755 if (ops->datbuf && (from + ops->len) > mtd->size) {
2756 pr_debug("%s: attempt to read beyond end of device\n",
2757 __func__);
2758 return -EINVAL;
2759 }
2760
2761 nand_get_device(mtd, FL_READING);
2762
2763 switch (ops->mode) {
2764 case MTD_OPS_PLACE_OOB:
2765 case MTD_OPS_AUTO_OOB:
2766 case MTD_OPS_RAW:
2767 break;
2768
2769 default:
2770 goto out;
2771 }
2772
2773 if (!ops->datbuf)
2774 ret = nand_do_read_oob(mtd, from, ops);
2775 else
2776 ret = nand_do_read_ops(mtd, from, ops);
2777
2778out:
2779 nand_release_device(mtd);
2780 return ret;
2781}
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2795 const uint8_t *buf, int oob_required, int page)
2796{
2797 int ret;
2798
2799 ret = nand_write_data_op(chip, buf, mtd->writesize, false);
2800 if (ret)
2801 return ret;
2802
2803 if (oob_required) {
2804 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
2805 false);
2806 if (ret)
2807 return ret;
2808 }
2809
2810 return 0;
2811}
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2824 struct nand_chip *chip,
2825 const uint8_t *buf, int oob_required,
2826 int page)
2827{
2828 int eccsize = chip->ecc.size;
2829 int eccbytes = chip->ecc.bytes;
2830 uint8_t *oob = chip->oob_poi;
2831 int steps, size, ret;
2832
2833 for (steps = chip->ecc.steps; steps > 0; steps--) {
2834 ret = nand_write_data_op(chip, buf, eccsize, false);
2835 if (ret)
2836 return ret;
2837
2838 buf += eccsize;
2839
2840 if (chip->ecc.prepad) {
2841 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
2842 false);
2843 if (ret)
2844 return ret;
2845
2846 oob += chip->ecc.prepad;
2847 }
2848
2849 ret = nand_write_data_op(chip, oob, eccbytes, false);
2850 if (ret)
2851 return ret;
2852
2853 oob += eccbytes;
2854
2855 if (chip->ecc.postpad) {
2856 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
2857 false);
2858 if (ret)
2859 return ret;
2860
2861 oob += chip->ecc.postpad;
2862 }
2863 }
2864
2865 size = mtd->oobsize - (oob - chip->oob_poi);
2866 if (size) {
2867 ret = nand_write_data_op(chip, oob, size, false);
2868 if (ret)
2869 return ret;
2870 }
2871
2872 return 0;
2873}
2874
2875
2876
2877
2878
2879
2880
2881
2882static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2883 const uint8_t *buf, int oob_required,
2884 int page)
2885{
2886 int i, eccsize = chip->ecc.size;
2887 int eccbytes = chip->ecc.bytes;
2888 int eccsteps = chip->ecc.steps;
2889 uint8_t *ecc_calc = chip->buffers->ecccalc;
2890 const uint8_t *p = buf;
2891 uint32_t *eccpos = chip->ecc.layout->eccpos;
2892
2893
2894 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2895 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2896
2897 for (i = 0; i < chip->ecc.total; i++)
2898 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2899
2900 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
2901}
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2912 const uint8_t *buf, int oob_required,
2913 int page)
2914{
2915 int i, eccsize = chip->ecc.size;
2916 int eccbytes = chip->ecc.bytes;
2917 int eccsteps = chip->ecc.steps;
2918 uint8_t *ecc_calc = chip->buffers->ecccalc;
2919 const uint8_t *p = buf;
2920 uint32_t *eccpos = chip->ecc.layout->eccpos;
2921 int ret;
2922
2923 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2924 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2925
2926 ret = nand_write_data_op(chip, p, eccsize, false);
2927 if (ret)
2928 return ret;
2929
2930 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2931 }
2932
2933 for (i = 0; i < chip->ecc.total; i++)
2934 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2935
2936 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
2937 if (ret)
2938 return ret;
2939
2940 return 0;
2941}
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2955 struct nand_chip *chip, uint32_t offset,
2956 uint32_t data_len, const uint8_t *buf,
2957 int oob_required, int page)
2958{
2959 uint8_t *oob_buf = chip->oob_poi;
2960 uint8_t *ecc_calc = chip->buffers->ecccalc;
2961 int ecc_size = chip->ecc.size;
2962 int ecc_bytes = chip->ecc.bytes;
2963 int ecc_steps = chip->ecc.steps;
2964 uint32_t *eccpos = chip->ecc.layout->eccpos;
2965 uint32_t start_step = offset / ecc_size;
2966 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2967 int oob_bytes = mtd->oobsize / ecc_steps;
2968 int step, i;
2969 int ret;
2970
2971 for (step = 0; step < ecc_steps; step++) {
2972
2973 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2974
2975
2976 ret = nand_write_data_op(chip, buf, ecc_size, false);
2977 if (ret)
2978 return ret;
2979
2980
2981 if ((step < start_step) || (step > end_step))
2982 memset(ecc_calc, 0xff, ecc_bytes);
2983 else
2984 chip->ecc.calculate(mtd, buf, ecc_calc);
2985
2986
2987
2988 if (!oob_required || (step < start_step) || (step > end_step))
2989 memset(oob_buf, 0xff, oob_bytes);
2990
2991 buf += ecc_size;
2992 ecc_calc += ecc_bytes;
2993 oob_buf += oob_bytes;
2994 }
2995
2996
2997
2998 ecc_calc = chip->buffers->ecccalc;
2999 for (i = 0; i < chip->ecc.total; i++)
3000 chip->oob_poi[eccpos[i]] = ecc_calc[i];
3001
3002
3003 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
3004 if (ret)
3005 return ret;
3006
3007 return 0;
3008}
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022static int nand_write_page_syndrome(struct mtd_info *mtd,
3023 struct nand_chip *chip,
3024 const uint8_t *buf, int oob_required,
3025 int page)
3026{
3027 int i, eccsize = chip->ecc.size;
3028 int eccbytes = chip->ecc.bytes;
3029 int eccsteps = chip->ecc.steps;
3030 const uint8_t *p = buf;
3031 uint8_t *oob = chip->oob_poi;
3032 int ret;
3033
3034 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3035 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
3036
3037 ret = nand_write_data_op(chip, p, eccsize, false);
3038 if (ret)
3039 return ret;
3040
3041 if (chip->ecc.prepad) {
3042 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
3043 false);
3044 if (ret)
3045 return ret;
3046
3047 oob += chip->ecc.prepad;
3048 }
3049
3050 chip->ecc.calculate(mtd, p, oob);
3051
3052 ret = nand_write_data_op(chip, oob, eccbytes, false);
3053 if (ret)
3054 return ret;
3055
3056 oob += eccbytes;
3057
3058 if (chip->ecc.postpad) {
3059 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
3060 false);
3061 if (ret)
3062 return ret;
3063
3064 oob += chip->ecc.postpad;
3065 }
3066 }
3067
3068
3069 i = mtd->oobsize - (oob - chip->oob_poi);
3070 if (i) {
3071 ret = nand_write_data_op(chip, oob, i, false);
3072 if (ret)
3073 return ret;
3074 }
3075
3076 return 0;
3077}
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
3091 uint32_t offset, int data_len, const uint8_t *buf,
3092 int oob_required, int page, int raw)
3093{
3094 int status, subpage;
3095
3096 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3097 chip->ecc.write_subpage)
3098 subpage = offset || (data_len < mtd->writesize);
3099 else
3100 subpage = 0;
3101
3102 if (nand_standard_page_accessors(&chip->ecc)) {
3103 status = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3104 if (status)
3105 return status;
3106 }
3107
3108 if (unlikely(raw))
3109 status = chip->ecc.write_page_raw(mtd, chip, buf,
3110 oob_required, page);
3111 else if (subpage)
3112 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
3113 buf, oob_required, page);
3114 else
3115 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
3116 page);
3117
3118 if (status < 0)
3119 return status;
3120
3121 if (nand_standard_page_accessors(&chip->ecc))
3122 return nand_prog_page_end_op(chip);
3123
3124 return 0;
3125}
3126
3127
3128
3129
3130
3131
3132
3133
3134static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
3135 struct mtd_oob_ops *ops)
3136{
3137 struct nand_chip *chip = mtd_to_nand(mtd);
3138
3139
3140
3141
3142
3143 memset(chip->oob_poi, 0xff, mtd->oobsize);
3144
3145 switch (ops->mode) {
3146
3147 case MTD_OPS_PLACE_OOB:
3148 case MTD_OPS_RAW:
3149 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
3150 return oob + len;
3151
3152 case MTD_OPS_AUTO_OOB: {
3153 struct nand_oobfree *free = chip->ecc.layout->oobfree;
3154 uint32_t boffs = 0, woffs = ops->ooboffs;
3155 size_t bytes = 0;
3156
3157 for (; free->length && len; free++, len -= bytes) {
3158
3159 if (unlikely(woffs)) {
3160 if (woffs >= free->length) {
3161 woffs -= free->length;
3162 continue;
3163 }
3164 boffs = free->offset + woffs;
3165 bytes = min_t(size_t, len,
3166 (free->length - woffs));
3167 woffs = 0;
3168 } else {
3169 bytes = min_t(size_t, len, free->length);
3170 boffs = free->offset;
3171 }
3172 memcpy(chip->oob_poi + boffs, oob, bytes);
3173 oob += bytes;
3174 }
3175 return oob;
3176 }
3177 default:
3178 BUG();
3179 }
3180 return NULL;
3181}
3182
3183#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
3194 struct mtd_oob_ops *ops)
3195{
3196 int chipnr, realpage, page, column;
3197 struct nand_chip *chip = mtd_to_nand(mtd);
3198 uint32_t writelen = ops->len;
3199
3200 uint32_t oobwritelen = ops->ooblen;
3201 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
3202
3203 uint8_t *oob = ops->oobbuf;
3204 uint8_t *buf = ops->datbuf;
3205 int ret;
3206 int oob_required = oob ? 1 : 0;
3207
3208 ops->retlen = 0;
3209 if (!writelen)
3210 return 0;
3211
3212
3213 if (NOTALIGNED(to)) {
3214 pr_notice("%s: attempt to write non page aligned data\n",
3215 __func__);
3216 return -EINVAL;
3217 }
3218
3219 column = to & (mtd->writesize - 1);
3220
3221 chipnr = (int)(to >> chip->chip_shift);
3222 chip->select_chip(mtd, chipnr);
3223
3224
3225 if (nand_check_wp(mtd)) {
3226 ret = -EIO;
3227 goto err_out;
3228 }
3229
3230 realpage = (int)(to >> chip->page_shift);
3231 page = realpage & chip->pagemask;
3232
3233
3234 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
3235 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
3236 chip->pagebuf = -1;
3237
3238
3239 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
3240 ret = -EINVAL;
3241 goto err_out;
3242 }
3243
3244 while (1) {
3245 int bytes = mtd->writesize;
3246 uint8_t *wbuf = buf;
3247 int use_bufpoi;
3248 int part_pagewr = (column || writelen < mtd->writesize);
3249
3250 if (part_pagewr)
3251 use_bufpoi = 1;
3252 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
3253 use_bufpoi = !IS_ALIGNED((unsigned long)buf,
3254 chip->buf_align);
3255 else
3256 use_bufpoi = 0;
3257
3258 WATCHDOG_RESET();
3259
3260 if (use_bufpoi) {
3261 pr_debug("%s: using write bounce buffer for buf@%p\n",
3262 __func__, buf);
3263 if (part_pagewr)
3264 bytes = min_t(int, bytes - column, writelen);
3265 chip->pagebuf = -1;
3266 memset(chip->buffers->databuf, 0xff, mtd->writesize);
3267 memcpy(&chip->buffers->databuf[column], buf, bytes);
3268 wbuf = chip->buffers->databuf;
3269 }
3270
3271 if (unlikely(oob)) {
3272 size_t len = min(oobwritelen, oobmaxlen);
3273 oob = nand_fill_oob(mtd, oob, len, ops);
3274 oobwritelen -= len;
3275 } else {
3276
3277 memset(chip->oob_poi, 0xff, mtd->oobsize);
3278 }
3279 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
3280 oob_required, page,
3281 (ops->mode == MTD_OPS_RAW));
3282 if (ret)
3283 break;
3284
3285 writelen -= bytes;
3286 if (!writelen)
3287 break;
3288
3289 column = 0;
3290 buf += bytes;
3291 realpage++;
3292
3293 page = realpage & chip->pagemask;
3294
3295 if (!page) {
3296 chipnr++;
3297 chip->select_chip(mtd, -1);
3298 chip->select_chip(mtd, chipnr);
3299 }
3300 }
3301
3302 ops->retlen = ops->len - writelen;
3303 if (unlikely(oob))
3304 ops->oobretlen = ops->ooblen;
3305
3306err_out:
3307 chip->select_chip(mtd, -1);
3308 return ret;
3309}
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
3323 size_t *retlen, const uint8_t *buf)
3324{
3325 struct nand_chip *chip = mtd_to_nand(mtd);
3326 struct mtd_oob_ops ops;
3327 int ret;
3328
3329
3330 panic_nand_wait(mtd, chip, 400);
3331
3332
3333 panic_nand_get_device(chip, mtd, FL_WRITING);
3334
3335 memset(&ops, 0, sizeof(ops));
3336 ops.len = len;
3337 ops.datbuf = (uint8_t *)buf;
3338 ops.mode = MTD_OPS_PLACE_OOB;
3339
3340 ret = nand_do_write_ops(mtd, to, &ops);
3341
3342 *retlen = ops.retlen;
3343 return ret;
3344}
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
3355 struct mtd_oob_ops *ops)
3356{
3357 int chipnr, page, status, len;
3358 struct nand_chip *chip = mtd_to_nand(mtd);
3359
3360 pr_debug("%s: to = 0x%08x, len = %i\n",
3361 __func__, (unsigned int)to, (int)ops->ooblen);
3362
3363 len = mtd_oobavail(mtd, ops);
3364
3365
3366 if ((ops->ooboffs + ops->ooblen) > len) {
3367 pr_debug("%s: attempt to write past end of page\n",
3368 __func__);
3369 return -EINVAL;
3370 }
3371
3372 if (unlikely(ops->ooboffs >= len)) {
3373 pr_debug("%s: attempt to start write outside oob\n",
3374 __func__);
3375 return -EINVAL;
3376 }
3377
3378
3379 if (unlikely(to >= mtd->size ||
3380 ops->ooboffs + ops->ooblen >
3381 ((mtd->size >> chip->page_shift) -
3382 (to >> chip->page_shift)) * len)) {
3383 pr_debug("%s: attempt to write beyond end of device\n",
3384 __func__);
3385 return -EINVAL;
3386 }
3387
3388 chipnr = (int)(to >> chip->chip_shift);
3389
3390
3391
3392
3393
3394
3395
3396 nand_reset(chip, chipnr);
3397
3398 chip->select_chip(mtd, chipnr);
3399
3400
3401 page = (int)(to >> chip->page_shift);
3402
3403
3404 if (nand_check_wp(mtd)) {
3405 chip->select_chip(mtd, -1);
3406 return -EROFS;
3407 }
3408
3409
3410 if (page == chip->pagebuf)
3411 chip->pagebuf = -1;
3412
3413 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
3414
3415 if (ops->mode == MTD_OPS_RAW)
3416 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
3417 else
3418 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
3419
3420 chip->select_chip(mtd, -1);
3421
3422 if (status)
3423 return status;
3424
3425 ops->oobretlen = ops->ooblen;
3426
3427 return 0;
3428}
3429
3430
3431
3432
3433
3434
3435
3436static int nand_write_oob(struct mtd_info *mtd, loff_t to,
3437 struct mtd_oob_ops *ops)
3438{
3439 int ret = -ENOTSUPP;
3440
3441 ops->retlen = 0;
3442
3443
3444 if (ops->datbuf && (to + ops->len) > mtd->size) {
3445 pr_debug("%s: attempt to write beyond end of device\n",
3446 __func__);
3447 return -EINVAL;
3448 }
3449
3450 nand_get_device(mtd, FL_WRITING);
3451
3452 switch (ops->mode) {
3453 case MTD_OPS_PLACE_OOB:
3454 case MTD_OPS_AUTO_OOB:
3455 case MTD_OPS_RAW:
3456 break;
3457
3458 default:
3459 goto out;
3460 }
3461
3462 if (!ops->datbuf)
3463 ret = nand_do_write_oob(mtd, to, ops);
3464 else
3465 ret = nand_do_write_ops(mtd, to, ops);
3466
3467out:
3468 nand_release_device(mtd);
3469 return ret;
3470}
3471
3472
3473
3474
3475
3476
3477
3478
3479static int single_erase(struct mtd_info *mtd, int page)
3480{
3481 struct nand_chip *chip = mtd_to_nand(mtd);
3482 unsigned int eraseblock;
3483
3484
3485 eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
3486
3487 return nand_erase_op(chip, eraseblock);
3488}
3489
3490
3491
3492
3493
3494
3495
3496
3497static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
3498{
3499 return nand_erase_nand(mtd, instr, 0);
3500}
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
3511 int allowbbt)
3512{
3513 int page, status, pages_per_block, ret, chipnr;
3514 struct nand_chip *chip = mtd_to_nand(mtd);
3515 loff_t len;
3516
3517 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3518 __func__, (unsigned long long)instr->addr,
3519 (unsigned long long)instr->len);
3520
3521 if (check_offs_len(mtd, instr->addr, instr->len))
3522 return -EINVAL;
3523
3524
3525 nand_get_device(mtd, FL_ERASING);
3526
3527
3528 page = (int)(instr->addr >> chip->page_shift);
3529 chipnr = (int)(instr->addr >> chip->chip_shift);
3530
3531
3532 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
3533
3534
3535 chip->select_chip(mtd, chipnr);
3536
3537
3538 if (nand_check_wp(mtd)) {
3539 pr_debug("%s: device is write protected!\n",
3540 __func__);
3541 instr->state = MTD_ERASE_FAILED;
3542 goto erase_exit;
3543 }
3544
3545
3546 len = instr->len;
3547
3548 instr->state = MTD_ERASING;
3549
3550 while (len) {
3551 WATCHDOG_RESET();
3552
3553
3554 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
3555 chip->page_shift, allowbbt)) {
3556 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3557 __func__, page);
3558 instr->state = MTD_ERASE_FAILED;
3559 instr->fail_addr =
3560 ((loff_t)page << chip->page_shift);
3561 goto erase_exit;
3562 }
3563
3564
3565
3566
3567
3568 if (page <= chip->pagebuf && chip->pagebuf <
3569 (page + pages_per_block))
3570 chip->pagebuf = -1;
3571
3572 status = chip->erase(mtd, page & chip->pagemask);
3573
3574
3575 if (status & NAND_STATUS_FAIL) {
3576 pr_debug("%s: failed erase, page 0x%08x\n",
3577 __func__, page);
3578 instr->state = MTD_ERASE_FAILED;
3579 instr->fail_addr =
3580 ((loff_t)page << chip->page_shift);
3581 goto erase_exit;
3582 }
3583
3584
3585 len -= (1ULL << chip->phys_erase_shift);
3586 page += pages_per_block;
3587
3588
3589 if (len && !(page & chip->pagemask)) {
3590 chipnr++;
3591 chip->select_chip(mtd, -1);
3592 chip->select_chip(mtd, chipnr);
3593 }
3594 }
3595 instr->state = MTD_ERASE_DONE;
3596
3597erase_exit:
3598
3599 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
3600
3601
3602 chip->select_chip(mtd, -1);
3603 nand_release_device(mtd);
3604
3605
3606 return ret;
3607}
3608
3609
3610
3611
3612
3613
3614
3615static void nand_sync(struct mtd_info *mtd)
3616{
3617 pr_debug("%s: called\n", __func__);
3618
3619
3620 nand_get_device(mtd, FL_SYNCING);
3621
3622 nand_release_device(mtd);
3623}
3624
3625
3626
3627
3628
3629
3630static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
3631{
3632 struct nand_chip *chip = mtd_to_nand(mtd);
3633 int chipnr = (int)(offs >> chip->chip_shift);
3634 int ret;
3635
3636
3637 nand_get_device(mtd, FL_READING);
3638 chip->select_chip(mtd, chipnr);
3639
3640 ret = nand_block_checkbad(mtd, offs, 0);
3641
3642 chip->select_chip(mtd, -1);
3643 nand_release_device(mtd);
3644
3645 return ret;
3646}
3647
3648
3649
3650
3651
3652
3653static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3654{
3655 int ret;
3656
3657 ret = nand_block_isbad(mtd, ofs);
3658 if (ret) {
3659
3660 if (ret > 0)
3661 return 0;
3662 return ret;
3663 }
3664
3665 return nand_block_markbad_lowlevel(mtd, ofs);
3666}
3667
3668
3669
3670
3671
3672
3673
3674
3675static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3676 int addr, uint8_t *subfeature_param)
3677{
3678#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3679 if (!chip->onfi_version ||
3680 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3681 & ONFI_OPT_CMD_SET_GET_FEATURES))
3682 return -ENOTSUPP;
3683#endif
3684
3685 return nand_set_features_op(chip, addr, subfeature_param);
3686}
3687
3688
3689
3690
3691
3692
3693
3694
3695static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3696 int addr, uint8_t *subfeature_param)
3697{
3698#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3699 if (!chip->onfi_version ||
3700 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3701 & ONFI_OPT_CMD_SET_GET_FEATURES))
3702 return -ENOTSUPP;
3703#endif
3704
3705 return nand_get_features_op(chip, addr, subfeature_param);
3706}
3707
3708
3709static void nand_set_defaults(struct nand_chip *chip, int busw)
3710{
3711
3712 if (!chip->chip_delay)
3713 chip->chip_delay = 20;
3714
3715
3716 if (chip->cmdfunc == NULL)
3717 chip->cmdfunc = nand_command;
3718
3719
3720 if (chip->waitfunc == NULL)
3721 chip->waitfunc = nand_wait;
3722
3723 if (!chip->select_chip)
3724 chip->select_chip = nand_select_chip;
3725
3726
3727 if (!chip->onfi_set_features)
3728 chip->onfi_set_features = nand_onfi_set_features;
3729 if (!chip->onfi_get_features)
3730 chip->onfi_get_features = nand_onfi_get_features;
3731
3732
3733 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3734 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3735 if (!chip->read_word)
3736 chip->read_word = nand_read_word;
3737 if (!chip->block_bad)
3738 chip->block_bad = nand_block_bad;
3739 if (!chip->block_markbad)
3740 chip->block_markbad = nand_default_block_markbad;
3741 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3742 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3743 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3744 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3745 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3746 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3747 if (!chip->scan_bbt)
3748 chip->scan_bbt = nand_default_bbt;
3749
3750 if (!chip->controller) {
3751 chip->controller = &chip->hwcontrol;
3752 spin_lock_init(&chip->controller->lock);
3753 init_waitqueue_head(&chip->controller->wq);
3754 }
3755
3756 if (!chip->buf_align)
3757 chip->buf_align = 1;
3758}
3759
3760
3761static void sanitize_string(char *s, size_t len)
3762{
3763 ssize_t i;
3764
3765
3766 s[len - 1] = 0;
3767
3768
3769 for (i = 0; i < len - 1; i++) {
3770 if (s[i] < ' ' || s[i] > 127)
3771 s[i] = '?';
3772 }
3773
3774
3775 strim(s);
3776}
3777
3778static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3779{
3780 int i;
3781 while (len--) {
3782 crc ^= *p++ << 8;
3783 for (i = 0; i < 8; i++)
3784 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3785 }
3786
3787 return crc;
3788}
3789
3790#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3791
3792static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3793 struct nand_chip *chip, struct nand_onfi_params *p)
3794{
3795 struct onfi_ext_param_page *ep;
3796 struct onfi_ext_section *s;
3797 struct onfi_ext_ecc_info *ecc;
3798 uint8_t *cursor;
3799 int ret;
3800 int len;
3801 int i;
3802
3803 len = le16_to_cpu(p->ext_param_page_length) * 16;
3804 ep = kmalloc(len, GFP_KERNEL);
3805 if (!ep)
3806 return -ENOMEM;
3807
3808
3809 ret = nand_read_param_page_op(chip, 0, NULL, 0);
3810 if (ret)
3811 goto ext_out;
3812
3813
3814 ret = nand_change_read_column_op(chip,
3815 sizeof(*p) * p->num_of_param_pages,
3816 ep, len, true);
3817 if (ret)
3818 goto ext_out;
3819
3820 ret = -EINVAL;
3821 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3822 != le16_to_cpu(ep->crc))) {
3823 pr_debug("fail in the CRC.\n");
3824 goto ext_out;
3825 }
3826
3827
3828
3829
3830
3831 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3832 pr_debug("The signature is invalid.\n");
3833 goto ext_out;
3834 }
3835
3836
3837 cursor = (uint8_t *)(ep + 1);
3838 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3839 s = ep->sections + i;
3840 if (s->type == ONFI_SECTION_TYPE_2)
3841 break;
3842 cursor += s->length * 16;
3843 }
3844 if (i == ONFI_EXT_SECTION_MAX) {
3845 pr_debug("We can not find the ECC section.\n");
3846 goto ext_out;
3847 }
3848
3849
3850 ecc = (struct onfi_ext_ecc_info *)cursor;
3851
3852 if (!ecc->codeword_size) {
3853 pr_debug("Invalid codeword size\n");
3854 goto ext_out;
3855 }
3856
3857 chip->ecc_strength_ds = ecc->ecc_bits;
3858 chip->ecc_step_ds = 1 << ecc->codeword_size;
3859 ret = 0;
3860
3861ext_out:
3862 kfree(ep);
3863 return ret;
3864}
3865
3866static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3867{
3868 struct nand_chip *chip = mtd_to_nand(mtd);
3869 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3870
3871 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3872 feature);
3873}
3874
3875
3876
3877
3878static void nand_onfi_detect_micron(struct nand_chip *chip,
3879 struct nand_onfi_params *p)
3880{
3881 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3882
3883 if (le16_to_cpu(p->vendor_revision) < 1)
3884 return;
3885
3886 chip->read_retries = micron->read_retry_options;
3887 chip->setup_read_retry = nand_setup_read_retry_micron;
3888}
3889
3890
3891
3892
3893static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3894 int *busw)
3895{
3896 struct nand_onfi_params *p = &chip->onfi_params;
3897 char id[4];
3898 int i, ret, val;
3899
3900
3901 ret = nand_readid_op(chip, 0x20, id, sizeof(id));
3902 if (ret || strncmp(id, "ONFI", 4))
3903 return 0;
3904
3905 ret = nand_read_param_page_op(chip, 0, NULL, 0);
3906 if (ret)
3907 return 0;
3908
3909 for (i = 0; i < 3; i++) {
3910 ret = nand_read_data_op(chip, p, sizeof(*p), true);
3911 if (ret)
3912 return 0;
3913
3914 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3915 le16_to_cpu(p->crc)) {
3916 break;
3917 }
3918 }
3919
3920 if (i == 3) {
3921 pr_err("Could not find valid ONFI parameter page; aborting\n");
3922 return 0;
3923 }
3924
3925
3926 val = le16_to_cpu(p->revision);
3927 if (val & (1 << 5))
3928 chip->onfi_version = 23;
3929 else if (val & (1 << 4))
3930 chip->onfi_version = 22;
3931 else if (val & (1 << 3))
3932 chip->onfi_version = 21;
3933 else if (val & (1 << 2))
3934 chip->onfi_version = 20;
3935 else if (val & (1 << 1))
3936 chip->onfi_version = 10;
3937
3938 if (!chip->onfi_version) {
3939 pr_info("unsupported ONFI version: %d\n", val);
3940 return 0;
3941 }
3942
3943 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3944 sanitize_string(p->model, sizeof(p->model));
3945 if (!mtd->name)
3946 mtd->name = p->model;
3947
3948 mtd->writesize = le32_to_cpu(p->byte_per_page);
3949
3950
3951
3952
3953
3954
3955 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3956 mtd->erasesize *= mtd->writesize;
3957
3958 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3959
3960
3961 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3962 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3963 chip->bits_per_cell = p->bits_per_cell;
3964
3965 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3966 *busw = NAND_BUSWIDTH_16;
3967 else
3968 *busw = 0;
3969
3970 if (p->ecc_bits != 0xff) {
3971 chip->ecc_strength_ds = p->ecc_bits;
3972 chip->ecc_step_ds = 512;
3973 } else if (chip->onfi_version >= 21 &&
3974 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3975
3976
3977
3978
3979
3980
3981
3982 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3983 chip->cmdfunc = nand_command_lp;
3984
3985
3986 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3987 pr_warn("Failed to detect ONFI extended param page\n");
3988 } else {
3989 pr_warn("Could not retrieve ONFI ECC requirements\n");
3990 }
3991
3992 if (p->jedec_id == NAND_MFR_MICRON)
3993 nand_onfi_detect_micron(chip, p);
3994
3995 return 1;
3996}
3997#else
3998static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3999 int *busw)
4000{
4001 return 0;
4002}
4003#endif
4004
4005
4006
4007
4008static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
4009 int *busw)
4010{
4011 struct nand_jedec_params *p = &chip->jedec_params;
4012 struct jedec_ecc_info *ecc;
4013 char id[5];
4014 int i, val, ret;
4015
4016
4017 ret = nand_readid_op(chip, 0x40, id, sizeof(id));
4018 if (ret || strncmp(id, "JEDEC", sizeof(id)))
4019 return 0;
4020
4021 ret = nand_read_param_page_op(chip, 0x40, NULL, 0);
4022 if (ret)
4023 return 0;
4024
4025 for (i = 0; i < 3; i++) {
4026 ret = nand_read_data_op(chip, p, sizeof(*p), true);
4027 if (ret)
4028 return 0;
4029
4030 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
4031 le16_to_cpu(p->crc))
4032 break;
4033 }
4034
4035 if (i == 3) {
4036 pr_err("Could not find valid JEDEC parameter page; aborting\n");
4037 return 0;
4038 }
4039
4040
4041 val = le16_to_cpu(p->revision);
4042 if (val & (1 << 2))
4043 chip->jedec_version = 10;
4044 else if (val & (1 << 1))
4045 chip->jedec_version = 1;
4046
4047 if (!chip->jedec_version) {
4048 pr_info("unsupported JEDEC version: %d\n", val);
4049 return 0;
4050 }
4051
4052 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
4053 sanitize_string(p->model, sizeof(p->model));
4054 if (!mtd->name)
4055 mtd->name = p->model;
4056
4057 mtd->writesize = le32_to_cpu(p->byte_per_page);
4058
4059
4060 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
4061 mtd->erasesize *= mtd->writesize;
4062
4063 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4064
4065
4066 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
4067 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
4068 chip->bits_per_cell = p->bits_per_cell;
4069
4070 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
4071 *busw = NAND_BUSWIDTH_16;
4072 else
4073 *busw = 0;
4074
4075
4076 ecc = &p->ecc_info[0];
4077
4078 if (ecc->codeword_size >= 9) {
4079 chip->ecc_strength_ds = ecc->ecc_bits;
4080 chip->ecc_step_ds = 1 << ecc->codeword_size;
4081 } else {
4082 pr_warn("Invalid codeword size\n");
4083 }
4084
4085 return 1;
4086}
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099static int nand_id_has_period(u8 *id_data, int arrlen, int period)
4100{
4101 int i, j;
4102 for (i = 0; i < period; i++)
4103 for (j = i + period; j < arrlen; j += period)
4104 if (id_data[i] != id_data[j])
4105 return 0;
4106 return 1;
4107}
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117static int nand_id_len(u8 *id_data, int arrlen)
4118{
4119 int last_nonzero, period;
4120
4121
4122 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
4123 if (id_data[last_nonzero])
4124 break;
4125
4126
4127 if (last_nonzero < 0)
4128 return 0;
4129
4130
4131 for (period = 1; period < arrlen; period++)
4132 if (nand_id_has_period(id_data, arrlen, period))
4133 break;
4134
4135
4136 if (period < arrlen)
4137 return period;
4138
4139
4140 if (last_nonzero < arrlen - 1)
4141 return last_nonzero + 1;
4142
4143
4144 return arrlen;
4145}
4146
4147
4148static int nand_get_bits_per_cell(u8 cellinfo)
4149{
4150 int bits;
4151
4152 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
4153 bits >>= NAND_CI_CELLTYPE_SHIFT;
4154 return bits + 1;
4155}
4156
4157
4158
4159
4160
4161
4162static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
4163 u8 id_data[8], int *busw)
4164{
4165 int extid, id_len;
4166
4167 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4168
4169 extid = id_data[3];
4170
4171 id_len = nand_id_len(id_data, 8);
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
4183 !nand_is_slc(chip) && id_data[5] != 0x00) {
4184
4185 mtd->writesize = 2048 << (extid & 0x03);
4186 extid >>= 2;
4187
4188 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
4189 case 1:
4190 mtd->oobsize = 128;
4191 break;
4192 case 2:
4193 mtd->oobsize = 218;
4194 break;
4195 case 3:
4196 mtd->oobsize = 400;
4197 break;
4198 case 4:
4199 mtd->oobsize = 436;
4200 break;
4201 case 5:
4202 mtd->oobsize = 512;
4203 break;
4204 case 6:
4205 mtd->oobsize = 640;
4206 break;
4207 case 7:
4208 default:
4209 mtd->oobsize = 1024;
4210 break;
4211 }
4212 extid >>= 2;
4213
4214 mtd->erasesize = (128 * 1024) <<
4215 (((extid >> 1) & 0x04) | (extid & 0x03));
4216 *busw = 0;
4217 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
4218 !nand_is_slc(chip)) {
4219 unsigned int tmp;
4220
4221
4222 mtd->writesize = 2048 << (extid & 0x03);
4223 extid >>= 2;
4224
4225 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
4226 case 0:
4227 mtd->oobsize = 128;
4228 break;
4229 case 1:
4230 mtd->oobsize = 224;
4231 break;
4232 case 2:
4233 mtd->oobsize = 448;
4234 break;
4235 case 3:
4236 mtd->oobsize = 64;
4237 break;
4238 case 4:
4239 mtd->oobsize = 32;
4240 break;
4241 case 5:
4242 mtd->oobsize = 16;
4243 break;
4244 default:
4245 mtd->oobsize = 640;
4246 break;
4247 }
4248 extid >>= 2;
4249
4250 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
4251 if (tmp < 0x03)
4252 mtd->erasesize = (128 * 1024) << tmp;
4253 else if (tmp == 0x03)
4254 mtd->erasesize = 768 * 1024;
4255 else
4256 mtd->erasesize = (64 * 1024) << tmp;
4257 *busw = 0;
4258 } else {
4259
4260 mtd->writesize = 1024 << (extid & 0x03);
4261 extid >>= 2;
4262
4263 mtd->oobsize = (8 << (extid & 0x01)) *
4264 (mtd->writesize >> 9);
4265 extid >>= 2;
4266
4267 mtd->erasesize = (64 * 1024) << (extid & 0x03);
4268 extid >>= 2;
4269
4270 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
4281 nand_is_slc(chip) &&
4282 (id_data[5] & 0x7) == 0x6 &&
4283 !(id_data[4] & 0x80) ) {
4284 mtd->oobsize = 32 * mtd->writesize >> 9;
4285 }
4286
4287 }
4288}
4289
4290
4291
4292
4293
4294
4295static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
4296 struct nand_flash_dev *type, u8 id_data[8],
4297 int *busw)
4298{
4299 int maf_id = id_data[0];
4300
4301 mtd->erasesize = type->erasesize;
4302 mtd->writesize = type->pagesize;
4303 mtd->oobsize = mtd->writesize / 32;
4304 *busw = type->options & NAND_BUSWIDTH_16;
4305
4306
4307 chip->bits_per_cell = 1;
4308
4309
4310
4311
4312
4313
4314
4315 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
4316 && id_data[6] == 0x00 && id_data[7] == 0x00
4317 && mtd->writesize == 512) {
4318 mtd->erasesize = 128 * 1024;
4319 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
4320 }
4321}
4322
4323
4324
4325
4326
4327
4328static void nand_decode_bbm_options(struct mtd_info *mtd,
4329 struct nand_chip *chip, u8 id_data[8])
4330{
4331 int maf_id = id_data[0];
4332
4333
4334 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
4335 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
4336 else
4337 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
4338
4339
4340
4341
4342
4343
4344
4345 if (!nand_is_slc(chip) &&
4346 (maf_id == NAND_MFR_SAMSUNG ||
4347 maf_id == NAND_MFR_HYNIX))
4348 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
4349 else if ((nand_is_slc(chip) &&
4350 (maf_id == NAND_MFR_SAMSUNG ||
4351 maf_id == NAND_MFR_HYNIX ||
4352 maf_id == NAND_MFR_TOSHIBA ||
4353 maf_id == NAND_MFR_AMD ||
4354 maf_id == NAND_MFR_MACRONIX)) ||
4355 (mtd->writesize == 2048 &&
4356 maf_id == NAND_MFR_MICRON))
4357 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
4358}
4359
4360static inline bool is_full_id_nand(struct nand_flash_dev *type)
4361{
4362 return type->id_len;
4363}
4364
4365static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
4366 struct nand_flash_dev *type, u8 *id_data, int *busw)
4367{
4368 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
4369 mtd->writesize = type->pagesize;
4370 mtd->erasesize = type->erasesize;
4371 mtd->oobsize = type->oobsize;
4372
4373 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4374 chip->chipsize = (uint64_t)type->chipsize << 20;
4375 chip->options |= type->options;
4376 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
4377 chip->ecc_step_ds = NAND_ECC_STEP(type);
4378 chip->onfi_timing_mode_default =
4379 type->onfi_timing_mode_default;
4380
4381 *busw = type->options & NAND_BUSWIDTH_16;
4382
4383 if (!mtd->name)
4384 mtd->name = type->name;
4385
4386 return true;
4387 }
4388 return false;
4389}
4390
4391
4392
4393
4394struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
4395 struct nand_chip *chip,
4396 int *maf_id, int *dev_id,
4397 struct nand_flash_dev *type)
4398{
4399 int busw, ret;
4400 int maf_idx;
4401 u8 id_data[8];
4402
4403
4404
4405
4406
4407 ret = nand_reset(chip, 0);
4408 if (ret)
4409 return ERR_PTR(ret);
4410
4411
4412 chip->select_chip(mtd, 0);
4413
4414
4415 ret = nand_readid_op(chip, 0, id_data, 2);
4416 if (ret)
4417 return ERR_PTR(ret);
4418
4419
4420 *maf_id = id_data[0];
4421 *dev_id = id_data[1];
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431 ret = nand_readid_op(chip, 0, id_data, 8);
4432 if (ret)
4433 return ERR_PTR(ret);
4434
4435 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
4436 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
4437 *maf_id, *dev_id, id_data[0], id_data[1]);
4438 return ERR_PTR(-ENODEV);
4439 }
4440
4441 if (!type)
4442 type = nand_flash_ids;
4443
4444 for (; type->name != NULL; type++) {
4445 if (is_full_id_nand(type)) {
4446 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
4447 goto ident_done;
4448 } else if (*dev_id == type->dev_id) {
4449 break;
4450 }
4451 }
4452
4453 chip->onfi_version = 0;
4454 if (!type->name || !type->pagesize) {
4455
4456 if (nand_flash_detect_onfi(mtd, chip, &busw))
4457 goto ident_done;
4458
4459
4460 if (nand_flash_detect_jedec(mtd, chip, &busw))
4461 goto ident_done;
4462 }
4463
4464 if (!type->name)
4465 return ERR_PTR(-ENODEV);
4466
4467 if (!mtd->name)
4468 mtd->name = type->name;
4469
4470 chip->chipsize = (uint64_t)type->chipsize << 20;
4471
4472 if (!type->pagesize) {
4473
4474 nand_decode_ext_id(mtd, chip, id_data, &busw);
4475 } else {
4476 nand_decode_id(mtd, chip, type, id_data, &busw);
4477 }
4478
4479 chip->options |= type->options;
4480
4481
4482
4483
4484
4485 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
4486 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
4487ident_done:
4488
4489
4490 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
4491 if (nand_manuf_ids[maf_idx].id == *maf_id)
4492 break;
4493 }
4494
4495 if (chip->options & NAND_BUSWIDTH_AUTO) {
4496 WARN_ON(chip->options & NAND_BUSWIDTH_16);
4497 chip->options |= busw;
4498 nand_set_defaults(chip, busw);
4499 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
4500
4501
4502
4503
4504 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4505 *maf_id, *dev_id);
4506 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
4507 pr_warn("bus width %d instead %d bit\n",
4508 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
4509 busw ? 16 : 8);
4510 return ERR_PTR(-EINVAL);
4511 }
4512
4513 nand_decode_bbm_options(mtd, chip, id_data);
4514
4515
4516 chip->page_shift = ffs(mtd->writesize) - 1;
4517
4518 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
4519
4520 chip->bbt_erase_shift = chip->phys_erase_shift =
4521 ffs(mtd->erasesize) - 1;
4522 if (chip->chipsize & 0xffffffff)
4523 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
4524 else {
4525 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
4526 chip->chip_shift += 32 - 1;
4527 }
4528
4529 if (chip->chip_shift - chip->page_shift > 16)
4530 chip->options |= NAND_ROW_ADDR_3;
4531
4532 chip->badblockbits = 8;
4533 chip->erase = single_erase;
4534
4535
4536 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
4537 chip->cmdfunc = nand_command_lp;
4538
4539 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4540 *maf_id, *dev_id);
4541
4542#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
4543 if (chip->onfi_version)
4544 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4545 chip->onfi_params.model);
4546 else if (chip->jedec_version)
4547 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4548 chip->jedec_params.model);
4549 else
4550 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4551 type->name);
4552#else
4553 if (chip->jedec_version)
4554 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4555 chip->jedec_params.model);
4556 else
4557 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4558 type->name);
4559
4560 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4561 type->name);
4562#endif
4563
4564 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4565 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
4566 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
4567 return type;
4568}
4569EXPORT_SYMBOL(nand_get_flash_type);
4570
4571#if CONFIG_IS_ENABLED(OF_CONTROL)
4572
4573static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node)
4574{
4575 int ret, ecc_mode = -1, ecc_strength, ecc_step;
4576 const char *str;
4577
4578 ret = ofnode_read_s32_default(node, "nand-bus-width", -1);
4579 if (ret == 16)
4580 chip->options |= NAND_BUSWIDTH_16;
4581
4582 if (ofnode_read_bool(node, "nand-on-flash-bbt"))
4583 chip->bbt_options |= NAND_BBT_USE_FLASH;
4584
4585 str = ofnode_read_string(node, "nand-ecc-mode");
4586 if (str) {
4587 if (!strcmp(str, "none"))
4588 ecc_mode = NAND_ECC_NONE;
4589 else if (!strcmp(str, "soft"))
4590 ecc_mode = NAND_ECC_SOFT;
4591 else if (!strcmp(str, "hw"))
4592 ecc_mode = NAND_ECC_HW;
4593 else if (!strcmp(str, "hw_syndrome"))
4594 ecc_mode = NAND_ECC_HW_SYNDROME;
4595 else if (!strcmp(str, "hw_oob_first"))
4596 ecc_mode = NAND_ECC_HW_OOB_FIRST;
4597 else if (!strcmp(str, "soft_bch"))
4598 ecc_mode = NAND_ECC_SOFT_BCH;
4599 }
4600
4601 ecc_strength = ofnode_read_s32_default(node,
4602 "nand-ecc-strength", -1);
4603 ecc_step = ofnode_read_s32_default(node,
4604 "nand-ecc-step-size", -1);
4605
4606 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
4607 (!(ecc_step >= 0) && ecc_strength >= 0)) {
4608 pr_err("must set both strength and step size in DT\n");
4609 return -EINVAL;
4610 }
4611
4612 if (ecc_mode >= 0)
4613 chip->ecc.mode = ecc_mode;
4614
4615 if (ecc_strength >= 0)
4616 chip->ecc.strength = ecc_strength;
4617
4618 if (ecc_step > 0)
4619 chip->ecc.size = ecc_step;
4620
4621 if (ofnode_read_bool(node, "nand-ecc-maximize"))
4622 chip->ecc.options |= NAND_ECC_MAXIMIZE;
4623
4624 return 0;
4625}
4626#else
4627static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node)
4628{
4629 return 0;
4630}
4631#endif
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4644 struct nand_flash_dev *table)
4645{
4646 int i, nand_maf_id, nand_dev_id;
4647 struct nand_chip *chip = mtd_to_nand(mtd);
4648 struct nand_flash_dev *type;
4649 int ret;
4650
4651 if (ofnode_valid(chip->flash_node)) {
4652 ret = nand_dt_init(mtd, chip, chip->flash_node);
4653 if (ret)
4654 return ret;
4655 }
4656
4657
4658 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
4659
4660
4661 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4662 &nand_dev_id, table);
4663
4664 if (IS_ERR(type)) {
4665 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
4666 pr_warn("No NAND device found\n");
4667 chip->select_chip(mtd, -1);
4668 return PTR_ERR(type);
4669 }
4670
4671
4672 ret = nand_init_data_interface(chip);
4673 if (ret)
4674 return ret;
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684 ret = nand_setup_data_interface(chip, 0);
4685 if (ret)
4686 return ret;
4687
4688 chip->select_chip(mtd, -1);
4689
4690
4691 for (i = 1; i < maxchips; i++) {
4692 u8 id[2];
4693
4694
4695 nand_reset(chip, i);
4696
4697 chip->select_chip(mtd, i);
4698
4699 nand_readid_op(chip, 0, id, sizeof(id));
4700
4701
4702 if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
4703 chip->select_chip(mtd, -1);
4704 break;
4705 }
4706 chip->select_chip(mtd, -1);
4707 }
4708
4709#ifdef DEBUG
4710 if (i > 1)
4711 pr_info("%d chips detected\n", i);
4712#endif
4713
4714
4715 chip->numchips = i;
4716 mtd->size = i * chip->chipsize;
4717
4718 return 0;
4719}
4720EXPORT_SYMBOL(nand_scan_ident);
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732int nand_check_ecc_caps(struct nand_chip *chip,
4733 const struct nand_ecc_caps *caps, int oobavail)
4734{
4735 struct mtd_info *mtd = nand_to_mtd(chip);
4736 const struct nand_ecc_step_info *stepinfo;
4737 int preset_step = chip->ecc.size;
4738 int preset_strength = chip->ecc.strength;
4739 int nsteps, ecc_bytes;
4740 int i, j;
4741
4742 if (WARN_ON(oobavail < 0))
4743 return -EINVAL;
4744
4745 if (!preset_step || !preset_strength)
4746 return -ENODATA;
4747
4748 nsteps = mtd->writesize / preset_step;
4749
4750 for (i = 0; i < caps->nstepinfos; i++) {
4751 stepinfo = &caps->stepinfos[i];
4752
4753 if (stepinfo->stepsize != preset_step)
4754 continue;
4755
4756 for (j = 0; j < stepinfo->nstrengths; j++) {
4757 if (stepinfo->strengths[j] != preset_strength)
4758 continue;
4759
4760 ecc_bytes = caps->calc_ecc_bytes(preset_step,
4761 preset_strength);
4762 if (WARN_ON_ONCE(ecc_bytes < 0))
4763 return ecc_bytes;
4764
4765 if (ecc_bytes * nsteps > oobavail) {
4766 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4767 preset_step, preset_strength);
4768 return -ENOSPC;
4769 }
4770
4771 chip->ecc.bytes = ecc_bytes;
4772
4773 return 0;
4774 }
4775 }
4776
4777 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4778 preset_step, preset_strength);
4779
4780 return -ENOTSUPP;
4781}
4782EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794int nand_match_ecc_req(struct nand_chip *chip,
4795 const struct nand_ecc_caps *caps, int oobavail)
4796{
4797 struct mtd_info *mtd = nand_to_mtd(chip);
4798 const struct nand_ecc_step_info *stepinfo;
4799 int req_step = chip->ecc_step_ds;
4800 int req_strength = chip->ecc_strength_ds;
4801 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
4802 int best_step, best_strength, best_ecc_bytes;
4803 int best_ecc_bytes_total = INT_MAX;
4804 int i, j;
4805
4806 if (WARN_ON(oobavail < 0))
4807 return -EINVAL;
4808
4809
4810 if (!req_step || !req_strength)
4811 return -ENOTSUPP;
4812
4813
4814 req_corr = mtd->writesize / req_step * req_strength;
4815
4816 for (i = 0; i < caps->nstepinfos; i++) {
4817 stepinfo = &caps->stepinfos[i];
4818 step_size = stepinfo->stepsize;
4819
4820 for (j = 0; j < stepinfo->nstrengths; j++) {
4821 strength = stepinfo->strengths[j];
4822
4823
4824
4825
4826
4827
4828 if (step_size < req_step && strength < req_strength)
4829 continue;
4830
4831 if (mtd->writesize % step_size)
4832 continue;
4833
4834 nsteps = mtd->writesize / step_size;
4835
4836 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4837 if (WARN_ON_ONCE(ecc_bytes < 0))
4838 continue;
4839 ecc_bytes_total = ecc_bytes * nsteps;
4840
4841 if (ecc_bytes_total > oobavail ||
4842 strength * nsteps < req_corr)
4843 continue;
4844
4845
4846
4847
4848
4849 if (ecc_bytes_total < best_ecc_bytes_total) {
4850 best_ecc_bytes_total = ecc_bytes_total;
4851 best_step = step_size;
4852 best_strength = strength;
4853 best_ecc_bytes = ecc_bytes;
4854 }
4855 }
4856 }
4857
4858 if (best_ecc_bytes_total == INT_MAX)
4859 return -ENOTSUPP;
4860
4861 chip->ecc.size = best_step;
4862 chip->ecc.strength = best_strength;
4863 chip->ecc.bytes = best_ecc_bytes;
4864
4865 return 0;
4866}
4867EXPORT_SYMBOL_GPL(nand_match_ecc_req);
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878int nand_maximize_ecc(struct nand_chip *chip,
4879 const struct nand_ecc_caps *caps, int oobavail)
4880{
4881 struct mtd_info *mtd = nand_to_mtd(chip);
4882 const struct nand_ecc_step_info *stepinfo;
4883 int step_size, strength, nsteps, ecc_bytes, corr;
4884 int best_corr = 0;
4885 int best_step = 0;
4886 int best_strength, best_ecc_bytes;
4887 int i, j;
4888
4889 if (WARN_ON(oobavail < 0))
4890 return -EINVAL;
4891
4892 for (i = 0; i < caps->nstepinfos; i++) {
4893 stepinfo = &caps->stepinfos[i];
4894 step_size = stepinfo->stepsize;
4895
4896
4897 if (chip->ecc.size && step_size != chip->ecc.size)
4898 continue;
4899
4900 for (j = 0; j < stepinfo->nstrengths; j++) {
4901 strength = stepinfo->strengths[j];
4902
4903 if (mtd->writesize % step_size)
4904 continue;
4905
4906 nsteps = mtd->writesize / step_size;
4907
4908 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4909 if (WARN_ON_ONCE(ecc_bytes < 0))
4910 continue;
4911
4912 if (ecc_bytes * nsteps > oobavail)
4913 continue;
4914
4915 corr = strength * nsteps;
4916
4917
4918
4919
4920
4921 if (corr > best_corr ||
4922 (corr == best_corr && step_size > best_step)) {
4923 best_corr = corr;
4924 best_step = step_size;
4925 best_strength = strength;
4926 best_ecc_bytes = ecc_bytes;
4927 }
4928 }
4929 }
4930
4931 if (!best_corr)
4932 return -ENOTSUPP;
4933
4934 chip->ecc.size = best_step;
4935 chip->ecc.strength = best_strength;
4936 chip->ecc.bytes = best_ecc_bytes;
4937
4938 return 0;
4939}
4940EXPORT_SYMBOL_GPL(nand_maximize_ecc);
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956static bool nand_ecc_strength_good(struct mtd_info *mtd)
4957{
4958 struct nand_chip *chip = mtd_to_nand(mtd);
4959 struct nand_ecc_ctrl *ecc = &chip->ecc;
4960 int corr, ds_corr;
4961
4962 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4963
4964 return true;
4965
4966
4967
4968
4969
4970 corr = (mtd->writesize * ecc->strength) / ecc->size;
4971 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4972
4973 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4974}
4975
4976static bool invalid_ecc_page_accessors(struct nand_chip *chip)
4977{
4978 struct nand_ecc_ctrl *ecc = &chip->ecc;
4979
4980 if (nand_standard_page_accessors(ecc))
4981 return false;
4982
4983
4984
4985
4986
4987
4988
4989 return (!ecc->read_page || !ecc->write_page ||
4990 !ecc->read_page_raw || !ecc->write_page_raw ||
4991 (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
4992 (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
4993 ecc->hwctl && ecc->calculate));
4994}
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004int nand_scan_tail(struct mtd_info *mtd)
5005{
5006 int i;
5007 struct nand_chip *chip = mtd_to_nand(mtd);
5008 struct nand_ecc_ctrl *ecc = &chip->ecc;
5009 struct nand_buffers *nbuf;
5010
5011
5012 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
5013 !(chip->bbt_options & NAND_BBT_USE_FLASH));
5014
5015 if (invalid_ecc_page_accessors(chip)) {
5016 pr_err("Invalid ECC page accessors setup\n");
5017 return -EINVAL;
5018 }
5019
5020 if (!(chip->options & NAND_OWN_BUFFERS)) {
5021 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
5022 chip->buffers = nbuf;
5023 } else {
5024 if (!chip->buffers)
5025 return -ENOMEM;
5026 }
5027
5028
5029 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
5030
5031
5032
5033
5034 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
5035 switch (mtd->oobsize) {
5036#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
5037 case 8:
5038 ecc->layout = &nand_oob_8;
5039 break;
5040 case 16:
5041 ecc->layout = &nand_oob_16;
5042 break;
5043 case 64:
5044 ecc->layout = &nand_oob_64;
5045 break;
5046 case 128:
5047 ecc->layout = &nand_oob_128;
5048 break;
5049#endif
5050 default:
5051 pr_warn("No oob scheme defined for oobsize %d\n",
5052 mtd->oobsize);
5053 BUG();
5054 }
5055 }
5056
5057 if (!chip->write_page)
5058 chip->write_page = nand_write_page;
5059
5060
5061
5062
5063
5064
5065 switch (ecc->mode) {
5066 case NAND_ECC_HW_OOB_FIRST:
5067
5068 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
5069 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
5070 BUG();
5071 }
5072 if (!ecc->read_page)
5073 ecc->read_page = nand_read_page_hwecc_oob_first;
5074
5075 case NAND_ECC_HW:
5076
5077 if (!ecc->read_page)
5078 ecc->read_page = nand_read_page_hwecc;
5079 if (!ecc->write_page)
5080 ecc->write_page = nand_write_page_hwecc;
5081 if (!ecc->read_page_raw)
5082 ecc->read_page_raw = nand_read_page_raw;
5083 if (!ecc->write_page_raw)
5084 ecc->write_page_raw = nand_write_page_raw;
5085 if (!ecc->read_oob)
5086 ecc->read_oob = nand_read_oob_std;
5087 if (!ecc->write_oob)
5088 ecc->write_oob = nand_write_oob_std;
5089 if (!ecc->read_subpage)
5090 ecc->read_subpage = nand_read_subpage;
5091 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
5092 ecc->write_subpage = nand_write_subpage_hwecc;
5093
5094 case NAND_ECC_HW_SYNDROME:
5095 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
5096 (!ecc->read_page ||
5097 ecc->read_page == nand_read_page_hwecc ||
5098 !ecc->write_page ||
5099 ecc->write_page == nand_write_page_hwecc)) {
5100 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
5101 BUG();
5102 }
5103
5104 if (!ecc->read_page)
5105 ecc->read_page = nand_read_page_syndrome;
5106 if (!ecc->write_page)
5107 ecc->write_page = nand_write_page_syndrome;
5108 if (!ecc->read_page_raw)
5109 ecc->read_page_raw = nand_read_page_raw_syndrome;
5110 if (!ecc->write_page_raw)
5111 ecc->write_page_raw = nand_write_page_raw_syndrome;
5112 if (!ecc->read_oob)
5113 ecc->read_oob = nand_read_oob_syndrome;
5114 if (!ecc->write_oob)
5115 ecc->write_oob = nand_write_oob_syndrome;
5116
5117 if (mtd->writesize >= ecc->size) {
5118 if (!ecc->strength) {
5119 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
5120 BUG();
5121 }
5122 break;
5123 }
5124 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
5125 ecc->size, mtd->writesize);
5126 ecc->mode = NAND_ECC_SOFT;
5127
5128 case NAND_ECC_SOFT:
5129 ecc->calculate = nand_calculate_ecc;
5130 ecc->correct = nand_correct_data;
5131 ecc->read_page = nand_read_page_swecc;
5132 ecc->read_subpage = nand_read_subpage;
5133 ecc->write_page = nand_write_page_swecc;
5134 ecc->read_page_raw = nand_read_page_raw;
5135 ecc->write_page_raw = nand_write_page_raw;
5136 ecc->read_oob = nand_read_oob_std;
5137 ecc->write_oob = nand_write_oob_std;
5138 if (!ecc->size)
5139 ecc->size = 256;
5140 ecc->bytes = 3;
5141 ecc->strength = 1;
5142 break;
5143
5144 case NAND_ECC_SOFT_BCH:
5145 if (!mtd_nand_has_bch()) {
5146 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
5147 BUG();
5148 }
5149 ecc->calculate = nand_bch_calculate_ecc;
5150 ecc->correct = nand_bch_correct_data;
5151 ecc->read_page = nand_read_page_swecc;
5152 ecc->read_subpage = nand_read_subpage;
5153 ecc->write_page = nand_write_page_swecc;
5154 ecc->read_page_raw = nand_read_page_raw;
5155 ecc->write_page_raw = nand_write_page_raw;
5156 ecc->read_oob = nand_read_oob_std;
5157 ecc->write_oob = nand_write_oob_std;
5158
5159
5160
5161
5162
5163 if (!ecc->size && (mtd->oobsize >= 64)) {
5164 ecc->size = 512;
5165 ecc->strength = 4;
5166 }
5167
5168
5169 ecc->bytes = 0;
5170 ecc->priv = nand_bch_init(mtd);
5171 if (!ecc->priv) {
5172 pr_warn("BCH ECC initialization failed!\n");
5173 BUG();
5174 }
5175 break;
5176
5177 case NAND_ECC_NONE:
5178 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
5179 ecc->read_page = nand_read_page_raw;
5180 ecc->write_page = nand_write_page_raw;
5181 ecc->read_oob = nand_read_oob_std;
5182 ecc->read_page_raw = nand_read_page_raw;
5183 ecc->write_page_raw = nand_write_page_raw;
5184 ecc->write_oob = nand_write_oob_std;
5185 ecc->size = mtd->writesize;
5186 ecc->bytes = 0;
5187 ecc->strength = 0;
5188 break;
5189
5190 default:
5191 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
5192 BUG();
5193 }
5194
5195
5196 if (!ecc->read_oob_raw)
5197 ecc->read_oob_raw = ecc->read_oob;
5198 if (!ecc->write_oob_raw)
5199 ecc->write_oob_raw = ecc->write_oob;
5200
5201
5202
5203
5204
5205 mtd->oobavail = 0;
5206 if (ecc->layout) {
5207 for (i = 0; ecc->layout->oobfree[i].length; i++)
5208 mtd->oobavail += ecc->layout->oobfree[i].length;
5209 }
5210
5211
5212 if (!nand_ecc_strength_good(mtd))
5213 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
5214 mtd->name);
5215
5216
5217
5218
5219
5220 ecc->steps = mtd->writesize / ecc->size;
5221 if (ecc->steps * ecc->size != mtd->writesize) {
5222 pr_warn("Invalid ECC parameters\n");
5223 BUG();
5224 }
5225 ecc->total = ecc->steps * ecc->bytes;
5226
5227
5228 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
5229 switch (ecc->steps) {
5230 case 2:
5231 mtd->subpage_sft = 1;
5232 break;
5233 case 4:
5234 case 8:
5235 case 16:
5236 mtd->subpage_sft = 2;
5237 break;
5238 }
5239 }
5240 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
5241
5242
5243 chip->state = FL_READY;
5244
5245
5246 chip->pagebuf = -1;
5247
5248
5249 switch (ecc->mode) {
5250 case NAND_ECC_SOFT:
5251 case NAND_ECC_SOFT_BCH:
5252 if (chip->page_shift > 9)
5253 chip->options |= NAND_SUBPAGE_READ;
5254 break;
5255
5256 default:
5257 break;
5258 }
5259
5260
5261 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
5262 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
5263 MTD_CAP_NANDFLASH;
5264 mtd->_erase = nand_erase;
5265 mtd->_panic_write = panic_nand_write;
5266 mtd->_read_oob = nand_read_oob;
5267 mtd->_write_oob = nand_write_oob;
5268 mtd->_sync = nand_sync;
5269 mtd->_lock = NULL;
5270 mtd->_unlock = NULL;
5271 mtd->_block_isreserved = nand_block_isreserved;
5272 mtd->_block_isbad = nand_block_isbad;
5273 mtd->_block_markbad = nand_block_markbad;
5274 mtd->writebufsize = mtd->writesize;
5275
5276
5277 mtd->ecclayout = ecc->layout;
5278 mtd->ecc_strength = ecc->strength;
5279 mtd->ecc_step_size = ecc->size;
5280
5281
5282
5283
5284
5285 if (!mtd->bitflip_threshold)
5286 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
5287
5288 return 0;
5289}
5290EXPORT_SYMBOL(nand_scan_tail);
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301int nand_scan(struct mtd_info *mtd, int maxchips)
5302{
5303 int ret;
5304
5305 ret = nand_scan_ident(mtd, maxchips, NULL);
5306 if (!ret)
5307 ret = nand_scan_tail(mtd);
5308 return ret;
5309}
5310EXPORT_SYMBOL(nand_scan);
5311
5312MODULE_LICENSE("GPL");
5313MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
5314MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
5315MODULE_DESCRIPTION("Generic NAND flash driver code");
5316