1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2014 Broadcom Corporation. 4 */ 5 6#ifndef _BCM_SF2_ETH_GMAC_H_ 7#define _BCM_SF2_ETH_GMAC_H_ 8 9#define BCM_SF2_ETH_MAC_NAME "gmac" 10 11#ifndef ETHHW_PORT_INT 12#define ETHHW_PORT_INT 8 13#endif 14 15#define GMAC0_REG_BASE 0x18042000 16#define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE 17#define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020) 18#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100) 19#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188) 20 21 22#define GMAC_DMA_PTR_OFFSET 0x04 23#define GMAC_DMA_ADDR_LOW_OFFSET 0x08 24#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c 25#define GMAC_DMA_STATUS0_OFFSET 0x10 26#define GMAC_DMA_STATUS1_OFFSET 0x14 27 28#define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200) 29#define GMAC0_DMA_TX_PTR_ADDR \ 30 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) 31#define GMAC0_DMA_TX_ADDR_LOW_ADDR \ 32 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) 33#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \ 34 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) 35#define GMAC0_DMA_TX_STATUS0_ADDR \ 36 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) 37#define GMAC0_DMA_TX_STATUS1_ADDR \ 38 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) 39 40#define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220) 41#define GMAC0_DMA_RX_PTR_ADDR \ 42 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) 43#define GMAC0_DMA_RX_ADDR_LOW_ADDR \ 44 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) 45#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \ 46 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) 47#define GMAC0_DMA_RX_STATUS0_ADDR \ 48 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) 49#define GMAC0_DMA_RX_STATUS1_ADDR \ 50 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) 51 52#define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808) 53#define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c) 54#define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810) 55#define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814) 56 57#define GMAC0_IRL_FRAMECOUNT_SHIFT 24 58 59/* transmit channel control */ 60/* transmit enable */ 61#define D64_XC_XE 0x00000001 62/* transmit suspend request */ 63#define D64_XC_SE 0x00000002 64/* parity check disable */ 65#define D64_XC_PD 0x00000800 66/* BurstLen bits */ 67#define D64_XC_BL_MASK 0x001C0000 68#define D64_XC_BL_SHIFT 18 69 70/* transmit descriptor table pointer */ 71/* last valid descriptor */ 72#define D64_XP_LD_MASK 0x00001fff 73 74/* transmit channel status */ 75/* transmit state */ 76#define D64_XS0_XS_MASK 0xf0000000 77#define D64_XS0_XS_SHIFT 28 78#define D64_XS0_XS_DISABLED 0x00000000 79#define D64_XS0_XS_ACTIVE 0x10000000 80#define D64_XS0_XS_IDLE 0x20000000 81#define D64_XS0_XS_STOPPED 0x30000000 82#define D64_XS0_XS_SUSP 0x40000000 83 84/* receive channel control */ 85/* receive enable */ 86#define D64_RC_RE 0x00000001 87/* address extension bits */ 88#define D64_RC_AE 0x00030000 89/* overflow continue */ 90#define D64_RC_OC 0x00000400 91/* parity check disable */ 92#define D64_RC_PD 0x00000800 93/* receive frame offset */ 94#define D64_RC_RO_MASK 0x000000fe 95#define D64_RC_RO_SHIFT 1 96/* BurstLen bits */ 97#define D64_RC_BL_MASK 0x001C0000 98#define D64_RC_BL_SHIFT 18 99 100/* flags for dma controller */ 101/* partity enable */ 102#define DMA_CTRL_PEN (1 << 0) 103/* rx overflow continue */ 104#define DMA_CTRL_ROC (1 << 1) 105 106/* receive descriptor table pointer */ 107/* last valid descriptor */ 108#define D64_RP_LD_MASK 0x00001fff 109 110/* receive channel status */ 111/* current descriptor pointer */ 112#define D64_RS0_CD_MASK 0x00001fff 113/* receive state */ 114#define D64_RS0_RS_MASK 0xf0000000 115#define D64_RS0_RS_SHIFT 28 116#define D64_RS0_RS_DISABLED 0x00000000 117#define D64_RS0_RS_ACTIVE 0x10000000 118#define D64_RS0_RS_IDLE 0x20000000 119#define D64_RS0_RS_STOPPED 0x30000000 120#define D64_RS0_RS_SUSP 0x40000000 121 122/* descriptor control flags 1 */ 123/* core specific flags */ 124#define D64_CTRL_COREFLAGS 0x0ff00000 125/* end of descriptor table */ 126#define D64_CTRL1_EOT ((uint32_t)1 << 28) 127/* interrupt on completion */ 128#define D64_CTRL1_IOC ((uint32_t)1 << 29) 129/* end of frame */ 130#define D64_CTRL1_EOF ((uint32_t)1 << 30) 131/* start of frame */ 132#define D64_CTRL1_SOF ((uint32_t)1 << 31) 133 134/* descriptor control flags 2 */ 135/* buffer byte count. real data len must <= 16KB */ 136#define D64_CTRL2_BC_MASK 0x00007fff 137/* address extension bits */ 138#define D64_CTRL2_AE 0x00030000 139#define D64_CTRL2_AE_SHIFT 16 140/* parity bit */ 141#define D64_CTRL2_PARITY 0x00040000 142/* control flags in the range [27:20] are core-specific and not defined here */ 143#define D64_CTRL_CORE_MASK 0x0ff00000 144 145#define DC_MROR 0x00000010 146#define PC_MTE 0x00800000 147 148/* command config */ 149#define CC_TE 0x00000001 150#define CC_RE 0x00000002 151#define CC_ES_MASK 0x0000000c 152#define CC_ES_SHIFT 2 153#define CC_PROM 0x00000010 154#define CC_PAD_EN 0x00000020 155#define CC_CF 0x00000040 156#define CC_PF 0x00000080 157#define CC_RPI 0x00000100 158#define CC_TAI 0x00000200 159#define CC_HD 0x00000400 160#define CC_HD_SHIFT 10 161#define CC_SR 0x00002000 162#define CC_ML 0x00008000 163#define CC_AE 0x00400000 164#define CC_CFE 0x00800000 165#define CC_NLC 0x01000000 166#define CC_RL 0x02000000 167#define CC_RED 0x04000000 168#define CC_PE 0x08000000 169#define CC_TPI 0x10000000 170#define CC_AT 0x20000000 171 172#define I_PDEE 0x00000400 173#define I_PDE 0x00000800 174#define I_DE 0x00001000 175#define I_RDU 0x00002000 176#define I_RFO 0x00004000 177#define I_XFU 0x00008000 178#define I_RI 0x00010000 179#define I_XI0 0x01000000 180#define I_XI1 0x02000000 181#define I_XI2 0x04000000 182#define I_XI3 0x08000000 183#define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU) 184#define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS) 185 186#define I_INTMASK 0x0f01fcff 187 188#define CHIP_DRU_BASE 0x0301d000 189#define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc) 190#define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194) 191 192#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0 193#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13 194 195#define AMAC0_IDM_RESET_ADDR 0x18110800 196#define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408 197#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6 198#define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5 199#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3 200 201#define CHIPA_CHIP_ID_ADDR 0x18000000 202#define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF) 203#define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF) 204#define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF) 205 206#define GMAC_MII_CTRL_ADDR 0x18002000 207#define GMAC_MII_CTRL_BYP_SHIFT 10 208#define GMAC_MII_CTRL_EXT_SHIFT 9 209#define GMAC_MII_DATA_ADDR 0x18002004 210#define GMAC_MII_DATA_READ_CMD 0x60020000 211#define GMAC_MII_DATA_WRITE_CMD 0x50020000 212#define GMAC_MII_BUSY_SHIFT 8 213#define GMAC_MII_PHY_ADDR_SHIFT 23 214#define GMAC_MII_PHY_REG_SHIFT 18 215 216#define GMAC_RESET_DELAY 2 217#define HWRXOFF 30 218#define MAXNAMEL 8 219#define NUMTXQ 4 220 221int gmac_add(struct eth_device *dev); 222 223#endif /* _BCM_SF2_ETH_GMAC_H_ */ 224