LXR uboot/drivers/net/fm/t1024.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/* Copyright 2014 Freescale Semiconductor, Inc.
   3 *
   4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   5 */
   6
   7#include <common.h>
   8#include <phy.h>
   9#include <fm_eth.h>
  10#include <asm/immap_85xx.h>
  11#include <asm/fsl_serdes.h>
  12
  13u32 port_to_devdisr[] = {
  14        [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  15        [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  16        [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  17        [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  18        [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */
  19};
  20
  21static int is_device_disabled(enum fm_port port)
  22{
  23        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  24        u32 devdisr2 = in_be32(&gur->devdisr2);
  25
  26        return port_to_devdisr[port] & devdisr2;
  27}
  28
  29void fman_disable_port(enum fm_port port)
  30{
  31        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  32
  33        setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  34}
  35
  36phy_interface_t fman_port_enet_if(enum fm_port port)
  37{
  38        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  39        u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  40
  41        if (is_device_disabled(port))
  42                return PHY_INTERFACE_MODE_NONE;
  43
  44        if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
  45                return PHY_INTERFACE_MODE_XGMII;
  46
  47        if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  48                FSL_CORENET_RCWSR13_EC2_RGMII) &&
  49                                        (!is_serdes_configured(QSGMII_FM1_A)))
  50                return PHY_INTERFACE_MODE_RGMII;
  51
  52        if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
  53                FSL_CORENET_RCWSR13_EC1_RGMII) &&
  54                                        (!is_serdes_configured(QSGMII_FM1_A)))
  55                return PHY_INTERFACE_MODE_RGMII;
  56
  57        /* handle SGMII */
  58        switch (port) {
  59        case FM1_DTSEC1:
  60        case FM1_DTSEC2:
  61        case FM1_DTSEC3:
  62                if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  63                        return PHY_INTERFACE_MODE_SGMII;
  64                else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
  65                         + port - FM1_DTSEC1))
  66                        return PHY_INTERFACE_MODE_2500BASEX;
  67                break;
  68        default:
  69                break;
  70        }
  71
  72        /* handle QSGMII */
  73        switch (port) {
  74        case FM1_DTSEC1:
  75        case FM1_DTSEC2:
  76        case FM1_DTSEC3:
  77        case FM1_DTSEC4:
  78                /* check lane A on SerDes1 */
  79                if (is_serdes_configured(QSGMII_FM1_A))
  80                        return PHY_INTERFACE_MODE_QSGMII;
  81                break;
  82        default:
  83                break;
  84        }
  85
  86        return PHY_INTERFACE_MODE_NONE;
  87}
  88