LXR uboot/drivers/net/fsl

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * ENETC ethernet controller driver
   4 * Copyright 2017-2021 NXP
   5 */
   6
   7#ifndef _ENETC_H
   8#define _ENETC_H
   9
  10#include <linux/bitops.h>
  11#define enetc_dbg(dev, fmt, args...)    debug("%s:" fmt, dev->name, ##args)
  12
  13/* PCI function IDs */
  14#define PCI_DEVICE_ID_ENETC_ETH         0xE100
  15#define PCI_DEVICE_ID_ENETC_MDIO        0xEE01
  16
  17/* ENETC Ethernet controller registers */
  18/* Station interface register offsets */
  19#define ENETC_SIMR              0x000
  20#define  ENETC_SIMR_EN          BIT(31)
  21#define ENETC_SICAR0            0x040
  22/* write cache cfg: snoop, no allocate, data & BD coherent */
  23#define  ENETC_SICAR_WR_CFG     0x6767
  24/* read cache cfg: coherent copy, look up, don't alloc in cache */
  25#define  ENETC_SICAR_RD_CFG     0x27270000
  26#define ENETC_SIROCT            0x300
  27#define ENETC_SIRFRM            0x308
  28#define ENETC_SITOCT            0x320
  29#define ENETC_SITFRM            0x328
  30
  31/* Rx/Tx Buffer Descriptor Ring registers */
  32enum enetc_bdr_type {TX, RX};
  33#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
  34#define ENETC_BDR_IDX_MASK      0xffff
  35
  36/* Rx BDR reg offsets */
  37#define ENETC_RBMR              0x00
  38#define  ENETC_RBMR_EN          BIT(31)
  39#define ENETC_RBBSR             0x08
  40/* initial consumer index for Rx BDR */
  41#define ENETC_RBCIR             0x0c
  42#define ENETC_RBBAR0            0x10
  43#define ENETC_RBBAR1            0x14
  44#define ENETC_RBPIR             0x18
  45#define ENETC_RBLENR            0x20
  46
  47/* Tx BDR reg offsets */
  48#define ENETC_TBMR              0x00
  49#define  ENETC_TBMR_EN          BIT(31)
  50#define ENETC_TBBAR0            0x10
  51#define ENETC_TBBAR1            0x14
  52#define ENETC_TBPIR             0x18
  53#define ENETC_TBCIR             0x1c
  54#define ENETC_TBLENR            0x20
  55
  56/* Port registers offset */
  57#define ENETC_PORT_REGS_OFF             0x10000
  58
  59/* Port registers */
  60#define ENETC_PMR                       0x0000
  61#define  ENETC_PMR_SI0_EN               BIT(16)
  62#define ENETC_PSIPMMR                   0x0018
  63#define ENETC_PSIPMAR0                  0x0100
  64#define ENETC_PSIPMAR1                  0x0104
  65#define ENETC_PCAPR0                    0x0900
  66#define  ENETC_PCAPRO_MDIO              BIT(11)
  67#define ENETC_PSICFGR(n)                (0x0940 + (n) * 0x10)
  68#define  ENETC_PSICFGR_SET_TXBDR(val)   ((val) & 0xff)
  69#define  ENETC_PSICFGR_SET_RXBDR(val)   (((val) & 0xff) << 16)
  70/* MAC configuration */
  71#define ENETC_PM_CC                     0x8008
  72#define  ENETC_PM_CC_DEFAULT            0x0810
  73#define  ENETC_PM_CC_RX_TX_EN           0x8813
  74#define ENETC_PM_MAXFRM                 0x8014
  75#define  ENETC_RX_MAXFRM_SIZE           PKTSIZE_ALIGN
  76#define ENETC_PM_IMDIO_BASE             0x8030
  77#define ENETC_PM_IF_MODE                0x8300
  78#define  ENETC_PM_IF_MODE_RG            BIT(2)
  79#define  ENETC_PM_IF_MODE_AN_ENA        BIT(15)
  80#define  ENETC_PM_IFM_SSP_MASK          GENMASK(14, 13)
  81#define  ENETC_PM_IFM_SSP_1000          (2 << 13)
  82#define  ENETC_PM_IFM_SSP_100           (0 << 13)
  83#define  ENETC_PM_IFM_SSP_10            (1 << 13)
  84#define  ENETC_PM_IFM_FULL_DPX          BIT(12)
  85#define  ENETC_PM_IF_IFMODE_MASK        GENMASK(1, 0)
  86
  87/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
  88#define ENETC_BD_CNT            CONFIG_SYS_RX_ETH_BUFFER
  89#define ENETC_BD_ALIGN          128
  90
  91/* single pair of Rx/Tx rings */
  92#define ENETC_RX_BDR_CNT        1
  93#define ENETC_TX_BDR_CNT        1
  94#define ENETC_RX_BDR_ID         0
  95#define ENETC_TX_BDR_ID         0
  96
  97/* Tx buffer descriptor */
  98struct enetc_tx_bd {
  99        __le64 addr;
 100        __le16 buf_len;
 101        __le16 frm_len;
 102        __le16 err_csum;
 103        __le16 flags;
 104};
 105
 106#define ENETC_TXBD_FLAGS_F      BIT(15)
 107#define ENETC_POLL_TRIES        32000
 108
 109/* Rx buffer descriptor */
 110union enetc_rx_bd {
 111        /* SW provided BD format */
 112        struct {
 113                __le64 addr;
 114                u8 reserved[8];
 115        } w;
 116
 117        /* ENETC returned BD format */
 118        struct {
 119                __le16 inet_csum;
 120                __le16 parse_summary;
 121                __le32 rss_hash;
 122                __le16 buf_len;
 123                __le16 vlan_opt;
 124                union {
 125                        struct {
 126                                __le16 flags;
 127                                __le16 error;
 128                        };
 129                        __le32 lstatus;
 130                };
 131        } r;
 132};
 133
 134#define ENETC_RXBD_STATUS_R(status)             (((status) >> 30) & 0x1)
 135#define ENETC_RXBD_STATUS_F(status)             (((status) >> 31) & 0x1)
 136#define ENETC_RXBD_STATUS_ERRORS(status)        (((status) >> 16) & 0xff)
 137#define ENETC_RXBD_STATUS(flags)                ((flags) << 16)
 138
 139/* Tx/Rx ring info */
 140struct bd_ring {
 141        void *cons_idx;
 142        void *prod_idx;
 143        /* next BD index to use */
 144        int next_prod_idx;
 145        int next_cons_idx;
 146        int bd_count;
 147};
 148
 149/* ENETC private structure */
 150struct enetc_priv {
 151        struct enetc_tx_bd *enetc_txbd;
 152        union enetc_rx_bd *enetc_rxbd;
 153
 154        void *regs_base; /* base ENETC registers */
 155        void *port_regs; /* base ENETC port registers */
 156
 157        /* Rx/Tx buffer descriptor rings info */
 158        struct bd_ring tx_bdr;
 159        struct bd_ring rx_bdr;
 160
 161        int if_type;
 162        struct mii_dev imdio;
 163        struct phy_device *phy;
 164};
 165
 166/* register accessors */
 167#define enetc_read_reg(x)       readl((x))
 168#define enetc_write_reg(x, val) writel((val), (x))
 169#define enetc_read(priv, off)   enetc_read_reg((priv)->regs_base + (off))
 170#define enetc_write(priv, off, v) \
 171                        enetc_write_reg((priv)->regs_base + (off), v)
 172
 173/* port register accessors */
 174#define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
 175#define enetc_read_port(priv, off) \
 176                        enetc_read_reg(enetc_port_regs((priv), (off)))
 177#define enetc_write_port(priv, off, v) \
 178                        enetc_write_reg(enetc_port_regs((priv), (off)), v)
 179
 180/* BDR register accessors, see ENETC_BDR() */
 181#define enetc_bdr_read(priv, t, n, off) \
 182                        enetc_read(priv, ENETC_BDR(t, n, off))
 183#define enetc_bdr_write(priv, t, n, off, val) \
 184                        enetc_write(priv, ENETC_BDR(t, n, off), val)
 185
 186/* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */
 187#define ENETC_PCS_PHY_ADDR      0
 188
 189/* PCS registers */
 190#define ENETC_PCS_CR                    0x00
 191#define  ENETC_PCS_CR_RESET_AN          0x1200
 192#define  ENETC_PCS_CR_DEF_VAL           0x0140
 193#define  ENETC_PCS_CR_RST               BIT(15)
 194#define ENETC_PCS_DEV_ABILITY           0x04
 195#define  ENETC_PCS_DEV_ABILITY_SGMII    0x4001
 196#define  ENETC_PCS_DEV_ABILITY_SXGMII   0x5001
 197#define ENETC_PCS_LINK_TIMER1           0x12
 198#define  ENETC_PCS_LINK_TIMER1_VAL      0x06a0
 199#define ENETC_PCS_LINK_TIMER2           0x13
 200#define  ENETC_PCS_LINK_TIMER2_VAL      0x0003
 201#define ENETC_PCS_IF_MODE               0x14
 202#define  ENETC_PCS_IF_MODE_SGMII        BIT(0)
 203#define  ENETC_PCS_IF_MODE_SGMII_AN     BIT(1)
 204#define  ENETC_PCS_IF_MODE_SPEED_1G     BIT(3)
 205
 206/* PCS replicator block for USXGMII */
 207#define ENETC_PCS_DEVAD_REPL            0x1f
 208
 209#define ENETC_PCS_REPL_LINK_TIMER_1     0x12
 210#define  ENETC_PCS_REPL_LINK_TIMER_1_DEF        0x0003
 211#define ENETC_PCS_REPL_LINK_TIMER_2     0x13
 212#define  ENETC_PCS_REPL_LINK_TIMER_2_DEF        0x06a0
 213
 214/* ENETC external MDIO registers */
 215#define ENETC_MDIO_BASE         0x1c00
 216#define ENETC_MDIO_CFG          0x00
 217#define  ENETC_EMDIO_CFG_C22    0x00809508
 218#define  ENETC_EMDIO_CFG_C45    0x00809548
 219#define  ENETC_EMDIO_CFG_RD_ER  BIT(1)
 220#define  ENETC_EMDIO_CFG_BSY    BIT(0)
 221#define ENETC_MDIO_CTL          0x04
 222#define  ENETC_MDIO_CTL_READ    BIT(15)
 223#define ENETC_MDIO_DATA         0x08
 224#define ENETC_MDIO_STAT         0x0c
 225
 226#define ENETC_MDIO_READ_ERR     0xffff
 227
 228struct enetc_mdio_priv {
 229        void *regs_base;
 230};
 231
 232/*
 233 * these functions are implemented by ENETC_MDIO and are re-used by ENETC driver
 234 * to drive serdes / internal SoC PHYs
 235 */
 236int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
 237                         int reg);
 238int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
 239                          int reg, u16 val);
 240
 241/* sets up primary MAC addresses in DT/IERB */
 242void fdt_fixup_enetc_mac(void *blob);
 243
 244#endif /* _ENETC_H */
 245