LXR uboot/drivers/net/mscc_eswitch/ocelot

   1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2/*
   3 * Copyright (c) 2018 Microsemi Corporation
   4 */
   5
   6#include <common.h>
   7#include <config.h>
   8#include <dm.h>
   9#include <log.h>
  10#include <malloc.h>
  11#include <dm/of_access.h>
  12#include <dm/of_addr.h>
  13#include <fdt_support.h>
  14#include <linux/bitops.h>
  15#include <linux/io.h>
  16#include <linux/ioport.h>
  17#include <miiphy.h>
  18#include <net.h>
  19#include <wait_bit.h>
  20
  21#include "mscc_xfer.h"
  22#include "mscc_mac_table.h"
  23#include "mscc_miim.h"
  24
  25#define PHY_CFG                         0x0
  26#define PHY_CFG_ENA                             0xF
  27#define PHY_CFG_COMMON_RST                      BIT(4)
  28#define PHY_CFG_RST                             (0xF << 5)
  29#define PHY_STAT                        0x4
  30#define PHY_STAT_SUPERVISOR_COMPLETE            BIT(0)
  31
  32#define ANA_PORT_VLAN_CFG(x)            (0x7000 + 0x100 * (x))
  33#define         ANA_PORT_VLAN_CFG_AWARE_ENA     BIT(20)
  34#define         ANA_PORT_VLAN_CFG_POP_CNT(x)    ((x) << 18)
  35#define ANA_PORT_PORT_CFG(x)            (0x7070 + 0x100 * (x))
  36#define         ANA_PORT_PORT_CFG_RECV_ENA      BIT(6)
  37#define ANA_PGID(x)                     (0x8c00 + 4 * (x))
  38
  39#define HSIO_ANA_SERDES1G_DES_CFG               0x4c
  40#define         HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)            ((x) << 1)
  41#define         HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x)             ((x) << 5)
  42#define         HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x)          ((x) << 8)
  43#define         HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x)           ((x) << 13)
  44#define HSIO_ANA_SERDES1G_IB_CFG                0x50
  45#define         HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x)       (x)
  46#define         HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x)             ((x) << 6)
  47#define         HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP        BIT(9)
  48#define         HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV             BIT(11)
  49#define         HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM           BIT(13)
  50#define         HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x)         ((x) << 24)
  51#define HSIO_ANA_SERDES1G_OB_CFG                0x54
  52#define         HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x)       (x)
  53#define         HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)            ((x) << 4)
  54#define         HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x)       ((x) << 10)
  55#define         HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)            ((x) << 13)
  56#define         HSIO_ANA_SERDES1G_OB_CFG_SLP(x)                 ((x) << 17)
  57#define HSIO_ANA_SERDES1G_SER_CFG               0x58
  58#define HSIO_ANA_SERDES1G_COMMON_CFG            0x5c
  59#define         HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE            BIT(0)
  60#define         HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE           BIT(18)
  61#define         HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST            BIT(31)
  62#define HSIO_ANA_SERDES1G_PLL_CFG               0x60
  63#define         HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA               BIT(7)
  64#define         HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x)      ((x) << 8)
  65#define         HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2           BIT(21)
  66#define HSIO_DIG_SERDES1G_DFT_CFG0              0x68
  67#define HSIO_DIG_SERDES1G_MISC_CFG              0x7c
  68#define         HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST             BIT(0)
  69#define HSIO_MCB_SERDES1G_CFG                   0x88
  70#define         HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT               BIT(31)
  71#define         HSIO_MCB_SERDES1G_CFG_ADDR(x)                   (x)
  72#define HSIO_HW_CFGSTAT_HW_CFG                  0x10c
  73
  74#define SYS_FRM_AGING                   0x574
  75#define         SYS_FRM_AGING_ENA               BIT(20)
  76
  77#define SYS_SYSTEM_RST_CFG              0x508
  78#define         SYS_SYSTEM_RST_MEM_INIT         BIT(0)
  79#define         SYS_SYSTEM_RST_MEM_ENA          BIT(1)
  80#define         SYS_SYSTEM_RST_CORE_ENA         BIT(2)
  81#define SYS_PORT_MODE(x)                (0x514 + 0x4 * (x))
  82#define         SYS_PORT_MODE_INCL_INJ_HDR(x)   ((x) << 3)
  83#define         SYS_PORT_MODE_INCL_INJ_HDR_M    GENMASK(4, 3)
  84#define         SYS_PORT_MODE_INCL_XTR_HDR(x)   ((x) << 1)
  85#define         SYS_PORT_MODE_INCL_XTR_HDR_M    GENMASK(2, 1)
  86#define SYS_PAUSE_CFG(x)                (0x608 + 0x4 * (x))
  87#define         SYS_PAUSE_CFG_PAUSE_ENA         BIT(0)
  88
  89#define QSYS_SWITCH_PORT_MODE(x)        (0x11234 + 0x4 * (x))
  90#define         QSYS_SWITCH_PORT_MODE_PORT_ENA  BIT(14)
  91#define QSYS_QMAP                       0x112d8
  92#define QSYS_EGR_NO_SHARING             0x1129c
  93
  94/* Port registers */
  95#define DEV_CLOCK_CFG                   0x0
  96#define DEV_CLOCK_CFG_LINK_SPEED_1000           1
  97#define DEV_MAC_ENA_CFG                 0x1c
  98#define         DEV_MAC_ENA_CFG_RX_ENA          BIT(4)
  99#define         DEV_MAC_ENA_CFG_TX_ENA          BIT(0)
 100
 101#define DEV_MAC_IFG_CFG                 0x30
 102#define         DEV_MAC_IFG_CFG_TX_IFG(x)       ((x) << 8)
 103#define         DEV_MAC_IFG_CFG_RX_IFG2(x)      ((x) << 4)
 104#define         DEV_MAC_IFG_CFG_RX_IFG1(x)      (x)
 105
 106#define PCS1G_CFG                       0x48
 107#define         PCS1G_MODE_CFG_SGMII_MODE_ENA   BIT(0)
 108#define PCS1G_MODE_CFG                  0x4c
 109#define         PCS1G_MODE_CFG_UNIDIR_MODE_ENA  BIT(4)
 110#define         PCS1G_MODE_CFG_SGMII_MODE_ENA   BIT(0)
 111#define PCS1G_SD_CFG                    0x50
 112#define PCS1G_ANEG_CFG                  0x54
 113#define         PCS1G_ANEG_CFG_ADV_ABILITY(x)   ((x) << 16)
 114
 115#define QS_XTR_GRP_CFG(x)               (4 * (x))
 116#define QS_XTR_GRP_CFG_MODE(x)                  ((x) << 2)
 117#define         QS_XTR_GRP_CFG_STATUS_WORD_POS  BIT(1)
 118#define         QS_XTR_GRP_CFG_BYTE_SWAP        BIT(0)
 119#define QS_INJ_GRP_CFG(x)               (0x24 + (x) * 4)
 120#define         QS_INJ_GRP_CFG_MODE(x)          ((x) << 2)
 121#define         QS_INJ_GRP_CFG_BYTE_SWAP        BIT(0)
 122
 123#define IFH_INJ_BYPASS          BIT(31)
 124#define IFH_TAG_TYPE_C          0
 125#define MAC_VID                 1
 126#define CPU_PORT                11
 127#define INTERNAL_PORT_MSK       0x2FF
 128#define IFH_LEN                 4
 129#define ETH_ALEN                6
 130#define PGID_BROADCAST          13
 131#define PGID_UNICAST            14
 132#define PGID_SRC                80
 133
 134static const char * const regs_names[] = {
 135        "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7",
 136        "port8", "port9", "port10", "sys", "rew", "qs", "hsio", "qsys", "ana",
 137};
 138
 139#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
 140#define MAX_PORT 11
 141
 142enum ocelot_ctrl_regs {
 143        SYS = MAX_PORT,
 144        REW,
 145        QS,
 146        HSIO,
 147        QSYS,
 148        ANA,
 149};
 150
 151#define OCELOT_MIIM_BUS_COUNT 2
 152
 153struct ocelot_phy_port_t {
 154        size_t phy_addr;
 155        struct mii_dev *bus;
 156        u8 serdes_index;
 157        u8 phy_mode;
 158};
 159
 160struct ocelot_private {
 161        void __iomem *regs[REGS_NAMES_COUNT];
 162        struct mii_dev *bus[OCELOT_MIIM_BUS_COUNT];
 163        struct ocelot_phy_port_t ports[MAX_PORT];
 164};
 165
 166static struct mscc_miim_dev miim[OCELOT_MIIM_BUS_COUNT];
 167static int miim_count = -1;
 168
 169static const unsigned long ocelot_regs_qs[] = {
 170        [MSCC_QS_XTR_RD] = 0x8,
 171        [MSCC_QS_XTR_FLUSH] = 0x18,
 172        [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
 173        [MSCC_QS_INJ_WR] = 0x2c,
 174        [MSCC_QS_INJ_CTRL] = 0x34,
 175};
 176
 177static const unsigned long ocelot_regs_ana_table[] = {
 178        [MSCC_ANA_TABLES_MACHDATA] = 0x8b34,
 179        [MSCC_ANA_TABLES_MACLDATA] = 0x8b38,
 180        [MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
 181};
 182
 183static void mscc_phy_reset(void)
 184{
 185        writel(0, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG);
 186        writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
 187               | PHY_CFG_ENA, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG);
 188        if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + PERF_PHY_CFG) +
 189                              PHY_STAT, PHY_STAT_SUPERVISOR_COMPLETE,
 190                              true, 2000, false)) {
 191                pr_err("Timeout in phy reset\n");
 192        }
 193}
 194
 195__weak void mscc_switch_reset(void)
 196{
 197}
 198
 199static void ocelot_stop(struct udevice *dev)
 200{
 201        mscc_switch_reset();
 202        mscc_phy_reset();
 203}
 204
 205static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
 206{
 207        int i;
 208
 209        /* map the 8 CPU extraction queues to CPU port 11 */
 210        writel(0, priv->regs[QSYS] + QSYS_QMAP);
 211
 212        for (i = 0; i <= 1; i++) {
 213                /*
 214                 * Do byte-swap and expect status after last data word
 215                 * Extraction: Mode: manual extraction) | Byte_swap
 216                 */
 217                writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
 218                       priv->regs[QS] + QS_XTR_GRP_CFG(i));
 219                /*
 220                 * Injection: Mode: manual extraction | Byte_swap
 221                 */
 222                writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
 223                       priv->regs[QS] + QS_INJ_GRP_CFG(i));
 224        }
 225
 226        for (i = 0; i <= 1; i++)
 227                /* Enable IFH insertion/parsing on CPU ports */
 228                writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
 229                       SYS_PORT_MODE_INCL_XTR_HDR(1),
 230                       priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
 231        /*
 232         * Setup the CPU port as VLAN aware to support switching frames
 233         * based on tags
 234         */
 235        writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
 236               MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
 237
 238        /* Disable learning (only RECV_ENA must be set) */
 239        writel(ANA_PORT_PORT_CFG_RECV_ENA,
 240               priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
 241
 242        /* Enable switching to/from cpu port */
 243        setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
 244                     QSYS_SWITCH_PORT_MODE_PORT_ENA);
 245
 246        /* No pause on CPU port - not needed (off by default) */
 247        clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
 248                     SYS_PAUSE_CFG_PAUSE_ENA);
 249
 250        setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
 251}
 252
 253static void ocelot_port_init(struct ocelot_private *priv, int port)
 254{
 255        void __iomem *regs = priv->regs[port];
 256
 257        /* Enable PCS */
 258        writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
 259
 260        /* Disable Signal Detect */
 261        writel(0, regs + PCS1G_SD_CFG);
 262
 263        /* Enable MAC RX and TX */
 264        writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
 265               regs + DEV_MAC_ENA_CFG);
 266
 267        /* Clear sgmii_mode_ena */
 268        writel(0, regs + PCS1G_MODE_CFG);
 269
 270        /*
 271         * Clear sw_resolve_ena(bit 0) and set adv_ability to
 272         * something meaningful just in case
 273         */
 274        writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
 275
 276        /* Set MAC IFG Gaps */
 277        writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
 278               DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
 279
 280        /* Set link speed and release all resets */
 281        writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
 282
 283        /* Make VLAN aware for CPU traffic */
 284        writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
 285               MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
 286
 287        /* Enable the port in the core */
 288        setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
 289                     QSYS_SWITCH_PORT_MODE_PORT_ENA);
 290}
 291
 292static void serdes1g_write(void __iomem *base, u32 addr)
 293{
 294        u32 data;
 295
 296        writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
 297               HSIO_MCB_SERDES1G_CFG_ADDR(addr),
 298               base + HSIO_MCB_SERDES1G_CFG);
 299
 300        do {
 301                data = readl(base + HSIO_MCB_SERDES1G_CFG);
 302        } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
 303}
 304
 305static void serdes1g_setup(void __iomem *base, uint32_t addr,
 306                           phy_interface_t interface)
 307{
 308        writel(0x34, base + HSIO_HW_CFGSTAT_HW_CFG);
 309
 310        writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
 311        writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
 312        writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
 313               HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
 314               HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
 315               HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
 316               HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
 317               base + HSIO_ANA_SERDES1G_IB_CFG);
 318        writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
 319               HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
 320               HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
 321               HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
 322               base + HSIO_ANA_SERDES1G_DES_CFG);
 323        writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
 324               HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
 325               HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
 326               HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
 327               HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
 328               base + HSIO_ANA_SERDES1G_OB_CFG);
 329        writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
 330               HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
 331               base + HSIO_ANA_SERDES1G_COMMON_CFG);
 332        writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
 333               HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
 334               HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
 335               base + HSIO_ANA_SERDES1G_PLL_CFG);
 336        writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
 337               base + HSIO_DIG_SERDES1G_MISC_CFG);
 338
 339        serdes1g_write(base, addr);
 340
 341        writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
 342               HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
 343               HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
 344               base + HSIO_ANA_SERDES1G_COMMON_CFG);
 345        serdes1g_write(base, addr);
 346
 347        writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
 348        serdes1g_write(base, addr);
 349}
 350
 351static void serdes_setup(struct ocelot_private *priv)
 352{
 353        size_t mask;
 354        int i = 0;
 355
 356        for (i = 0; i < MAX_PORT; ++i) {
 357                if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff)
 358                        continue;
 359
 360                mask = BIT(priv->ports[i].serdes_index);
 361                serdes1g_setup(priv->regs[HSIO], mask,
 362                               priv->ports[i].phy_mode);
 363        }
 364}
 365
 366static int ocelot_switch_init(struct ocelot_private *priv)
 367{
 368        /* Reset switch & memories */
 369        writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
 370               priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
 371
 372        /* Wait to complete */
 373        if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
 374                              SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
 375                pr_err("Timeout in memory reset\n");
 376                return -EIO;
 377        }
 378
 379        /* Enable switch core */
 380        setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
 381                     SYS_SYSTEM_RST_CORE_ENA);
 382
 383        serdes_setup(priv);
 384        return 0;
 385}
 386
 387static int ocelot_initialize(struct ocelot_private *priv)
 388{
 389        int ret, i;
 390
 391        /* Initialize switch memories, enable core */
 392        ret = ocelot_switch_init(priv);
 393        if (ret)
 394                return ret;
 395        /*
 396         * Disable port-to-port by switching
 397         * Put fron ports in "port isolation modes" - i.e. they cant send
 398         * to other ports - via the PGID sorce masks.
 399         */
 400        for (i = 0; i < MAX_PORT; i++)
 401                writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
 402
 403        /* Flush queues */
 404        mscc_flush(priv->regs[QS], ocelot_regs_qs);
 405
 406        /* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
 407        writel(SYS_FRM_AGING_ENA | (20000000 / 65),
 408               priv->regs[SYS] + SYS_FRM_AGING);
 409
 410        for (i = 0; i < MAX_PORT; i++)
 411                ocelot_port_init(priv, i);
 412
 413        ocelot_cpu_capture_setup(priv);
 414
 415        debug("Ports enabled\n");
 416
 417        return 0;
 418}
 419
 420static int ocelot_write_hwaddr(struct udevice *dev)
 421{
 422        struct ocelot_private *priv = dev_get_priv(dev);
 423        struct eth_pdata *pdata = dev_get_plat(dev);
 424
 425        mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
 426                           pdata->enetaddr, PGID_UNICAST);
 427
 428        writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 429
 430        return 0;
 431}
 432
 433static int ocelot_start(struct udevice *dev)
 434{
 435        struct ocelot_private *priv = dev_get_priv(dev);
 436        struct eth_pdata *pdata = dev_get_plat(dev);
 437        const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
 438                                              0xff };
 439        int ret;
 440
 441        ret = ocelot_initialize(priv);
 442        if (ret)
 443                return ret;
 444
 445        /* Set MAC address tables entries for CPU redirection */
 446        mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac,
 447                           PGID_BROADCAST);
 448
 449        writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
 450               priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
 451
 452        /* It should be setup latter in ocelot_write_hwaddr */
 453        mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
 454                           pdata->enetaddr, PGID_UNICAST);
 455
 456        writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 457
 458        return 0;
 459}
 460
 461static int ocelot_send(struct udevice *dev, void *packet, int length)
 462{
 463        struct ocelot_private *priv = dev_get_priv(dev);
 464        u32 ifh[IFH_LEN];
 465        int port = BIT(0);      /* use port 0 */
 466        u32 *buf = packet;
 467
 468        /*
 469         * Generate the IFH for frame injection
 470         *
 471         * The IFH is a 128bit-value
 472         * bit 127: bypass the analyzer processing
 473         * bit 56-67: destination mask
 474         * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
 475         * bit 20-27: cpu extraction queue mask
 476         * bit 16: tag type 0: C-tag, 1: S-tag
 477         * bit 0-11: VID
 478         */
 479        ifh[0] = IFH_INJ_BYPASS;
 480        ifh[1] = (0xf00 & port) >> 8;
 481        ifh[2] = (0xff & port) << 24;
 482        ifh[3] = (IFH_TAG_TYPE_C << 16);
 483
 484        return mscc_send(priv->regs[QS], ocelot_regs_qs,
 485                         ifh, IFH_LEN, buf, length);
 486}
 487
 488static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
 489{
 490        struct ocelot_private *priv = dev_get_priv(dev);
 491        u32 *rxbuf = (u32 *)net_rx_packets[0];
 492        int byte_cnt;
 493
 494        byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN,
 495                             false);
 496
 497        *packetp = net_rx_packets[0];
 498
 499        return byte_cnt;
 500}
 501
 502static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
 503{
 504        int i = 0;
 505
 506        for (i = 0; i < OCELOT_MIIM_BUS_COUNT; ++i)
 507                if (miim[i].miim_base == base && miim[i].miim_size == size)
 508                        return miim[i].bus;
 509
 510        return NULL;
 511}
 512
 513static void add_port_entry(struct ocelot_private *priv, size_t index,
 514                           size_t phy_addr, struct mii_dev *bus,
 515                           u8 serdes_index, u8 phy_mode)
 516{
 517        priv->ports[index].phy_addr = phy_addr;
 518        priv->ports[index].bus = bus;
 519        priv->ports[index].serdes_index = serdes_index;
 520        priv->ports[index].phy_mode = phy_mode;
 521}
 522
 523static int external_bus(struct ocelot_private *priv, size_t port_index)
 524{
 525        return priv->ports[port_index].serdes_index != 0xff;
 526}
 527
 528static int ocelot_probe(struct udevice *dev)
 529{
 530        struct ocelot_private *priv = dev_get_priv(dev);
 531        int i, ret;
 532        struct resource res;
 533        phys_addr_t addr_base;
 534        unsigned long addr_size;
 535        ofnode eth_node, node, mdio_node;
 536        size_t phy_addr;
 537        struct mii_dev *bus;
 538        struct ofnode_phandle_args phandle;
 539        struct phy_device *phy;
 540
 541        if (!priv)
 542                return -EINVAL;
 543
 544        for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
 545                priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
 546                if (!priv->regs[i]) {
 547                        debug
 548                            ("Error can't get regs base addresses for %s\n",
 549                             regs_names[i]);
 550                        return -ENOMEM;
 551                }
 552        }
 553
 554        /* Initialize miim buses */
 555        memset(&miim, 0x0, sizeof(struct mscc_miim_dev) *
 556               OCELOT_MIIM_BUS_COUNT);
 557
 558        /* iterate all the ports and find out on which bus they are */
 559        i = 0;
 560        eth_node = dev_read_first_subnode(dev);
 561        for (node = ofnode_first_subnode(eth_node); ofnode_valid(node);
 562             node = ofnode_next_subnode(node)) {
 563                if (ofnode_read_resource(node, 0, &res))
 564                        return -ENOMEM;
 565                i = res.start;
 566
 567                ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
 568                                               &phandle);
 569
 570                /* Get phy address on mdio bus */
 571                if (ofnode_read_resource(phandle.node, 0, &res))
 572                        return -ENOMEM;
 573                phy_addr = res.start;
 574
 575                /* Get mdio node */
 576                mdio_node = ofnode_get_parent(phandle.node);
 577
 578                if (ofnode_read_resource(mdio_node, 0, &res))
 579                        return -ENOMEM;
 580
 581                addr_base = res.start;
 582                addr_size = res.end - res.start;
 583
 584                /* If the bus is new then create a new bus */
 585                if (!get_mdiobus(addr_base, addr_size))
 586                        priv->bus[miim_count] =
 587                                mscc_mdiobus_init(miim, &miim_count, addr_base,
 588                                                  addr_size);
 589
 590                /* Connect mdio bus with the port */
 591                bus = get_mdiobus(addr_base, addr_size);
 592
 593                /* Get serdes info */
 594                ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
 595                                                     3, 0, &phandle);
 596                if (ret)
 597                        add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff);
 598                else
 599                        add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
 600                                       phandle.args[2]);
 601        }
 602
 603        mscc_phy_reset();
 604
 605        for (i = 0; i < MAX_PORT; i++) {
 606                if (!priv->ports[i].bus)
 607                        continue;
 608
 609                phy = phy_connect(priv->ports[i].bus,
 610                                  priv->ports[i].phy_addr, dev,
 611                                  PHY_INTERFACE_MODE_NONE);
 612                if (phy && external_bus(priv, i))
 613                        board_phy_config(phy);
 614        }
 615
 616        return 0;
 617}
 618
 619static int ocelot_remove(struct udevice *dev)
 620{
 621        struct ocelot_private *priv = dev_get_priv(dev);
 622        int i;
 623
 624        for (i = 0; i < OCELOT_MIIM_BUS_COUNT; i++) {
 625                mdio_unregister(priv->bus[i]);
 626                mdio_free(priv->bus[i]);
 627        }
 628
 629        return 0;
 630}
 631
 632static const struct eth_ops ocelot_ops = {
 633        .start        = ocelot_start,
 634        .stop         = ocelot_stop,
 635        .send         = ocelot_send,
 636        .recv         = ocelot_recv,
 637        .write_hwaddr = ocelot_write_hwaddr,
 638};
 639
 640static const struct udevice_id mscc_ocelot_ids[] = {
 641        {.compatible = "mscc,vsc7514-switch"},
 642        { /* Sentinel */ }
 643};
 644
 645U_BOOT_DRIVER(ocelot) = {
 646        .name     = "ocelot-switch",
 647        .id       = UCLASS_ETH,
 648        .of_match = mscc_ocelot_ids,
 649        .probe    = ocelot_probe,
 650        .remove   = ocelot_remove,
 651        .ops      = &ocelot_ops,
 652        .priv_auto      = sizeof(struct ocelot_private),
 653        .plat_auto      = sizeof(struct eth_pdata),
 654};
 655